GB1483442A - Computing machine including a directly addressable memory arrangement - Google Patents

Abstract

1483442 Memory addressing STANDARD TELEPHONES & CABLES Ltd 9 Oct 1975 41431/75 Heading G4C The memory of a data processing system is divided into blocks associated with respective types of information and each containing not more than the number of locations addressable by the processor over direct address lines, there being switching means arranged in response to stored block select signals derived from an instruction to connect the direct address lines to the appropriate blocks in the appropriate sequence during execution of the instruction in a number of following processor cycles. It is assumed that no instruction requires more than five cycles for execution. In such a case during the first cycle the program block of memory is addressed by setting the output of shift register S/R to 1. The next instruction is then accessed and part of it used to address a programmed read only memory which supplies a four bit word to shift register S/R. The bits in the shift register are shifted out in successive cycles so as to apply the address signals fed over the direct address lines by the processor to the appropriate memory blocks in the appropriate sequence, a 1 selecting the program block and a 0 the data block. For instruction requiring less than the maximum number of cycles the relevant bit from the PROM may be l's to direct the address to the program block to allow the next instruction to be accessed or alternatively "don't care" bits in which case a reset signal is generated when an instruction is completed to load the shift register with l's for the same purpose. A second embodiment is exactly similar except that four memory blocks and two PROMs and shift registers are provided to produce a series of 2-bit groups to select among the four memory blocks.