GB1484380A - Data processing system - Google Patents

Abstract

1484380 Data processing system INTERNATIONAL STANDARD ELECTRIC CORP 10 Dec 1974 [17 Dec 1973] 53356/74 Heading G4A A data processing system has a memory divided into two portions storing instructions and data and only data respectively and is arranged to process instructions requiring a variable number of cycles, certain of the instructions requiring access to the memory, there being means settable to indicate which portion of the memory is to be accessed. The memory has portions MEMO storing instructions and data, the instructions being of two kinds, viz. memory reference instructions involving a memory access and control instructions, and MEM1 storing only data. Each instruction may require up to four cycles to execute. Four bi-stables BFCY, BICY, BACY and BBCY are set (the logic being given in the Specification) to define the required number of cycles for the current instruction. A bi-stable BNK is set by logic circuit LC (the logic being given in the Specification) to determine which portion of the memory is to be accessed. Two memory reference instructions are described, the first storing the current instruction address (from program counter P) in a predetermined portion of the memory (MEMO) and causing a program jump, and the other retrieving the stored address from MEM0 to resume the interrupted program. Various types of addressing, e.g. index addressing, are allowed, determined by decoder DEC2, in response to two bits in the current instruction.