JPH02165349A - Address tracing circuit - Google Patents

Abstract

PURPOSE:To effectively use an address tracing memory by specifying the range of execution addresses for collecting trace information by a microinstruction and storing only a necessary execution address in an address trace memory. CONSTITUTION:Two address comparators 8, 9 compare address information set up by a microinstruction with an execution address. When an address trace control circuit 10 outputs an address updating signal indicating whether the address of the address trace memory 6 is to be updated or not based upon the compared results of these comparators 8, 9, an address trace memory control circuit 11 controls the address of the memory 6 for storing the execution address based upon the address updating signal. Thus, the address trace memory 6 can be effectively used.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an address trace circuit that stores an execution address of a microinstruction in an address trace memory.

(Prior Art) A microprogram control device is provided with an address trace circuit that holds execution addresses of microinstructions of a microprogram in an address trace memory in order to efficiently debug the microprogram. In general, this address trace circuit stores the execution addresses of all executed microinstructions in the address trace memory when it is instructed to start collecting execution addresses, and stores execution address information in all address areas of the address trace memory. The operation ends when it is stored.

(Problems to be Solved by the Invention) As described above, the conventional address trace circuit stores all executed execution addresses in the address trace memory when the start of collection of execution addresses is instructed, and stores the executed addresses in the address trace memory. Since collection of execution addresses is stopped when address information is stored in all address areas of , there are cases where necessary execution addresses are not stored and unnecessary execution addresses are stored. Therefore, the address trace memory may be wasted. As described above, conventional address trace circuits have problems to be solved.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an address trace circuit that can effectively use address trace memory.

(Means for Solving the Problems) In order to achieve the above object, an address trace circuit of the present invention stores an execution address of a microinstruction in an address trace memory, and includes an address trace circuit that stores an execution address of a microinstruction in an address trace memory. a first comparison circuit and a second comparison circuit that compare information and the execution address; and updating the address of the address trace memory based on a comparison result between the first comparison circuit and the second comparison circuit. an address trace control circuit that outputs an address update signal indicating whether or not to execute the execution address; and an address that controls the address of the address trace memory that stores the execution address based on the address update signal output by the address trace control circuit. and a trace memory control circuit.

(Operation) In the address trace circuit of the present invention, the first comparison circuit and the second comparison circuit compare address information set by a microinstruction with an execution address. Then, when the address trace control circuit outputs an address update signal indicating whether or not to update the address of the address trace memory based on the comparison result between the first comparison circuit and the second comparison circuit, the address trace control circuit outputs an address update signal indicating whether or not to update the address of the address trace memory. A $ control circuit controls the address of the address trace memory that stores the execution address based on this address update signal.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, 1 is a control storage that stores microinstructions, and 2 is a control storage 1 in which the next microinstruction to be executed is usually incremented by 1 each time one microinstruction is executed. A microaddress register 3 specifies an address (execution address), a microaddress control circuit 3 changes the address output by the microaddress register 2 in the case of an unconditional branch instruction, a conditional branch instruction, etc., and a microaddress control circuit 4 reads out the address from the control storage 1. 5 is a decode circuit that decodes the microinstructions held in the microaddress register 2, 6 is an address trace memory that stores execution addresses, and 7 is a microinstruction register that is output by the microaddress control circuit 3. 8.9 is an address comparison circuit that compares the value of the address information set by the microinstruction with the value of the latch circuit 7 and outputs a comparison result; 10 is an address comparison circuit 9.9; An address trace control circuit outputs a trace collection signal indicating whether or not to trace an execution address based on the output information of 10, and 11 writes the address of the address trace memory 6 each time it receives this trace address memory update signal. This is an address trace memory control circuit that outputs a signal and then increments the address value by 1.

Next, the operation of the embodiment of the present invention will be explained with reference to FIG. Here, at address 0.1 of the control storage 1, an instruction that specifies the lower limit address (lower limit address) for collecting trace information in the address comparison circuit 8 is stored, and at address 1, an upper limit address for collecting trace information is stored. address (
The instructions specifying the upper limit address) are stored, and 2
It is assumed that microinstructions to be actually processed are stored after the address. When the microcontroller is initialized (reset) from the outside, microaddress register 2,
The microinstruction register 4, latch circuit 7 and address trace memory control circuit 11 are set to a predetermined value, for example "0".
, respectively, and the microaddress control circuit 3 is set to output the value of the microaddress register 2 as is.

Next, when the start of execution of a microinstruction is instructed, gi' OJ of the microaddress register 2 is added to the control storage 1 via the microaddress control circuit 3, and the control storage 1 is stored at address 0. microinstruction (address comparison circuit 8 mentioned above)
(instruction to set the lower limit address) is output. This read microinstruction is held in the microinstruction register 4, and when a part of this held microinstruction is decoded by the decoding circuit 5 and interpreted as an instruction to set an address in the address comparison circuit 8, trace The lower 1@address information of the collection range is sent to the address comparison circuit 8.

The address comparison circuit 8 internally holds this lower limit address information, for example, the rlooi address. When the execution of one micro-instruction is completed in this way, the micro-address register 2 increments its value by 1, so it becomes "1" and the above-mentioned micro-instruction stored at address 1 executes the micro-instruction at address 0. will be executed in the same way.

As a result, the upper limit address of the trace collection range, for example r200j, is set in the address comparison circuit 9.

When the settings in address comparison circuits 8 and 9 are completed, the microinstruction at address 2 is executed in the same manner as described above. At this time, the execution address "2" outputted by the microaddress control circuit 3
is also added to the latch circuit 7 and held in the launch circuit 7. The address comparison circuit 8.9 compares the value of the address information held internally with the value "2" of the execution address held in the latch circuit 7. As a result, the address comparison circuit 8 outputs that the value is smaller than the value of the lower limit address information held internally, and the address comparison circuit 9 also outputs that the value is smaller than the value of the upper limit address held internally. The address trace control circuit 10 determines that the current execution address is outside the trace collection range based on these output results, and does not output the l/race collection number. Therefore, the address trace memory control circuit 11 instructs the address trace memory 6 to write. Therefore, this execution address is not written to the address trace memory 6.

Since the microinstruction at address 3 is also executed in the same manner as described above, the execution address "F3" is not written to the address trace memory 6.

Now, the microinstruction is executed 111 times, and for example 15
When the instruction at address 0 is executed and the execution address r150J is held in the latch circuit 7, the address comparison circuit 8 outputs that it is larger than the lower limit address, and the address comparison circuit 9 outputs that it is smaller than the upper limit address. Based on these output results, the address trace control circuit 110 determines that the execution address '150J held in the latch circuit 7 is within the trace collection range, and issues a trace collection signal to the address trace memory control circuit 11. The address trace memory control circuit 11 that received the address trace memory 6 issues an instruction to write the value held in the latch circuit 7 to the address trace memory 6.
The address trace memory 6 that has received the write instruction to increase the address by +1 (therefore becomes rl) is held in the latch circuit 7 by the address trace memory control circuit 11 at the address (in this case "0"). When the instruction at the 0th order address 151, which stores the execution address r150J, is executed, 1 of the address trace memory 6 is executed as described above.
Execution address r151J is stored at address. Thereafter, other microinstructions are executed in the same manner. In this way, trace collection range (currently '100J~r200')
) is stored in the address trace memory 6 only when the microinstruction with the execution address up to ) is executed.

(Effects of the Invention) As explained above, the address trace circuit of the present invention specifies the range of execution addresses for which trace information is collected using microinstructions and stores only the necessary execution addresses in the address trace memory. Address trace memory can be used effectively. Furthermore, since the address trace memory can be used effectively, the memory capacity can be smaller than that of the conventional address trace memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. 1... Control storage, 2... Micro address register, 3... Micro address control circuit,
4... Micro instruction register, 5... Decode circuit, 6... Address trace memory, 7... Latch circuit, 8.9... Address ratio axis circuit, 10... Address trace control circuit, 11...Address trace memory control circuit.

Claims (1)

[Scope of Claims] An address trace circuit that stores an execution address of a microinstruction in an address trace memory, comprising a first comparison circuit and a second comparison circuit that compares address information set by the microinstruction with the execution address. an address trace control circuit that outputs an address update signal indicating whether or not to update the address of the address trace memory based on a comparison result between the first comparison circuit and the second comparison circuit; An address trace memory control circuit that controls an address of the address trace memory that stores the execution address based on an address update signal output by the address trace control circuit.