JPS62154036A - Address tracing circuit - Google Patents

Abstract

PURPOSE:To suppress the increase in a hardware quantity and a price by storing an executing address at a memory circuit where a micro-program is stored. CONSTITUTION:The executing address shown by a micro-address register 1 is latched through a micro-address control circuit 2 to a latch circuit 5. When a latched micro-instruction is a branch instruction after it is decoded by a decoding circuit 8, the storing command is outputted from the decoding circuit 8 to a tracing control circuit 3, a selecting circuit 4 and a memory circuit 6. By the storing command, a tracing control circuit 3 shows the address of the memory circuit 6 to be stored, the selecting circuit 4 selects the address of the memory circuit 6 shown from the tracing control part 3, and the memory circuit 6 stores the executing address latched to the latch circuit 5 to the address selected by the selecting circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to an address trace circuit, and more particularly to an address trace circuit that stores an execution address of a microinstruction in a memory.

Prior Art Conventionally, address tracing methods include a trace memory for storing execution addresses, and the execution addresses are stored in this memory.

This conventional address trace circuit has the disadvantage that it requires additional hardware called a trace memory circuit, which increases hardware costs and costs.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional circuits as described above, and an object of the present invention is to provide an address trace circuit that suppresses increases in hardware and cost.

Structure of the Invention The address trace circuit according to the present invention includes a memory circuit in which microinstructions are stored in advance, and an address that meets predetermined conditions among the addresses of microinstructions sequentially read out and executed from the memory circuit. and storage control means for determining the address and storing the address in the memory circuit.

Embodiment Next, an embodiment of an address trace circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of an address trace circuit according to the present invention.

In the figure, 1 is a micro address register that increments and latches the execution address by 1, and 2 is a memory circuit 6.
3 is a trace control circuit that increments the address of the trace address by 1 in response to a storage command from the decode circuit 8; 4 is an address to the memory circuit 6; a select circuit that selects a signal; 5 a latch circuit that latches an execution address; 6 a memory circuit for storing a microprogram and an execution address; 7 a microinstruction register that latches a microinstruction read from the memory circuit 6; is a decoder circuit that decodes the microinstruction latched in the microinstruction register 7.

The execution address indicated by micro address register 1 passes through micro address control circuit 2 and is latched into latch circuit 5. The microinstruction at the address indicated by the execution address is read out by the memory circuit 6 and latched into the microinstruction register 7.

The latched microinstruction is decoded by the decode circuit 8. At this time, if the microinstruction is not a branch instruction, the next execution address is read from the microaddress register 1, and the same processing as described above is repeated.

When the previous latched microinstruction is a branch instruction as a result of being decoded by the decoding circuit 8, a storage command is issued from the decoding circuit 8 to the trace control circuit 3, the select circuit 4, and the memory circuit 6.

With this storage command, the trace control circuit 3 indicates the address of the memory circuit 6 for storage, the select circuit 4 selects the address of the memory circuit 6 indicated by the trace control circuit 3, and the memory circuit 6 selects the address of the memory circuit 6 indicated by the trace control circuit 3. The execution address latched in is stored in the address selected by the select circuit 4.

After storing the execution address in the memory circuit 6, the trace control circuit 3 increments the address by one. Further, the decode circuit 8 sends a branch instruction instruction and a branch address to the micro address control circuit 2, and instructs the next execution address to indicate the branch address.

This operation allows the execution address at the time of execution of the branch instruction to be stored in the memory circuit 6.

Note that by changing the content decoded by the decoding circuit 8, it is also possible to store execution addresses in the memory circuit 6 only for other microinstructions.

As explained above, the present invention stores the execution address in the memory circuit in which the microprogram is stored, thereby eliminating the need for hardware such as memory for trace addresses, thereby reducing the increase in hardware and cost. It can be suppressed.

According to the address trace circuit of the present invention, the micro-
By storing the execution address in the memory circuit in which the program is stored, it is possible to suppress an increase in the amount of hardware and cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. Explanation of symbols of main parts 3...Trace control circuit 6...Memory circuit 8...Decode circuit

Claims (2)

[Claims] (1) A memory circuit in which a microinstruction is stored in advance, and an address of a microinstruction sequentially read out from the memory circuit and executed, is determined to be an address that meets a predetermined condition, and this address is transferred to the memory circuit. 1. An address trace circuit comprising storage control means for storing information in the circuit. (2) A patent characterized in that the storage control means has a determination means for determining whether or not the microinstruction is a branch instruction, and stores the executed address in the memory circuit only when the microinstruction is a branch instruction. Address in claim 1
trace circuit.