JPH03118648A - Effective application method of memory area for cpu control - Google Patents

Abstract

PURPOSE:To store software in a quantity larger than a memory area by reading the data stored in an address designated by a CPU in an address area designat ed by a 2nd decoder of a ROM which is designated by the output signal of an address decoder. CONSTITUTION:The program of a main routine is stored in a ROM 30-1 and the sample routines are stored in the areas (a) and (b) of a ROM 30-2. Then an access is given to the area (b) when the program of the subroutine is called by the program of the main routine. In such the case, the ROM to give an access is selected by the chip selection signal of the output of an address decoder 20. Then an address given from a CPU 10 is designated to the selected area (b) via an address bus and the stored data is read out to the corresponding address. As a result, the software can be stored in a memory area designated by the CPU 10 in a quantity larger than the memory area.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for effectively using a memory area within a range determined by the CPU in a circuit controlled by the CPU. The purpose is to provide a method for effectively utilizing memory areas in CPU control that can store the above information, and identifies the CPU, the read-only memory that is connected to the CPU and stores predetermined data, and the read-only memory that should be accessed. Input the signal from the CPU to
In a circuit having an address decoder that decodes and outputs the data, the address area of the read-only memory is divided into a predetermined number, the same address is given to each address area in the read-only memory, and the control from the CPU is performed. A second decoder is provided which receives and decodes the signal and accesses the address area specified by the CPU among the divided address areas of the read-only memory. The device is configured to read data stored at an address specified by the CPU in an address area specified by the decoder No. 2.

[Industrial application field]

The present invention relates to a method for effectively using a memory area determined by a CPU in a circuit controlled by a CPU such as a microcomputer.

In the above circuit, when the CPU address space is, for example, 64 bytes, and the software uses 80 bytes, when the system configuration does not have a very large memory area, it is used as a read-only memory (hereinafter referred to as ROM). There are cases where you want to have a wide address area. For this reason, there is a need for a method of effectively utilizing a memory area under CPU control that can store more information than the memory area determined by the CPU.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a conventional circuit.

In Figure 3, for example, there is a usable area of 64 bytes in CPU 1, and 32 of them have byte RO.
If it can be used as the area of ROM3-1.
Assume that 16 bytes are allocated to 3-2. For example, when accessing ROM3-1, the CPU 1 outputs a chip select signal for accessing the ROM3-1 to the address decoder 2, the address decoder 2 decodes this, and specifies ROM3-1 as the ROM3-1. It outputs a signal to access the ROM 3-1. At the same time C
ROM3-1.3-2 from PU1 via address bus
Outputs a signal specifying the address.

As a result of step 2, the data stored at the designated address in the ROM 3-1 is read out.

The reading of data stored in the ROM 3-2 is also carried out in the same manner as described above.

In this way, the data stored in the ROM was read out.

[Problem to be solved by the invention]

However, in the above-described circuit, each memory area in the CPU and the address in the ROM have a one-to-one correspondence. There is no problem if the specified range of memory area within the CPU has a sufficiently wide address area, but if the CPU's address space is, for example, 64 bytes, and the software uses 80 bytes. In addition, when the system configuration does not have a large memory area, there is a problem that the corresponding ROM address area becomes narrow.

Therefore, it is an object of the present invention to store (software) data in a predetermined memory area within a CPU that is greater than or equal to the memory area.
An object of the present invention is to provide a method for effectively utilizing a memory area in CPU control that can store information.

[Means to solve the problem]

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, a CPU 100 and a read-only memory 30 connected to the CPU and storing predetermined data.
0-1 to 300-n and an address decoder 200 that manually inputs, decodes and outputs a signal from the CPU to identify the read-only memory to be accessed. The same address is given to each address area within the same read-only memory.

500 inputs and decodes control signals from the CPU, and selects C from among the address areas divided in the read-only memory.
This is a second decoder provided to access the address area specified by the PU.

Then, data stored at an address specified by the CPU in the address area specified by the second decoder of the read-only memory specified by the output signal of the address decoder is read out.

[For production]

In FIG. 1, read-only memories 300-1 to 3
The address areas 00 to n are divided into a predetermined number, and the same address is given to each address area within the same read-only memory.

Then, the second decoder 500 of the read-only memory specified by the output signal of the address decoder 200
The data stored at the address specified by the CPU 100 in the address area specified by the CPU 100 is read out.

As a result, within the memory area determined by the CPU, it becomes possible to store more software than that memory area.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a circuit according to an embodiment of the present invention.

The same reference numerals refer to the same objects throughout the design.

In FIG. 2, for example, each ROM 30-2 has one
Assume that the area is divided into two areas (a) and 6 bytes each, and the same address is given to (a) and (b). and CP[I 10 to the above ROM 3
A control signal is applied to the decoder 50 to specify one of the two regions (a) or [present] of 0-2. For example, when one word consists of 16 bits of AO-A15, this control signal can be applied to two areas of ROM 30-2 by using the upper 1 bit (A15) to give "1" or 0. Specify either (a) or (1)).

For example, a main routine program is stored in the ROM 30-1, and subroutine programs are stored in two areas (a) and (b) of the ROM 30-2. When the main routine program calls a subroutine program, for example, when accessing area (b) of ROM 30-2, the ROM to be accessed is selected by the chip select signal output from the address decoder 20. 2) Select region (c) (in this case) based on the output of the decoder 50. After that, the CPU sends a message to the selected area @) via the address bus.
Specify an address from 10 and read out the data (program) stored at the corresponding address.

Incidentally, in the above example, the case where the address area of one ROM is divided into two parts is explained, but when one ROM is divided into, for example, four parts, the decoder 5 from the CPU 10
Upper 2 bits (A14, A15) as control signal to 0
use.

As a result, within the memory area determined by the CPU, it becomes possible to store more software than that memory area.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram showing the configuration of a circuit according to an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of a conventional circuit. In the figure, 100 is a CPU. 200 is an address decoder, 300-1 to 300-n are read-only memories, 5
00 indicates the second decoder. [Effects of the Invention] As described above, according to the present invention, it is possible to store more software than the memory area determined by the CPU within the memory area. Atsushi 2 Figure 2 Book, 7 originals of invention Jri Figure 1 Figure

Claims (1)

[Claims] A CPU (100) and a read-only memory (300_-_1 to 300) connected to the CPU and storing predetermined data.
300_-_n) and a signal for identifying the read-only memory to be accessed from the CPU;
In a circuit having an address decoder (200) that decodes and outputs the data, the address area of the read-only memory is divided into a predetermined number, the same address is given to each address area in the same read-only memory, and the CPU A second decoder (500) is provided which inputs and decodes a control signal from the read-only memory and accesses an address area specified by the CPU among the divided address areas of the read-only memory, and according to the output signal of the address decoder. Effective utilization of a memory area in CPU control, characterized in that data stored in an address area specified by the second decoder of a specified read-only memory is read out at an address specified by the CPU. Method.