JPS63257044A - Programmable memory mapping system - Google Patents

Abstract

PURPOSE:To easily change an address map at the time of executing a program, by performing memory mapping by the RAM of a program, and switching the I/O terminal of the RAM to a data bus or a peripheral device. CONSTITUTION:When the execution of the program stored in a ROM3 is started, firstly, the space of a programmable decode RAM5 is selected, and also, a bus switching device 6 becomes active. Next, chip select on a signal line 13 prepared in advance is set at a select state, and data to be mapped is written. And when programmable mapping space is selected, a chip selector 7 becomes active, and the chip select corresponding to written data is selected. Also, when the memory mapping is changed, it can be changed by a software similarly as in the above stated manner.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to hardware of a processing circuit having a microprocessor, and particularly to a memory mapping method.

(Prior Art) Conventionally, in a processing circuit having this type of microprocessor, memory mapping is performed using a small scale integrated circuit (SSI) having a decoding function or a medium scale integrated circuit (MSI) having a decoding function.
) and was fixed hardware-wise.

(Problems to be Solved by the Invention) The first drawback of the conventional memory mapping method described above is that the memory allocation of the nine peripheral elements cannot be changed by software because the memory allocation is determined by hardware. .

Furthermore, since the decoding element is used only for dividing the address space, there is a second drawback that if bank switching is required, additional hardware is required to perform bank switching.

An object of the present invention is to perform memory mapping of a processing circuit having a microprocessor using a RAM using a program, and to eliminate the above-mentioned drawbacks by switching the I10 terminal of the RAM to a data bus or a peripheral element. An object of the present invention is to provide a programmable memory mapping system configured so that memory allocation can be easily changed using hardware.

(Means for Solving the Problems) The programmable memory mapping system according to the present invention includes a programmable decoding RAM and a control means.

The programmable decode RAM is for memory mapping.

The control means is for rewriting the write data of the programmable decoding RAM as necessary and controlling memory mapping of a desired address space by software.

(Example) Next, two aspects of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the programmable memory mapping method according to the present invention. In Figure 1, 1 is a CPU, 2 is a decoder, and 3aROM
, 4 is RAM, 5 is programmable decode RAM, 6
is a bus switching element.

7 is a chip selector, 8 is a C8 inversion element, 9 is a data bus, 10 is an address bus, 11 is a read signal line, 12 is a write signal line, 13 is a chip select signal line, 14 is a decode signal line, 15 is an expansion terminal It is.

CPUIU address bus10. A ROM 3.6 stores programs via the f-tabus 9° and the decoder 2.
RAM4 used as a data buffer. and a programmable decode RAM 5. Read signal &+11. Write signal line 12. And the decode signal line 14 is connected to the ROM3. RAM4. and a programmable decode RAM 5.

The bus switching element 6 is a programmable decode RAM 5
It becomes active only when data is written to it.

Further, the chip selector 7 is enabled when the programmable mapping space is selected, and the chip select signal 11J (C8I to CSS) becomes valid. The expansion terminal 15 can be connected to a desired device.

FIG. 2 is an explanatory diagram showing an example of the memory mapping shown in FIG. 1.

Next, the operation will be explained with reference to FIGS. 1 and 2.

The memory allocation shown in FIG. 2 is performed by the decoder 2 of FIG. 1. In FIG.

When the execution of the program stored in ROM3 starts, first the C8I in the programmable mapping space is
-C88 are set in the following order.

First, space 800 of programmable decode RAM 5
0H to BFFFH are selected. In response to this, the Yoshihas switching element 6 becomes active and the chip selector 7 becomes non-active. Second.

The chip select on the signal line 13 prepared in advance becomes a selected state, and the data to be mapped is written. Third, programmable mapping space CO
If 00H-FFFFH is selected, bus switching element 6
becomes non-active, and chip selector T becomes active. In this state, the chip select (cs) corresponding to the written data is selected.

Also, when changing memory mapping.

In a similar manner to the method described above, it is possible to change memory mapping with software.

If you connect the same mechanical elements to C8I and C82,
By rewriting the data in programmable decode RAM 5 when an abnormality occurs in the C8I element, C8
1 and C82 can be relocated to the same address space.

Furthermore, when implementing bank switching in the programmable mapping area, it can be handled by software without adding hardware for puncture switching.

(Effects of the Invention) As explained above, the present invention performs memory mapping of a processing circuit having a microprocessor in a RAM using a program, and by switching the I10 terminal of the RAM to a data bus or a peripheral element. This has the advantage that the address map can be changed during program execution.

Furthermore, by connecting the same type of elements to different C8 terminals, there is an effect that if an abnormality occurs in one terminal, the data in the programmable decode RAM can be rewritten and the address space can be rearranged.

When performing bank switching in a programmable mapping area, there is an advantage that it can be handled by software without adding hardware for bank switching.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the programmable memory mapping method according to the present invention. FIG. 2 is an explanatory diagram showing an example of the memory mapping shown in FIG. 1. 1... CPU 2... Decoder 3... ROM 4... RAM 5... Programmable decode RAM 6... Pass switching element 7... Chip selector 8... C8 inversion element 9.10. ...Bus 11-14...Signal line 15...Terminal

Claims (1)

[Claims] A programmable decode RAM for memory mapping, and a control means for rewriting the write data of the programmable decode RAM as necessary and controlling memory mapping of a desired address space by software. Features a programmable memory mapping method.