JPH04217026A - Parallel processor - Google Patents

Abstract

PURPOSE:To make a whole unit smaller in size and more compacter in constitution and reduce the number of peripheral circuits by using a bus having a small bit number. CONSTITUTION:This parallel processors are provided with plural arithmetic pipelines arranged in parallel, a decoder which outputs process instructions to each arithmetic pipeline after decoding, and general register which is provided with register sections in which process instructions outputted to each decoder are written and the arithmetic pipelines are simultaneously executed by successively writing the process instructions in each register section of the general register, simultaneously designating the register sections in which process instructions are written by means of a parallel instructing means, and then, simultaneously outputting the process instructions to each decoder. Therefore, simultaneous concentration of a large amount of information to one bus can be eliminated at the parallel processing time and the need of using a bus having a large bit number is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing apparatus such as an electronic computer that processes a plurality of pieces of information in parallel in order to speed up information processing.

0002

[Background Art] Many techniques have been devised to speed up information processing devices such as electronic computers, and one instruction that used to take several clocks to execute can now be executed in almost one clock. It has become. That is, CPI
(Cycle per instruction) The value used to be 2 to 5, but now it is approaching 1.

[0003] In order to further speed up the information processing device, that is, to reduce the CPI value to 1 or less, a parallel processing device that executes a plurality of instructions simultaneously has been devised.

[0004] As this type of parallel processing device, VLIW (
Very Large Instruction Word) method (
"Parallel Computer Configuration Theory", author Shinji Tomita, Shokodo Co., Ltd.
November 1986) is known. Below, a VLIW parallel computer based on "parallel computer configuration theory" will be outlined based on FIG. 2.

[0005] The basic instruction has a fixed length of 32 bits, and has a fixed length of 4 bits.
One basic instruction is stored in one word, or 128 bits. Then, during execution, one word is read at the same time, and four words are read at the same time.
The main arithmetic pipeline executes four basic instructions in parallel and simultaneously. As a result, the above-mentioned CPI value is ideally 0.25.

[0006] 201 has four internal buses with a width of 32 bits,
A data unit 202 is connected to the internal bus 201 by four 32-bit wide buses, and this data unit 202 includes a data cache. 203 is an instruction unit that includes an instruction cache. 2
04 is a bus interface, and data unit 202
A 128-bit wide internal data bus is connected to the instruction unit 203, and a 128-bit wide instruction bus is connected to the instruction unit 203. The bus interface 204 includes an external 32-bit address bus, 1
Connected by a 28-bit data bus and control bus.

205 is an instruction decoder;
06 is an instruction register. Instruction decoder 205 receives a 128-bit wide instruction from instruction unit 203, decodes it, and stores it in instruction register 206 as a microinstruction. The instruction register 206 holds four instructions worth of microinstructions, and controls the first to fourth arithmetic pipelines 208 to 211 by outputting these microinstructions.

Reference numeral 207 denotes a multi-port register. This multi-port register 207 is connected to the internal bus 201 by four 32-bit wide buses, inputs data to be processed from the internal bus 201, and inputs data to be processed from the internal bus 201. It is output to each calculation pipeline 208 to 211 via a bus. Each arithmetic pipeline 208 to 211 performs data processing such as fixed point arithmetic, logical arithmetic, and floating point arithmetic over several clocks using the microinstructions. The four operation pipelines 208 to 211 effectively perform four operations every clock. The output side of each arithmetic pipeline 208-211 is connected to the internal bus 201 via a 32-bit wide bus.

Next, the operation of the VLIW parallel computer with the above configuration will be explained.

The instruction unit 203 has 12
An 8-bit wide instruction is read from external memory (not shown) via bus interface 204. Next, the instruction decoder 205 decodes the read instruction and writes it into the instruction register 206 as a microinstruction. The microinstruction written in the instruction register 206 is output to each operation pipeline 208 to 211 to control them. Each of the calculation pipelines 208 to 211 reads data in the multiport register 207 as necessary, and writes the data after calculation processing to the multiport register 207 via the internal bus 201. Then, each calculation pipeline 208 to 211 reads this data again and performs calculation processing multiple times. In addition, each calculation pipeline 208 to 211 once writes the data after calculation processing to the data unit 202 via the internal bus 201, and
Data unit 202 writes data to multiport register 207 via internal bus 201 and performs multiple operations.

Furthermore, the data unit 202 exchanges data with the outside via a bus interface 204. Instruction decoding, microinstruction reading from the instruction register 206, and processing in each arithmetic pipeline 208 to 211 are all pipelined, so four instructions can be executed per clock.

0012

[Problems to be Solved by the Invention] However, since the above-mentioned VLIW parallel computer processes four basic instructions as one word, the data bus width of a normal computer is 16
However, a data bus width of 128 bits is required. For this reason, when the entire unit is packaged, there are problems in that the number of pins extending to the outside increases and becomes complicated, and the amount of peripheral circuits increases.

The present invention has been made in consideration of the above points, and it is possible to simplify the peripheral circuitry by reducing the number of pins by using a normal 32-bit width bus while maintaining high-speed processing capability. The purpose is to provide a parallel processing device.

[0014]

[Means for Solving the Problems] The present invention has been made to solve such problems, and includes a plurality of arithmetic pipelines provided in parallel to perform a plurality of arithmetic operations in parallel, and each arithmetic pipeline It has a decoder that decodes and outputs a processing instruction to each arithmetic pipeline, and a plurality of register sections, and a processing instruction that is output to each decoder is written in one of the register sections. and a general register, and includes parallel instruction means for simultaneously specifying each register section of the general register into which a processing instruction is written, outputting the same to each decoder at the same time, and causing each arithmetic pipeline to execute at the same time. Features.

[0015]

[Operation] With the above configuration, processing instructions are sequentially written to each register portion of the general register. Then, the parallel instruction means simultaneously specifies each register section into which a processing instruction has been written, outputs the processing instruction to each decoder simultaneously, and executes each arithmetic pipeline at the same time. This eliminates the simultaneous concentration of a large amount of information on one bus, and reduces the need to use a bus with a large number of bits.

[0016]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 and 3.

FIG. 1 is a block diagram showing a parallel computer as a parallel processing device of this embodiment, and FIG. 3 is an explanatory diagram showing parallel execute instructions.

In FIG. 1, 101 is an internal bus, 102
1 is a data unit including a data cache; 103 is an instruction unit including an instruction cache; 104 is a bus interface; 112 to 1;
Reference numeral 15 denotes first to fourth arithmetic pipelines, which have the same configuration as the conventional parallel processing device described above.

Internal bus 101 and data unit 102 are connected by a 32-bit wide internal data bus. The data unit 102 and the bus interface 104 are connected by a 32-bit wide internal data bus. Instruction unit 103 and bus interface 104 are connected by a 32-bit instruction bus. The bus interface 104 has all 3
A 2-bit address bus, data bus, and control bus are connected. Instruction unit 1
03 is connected to the internal bus 101.

Reference numeral 105 denotes a decoder for single arithmetic processing, which receives instructions from the instruction unit 103, decodes them, and outputs them as microinstructions. A multiplexer 106 selectively outputs microinstructions from the decoder 105 for single arithmetic processing and microinstructions from a parallel first decoder 107 (to be described later) to the first arithmetic pipeline 112.

Reference numeral 107 denotes a parallel first decoder for parallel arithmetic processing, which decodes processing instructions from the general register 111, which will be described later, into microinstructions and sends them to the multiplexer 1.
06 to the first calculation pipeline 112. 108 is a parallel second decoder, and general register 1
The processing instructions from 11 are decoded into microinstructions and output to the second arithmetic pipeline 113. 109 is a parallel third decoder, 110 is a parallel fourth decoder, and like the parallel second decoder 108, these also decode processing instructions from the general register 111 into microinstructions, and send them to the third and fourth arithmetic pipes. Lines 114, 11
5, respectively.

A general register 111 includes a plurality of register sections. Specifically, the general register 111 has 64 register sections each having a width of 32 bits and into which one processing instruction can be written.
It is composed of 1. Furthermore, the general register 111 has a multi-port configuration, and the internal bus 10
It is connected by four bidirectional buses with a width of 1 and 32 bits to input and output data, and further outputs data to each calculation pipeline 112 to 115 using a bus with a width of 32 bits. Processing instructions for controlling each arithmetic pipeline 112 to 115 are sequentially written in each register section of the general register 111 using a load instruction.

The parallel execute instruction as the parallel instruction means has the configuration shown in FIG. That is, it includes an operation code meaning "parallel execute" and four fields each specifying a specific register section of the general register 111. An example of these bit widths is, for example, an operation code of 8 bits and each field of 6 bits. Then, the parallel execute instruction 121 simultaneously specifies all specific register sections of the general register 111, and sends it to each operation pipeline via each decoder 107 to 110.
12 to 115 are executed simultaneously.

Next, the processing operation of the parallel computer with the above configuration will be explained. First, normal single operation processing is as follows. Instruction unit 103 reads processing instructions from external memory via bus interface 104 . Next, the read processing instruction is written to the decoder 105, decoded into a microinstruction, and the first arithmetic pipeline 112 is controlled via the multiplexer 106. The arithmetic pipeline 112 reads data in the general register 111 and writes processed data to the general register 111 via the internal bus 101 as necessary. Furthermore, the calculation pipeline 112
writes the processed data to the data unit 102 via the internal bus 101, and the data unit 102 writes the data via the internal bus 101 to the general register 11.
Write to 1. The data unit 102 also exchanges data with the outside via the bus interface 104.

[0025] When performing parallel arithmetic processing, the process is as follows.

First, before entering a loop, a load instruction is used to sequentially store a plurality of processing instructions to be executed in parallel in a specific register section of the general register 111. This processing instruction has a fixed length of 32 bits, and is written in advance to the data section or the like at the stage of compiling the program. Note that most processing instructions are included in loops and are often repeatedly executed. Generally, 95% of the execution time is spent on 5% of the total source code, so the general register 11
The time it takes to store a processing instruction in each register section of 1 is a time that hardly poses a problem for loop processing.

When the parallel execute instruction 121 is written to the decoder 105, the general register 111 specified by each field of this instruction 121
Each processing instruction of the parallel first to fourth decoders 107 to 110
is output to. Each decoder 107-110 decodes the received processing instruction into a microinstruction, and then outputs the microinstruction to each operation pipeline 112-115, respectively. At this time, the input side of the multiplexer 106 is connected to the parallel first decoder 1.
07 side, each calculation pipeline 11
2 to 115 perform pipeline operations according to each microinstruction. Since the decoding of the parallel execute instruction 121, the reading of the processing instruction from the general register 111, and the decoding of the processing instruction in the parallel first to fourth decoders 107 to 110 are all performed by pipeline processing, the parallel execution instruction is As long as the cute instruction 121 continues, equivalently four instructions will continue to be executed per clock. As a result, from the viewpoint of execution speed, by executing one parallel execute instruction 121, four normal instructions are executed. Note that it is desirable to keep the number of normal instructions to a minimum in the loop and place as many parallel execute instructions 121 as possible.

As described above, while the conventional VLIW parallel computer requires a 128-bit wide instruction bus and data bus to execute four basic instructions as one word per clock, the parallel computer of this embodiment maintains high-speed information processing capability through parallel processing,
A 32-bit wide instruction bus and data bus can be used, and the entire unit can be made smaller and more compact, and the number of peripheral circuits can be reduced.

In this embodiment, the case where four normal instructions are executed in parallel with one parallel execute instruction 121 was explained as an example, but one parallel execute instruction executes two normal instructions, Even when three or five or more instructions are executed in parallel, the same operations and effects as described above can be achieved.

[0030] Furthermore, a separate operation code is assigned to each field of a parallel execute instruction that executes two, three, four, or five or more normal instructions in parallel, and different processing is performed on each operation pipeline. It may be possible to do so.

[0031] It goes without saying that when five or more instructions are to be executed in parallel, five or more decoders and arithmetic pipelines are provided correspondingly.

[0032]

[Effects of the Invention] As detailed above, according to the present invention,
It includes multiple arithmetic pipelines installed in parallel, a decoder that decodes and outputs processing instructions to each arithmetic pipeline, and a general register in which the processing instructions to be output to each decoder are written in one of the register sections. The processing instructions are sequentially written to each register section of the general register, each register section into which the processing instructions have been written is specified simultaneously by the parallel instruction means, and the processing instructions are simultaneously output to each decoder to execute each calculation pipeline. Since they are executed simultaneously, it is possible to prevent a large amount of information from being concentrated on one bus at the same time, and to suppress the need to use a bus with a large number of bits. This makes it possible to use a bus with a smaller number of bits than in the past, making it possible to make the entire unit smaller and more compact, and to reduce the number of peripheral circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a parallel computer as a parallel processing device of this embodiment.

FIG. 2 is a block diagram showing a conventional parallel computer.

FIG. 3 is an explanatory diagram showing parallel execute instructions.

[Explanation of symbols]

101 Internal bus 102 Data unit 103 Instruction unit 104
Bus interface 105 Decoder 106 for independent calculation processing
Multiplexer 107 Parallel first decoder 108 Parallel second decoder 109 Parallel third decoder 110 Parallel fourth decoder 111 General register

Claims (1)

[Claims] Claim 1: A plurality of arithmetic pipelines are provided in parallel to perform a plurality of arithmetic operations in parallel, and a plurality of arithmetic pipelines are provided corresponding to each arithmetic pipeline, and a processing instruction is decoded into each arithmetic pipeline. and a general register which has a plurality of register sections and into which a processing instruction to be output to each decoder is written. A parallel processing device comprising parallel instruction means that simultaneously specifies each register section and simultaneously outputs to each decoder to execute each calculation pipeline simultaneously.