JPS6136671B2 - - Google Patents

Description

[Detailed Description of the Invention] (A) Technical Field of the Invention The present invention provides a main memory key control method, in particular, a method for updating key information corresponding to the memory content in response to an access to the memory content on the main memory device. In a data processing system equipped with an entry queue section in which a key information update requesting queue entry requesting that the key information be updated and a key information updated queue entry indicating that the key information has been updated are registered, Reset reference bit (RRB) that resets reference bits in information
When the command is issued, even if the above key information update request queue entry exists, the above RRB command is immediately executed in such a way that the above request contents are processed without any processing corresponding to the request. The present invention relates to a main memory key control method that is executed.

(B) Background and problems of the technology Conventionally, key information includes the manner in which access occurs to the storage contents on the main storage device, and the reference bit section and/or change bit on the key information is set in response to the occurrence of access. The contents of the section are updated. In this case, a key information update requesting queue entry is generated and registered in the entry queue section in response to the memory content that needs to be updated as described above, and the corresponding key information is sequentially updated. . It is desirable to be able to check in a simple way whether or not the above-mentioned update is performed, and the above-mentioned key information update requesting queue entry is changed to a key information updated queue entry and is registered in the above-mentioned entry queue section. things are being done.

Conventionally, when an RRB instruction is issued that specifies the address information of the item with the key information and resets the contents of the reference bit section, the key information with the address information is updated on the entry queue section. If there is a queue entry requesting key information update, the process described above will wait until the process corresponding to the request is completed.
The RRB instruction was now being executed.

However, since the above-mentioned RRB instructions in an operating system are often executed repeatedly and continuously (instructions are used frequently), it is desirable to speed up the processing of the above-mentioned RRB instructions. The above-mentioned speed increase is desired also because there is a risk of overrun occurring.

(C) Object and Structure of the Invention The present invention aims to solve the above-mentioned problems, and the main memory key control method of the present invention is such that key information is retained corresponding to the storage contents on the main memory device. The key information storage section has a key information storage section, and the key information has at least an access key section, a reference bit section, and a change bit section, and updates the key information in accordance with the stored contents, and updates one of the key information. an entry queue section in which a key information queue entry corresponding to the accessed storage content is registered in a data processing system in which an instruction is executed to reset the contents of the reference bit section by specifying the accessed memory contents;
A key access register in which the above instruction is set, and an address comparison section that compares the address information in the key access register with the address information in each key information queue entry stored in the entry queue section. When the above-mentioned instruction is set in the above-mentioned key access register, the above-mentioned instruction is registered in the above-mentioned queue entry as the key information update requesting queue entry and the key information updated queue entry. is controlled to check whether the key information corresponds to the key information processed by The present invention is characterized in that the corresponding key information is immediately written on the key information storage unit in a form in which the contents are forcibly reset. This will be explained below with reference to the drawings.

(D) Embodiments of the Invention FIG. 1 shows an embodiment of a data processing system to which the present invention is applied, FIG. 2 shows an embodiment of the key/memory control section shown in FIG. 1, and FIGS. An explanatory diagram illustrating the manner in which key information is stored and the manner in which general memory contents are stored, FIG. 4 is an example data format of a queue entry according to the present invention, and FIG. 5 is an example of a process for updating key information. An explanatory diagram explaining the embodiment, Fig. 6 is an ISK (insert storage
7 is an explanatory diagram illustrating an example of processing corresponding to the SSK (set storage key) command, and FIG. 8 is an explanatory diagram illustrating an example of processing corresponding to the SSK (set storage key) 1 is an explanatory diagram illustrating an embodiment of processing according to the present invention corresponding to a reset reference bit (reset reference bit) command.

In FIG. 1, 1 is a main storage unit, 2 is a key information storage unit (hereinafter referred to as key memory or KSU), 3 is a storage control unit, 4 is a central processing unit, and 5 is a main storage unit.
is a channel processor, 6 is a main memory control unit, and 7 is a channel processor.
represents the key memory control section.

In response to the storage content on the main storage device 1, for example, 4 KB, one piece of information is prepared as shown in FIG. 3 and stored in the key memory 2 shown in FIG. 1. As shown in FIG. 3A, the key information 8 includes an access key part 9 for memory protection and the corresponding 4
Indicates whether the storage contents in the KB have ever been accessed. The reference bit section 10 and the 4
It also includes a change bit section 11 that indicates whether or not the stored contents in the KB have been rewritten. When the storage contents within the corresponding 4KB are accessed, the reference bit section 10 is updated, and when the content is rewritten, the change bit section 11 is updated.

The above-mentioned update of the key information is executed in sequence at any time by registering an update request in the entry queue section, as will be described later with reference to FIG. Note that the request has been registered in the entry/queue section above, but the update has not yet been actually executed.
In this specification, it is called a key information update requesting queue entry. It is also desirable to easily check which 4KB has key information that has been updated, and register it as a key information updated queue entry on the entry/queue section. It will be done like this.

FIG. 2 shows an embodiment of the key memory control section shown in FIG. In the figure, 12 is an entry/queue unit constituted by, for example, N sets of registers, 13-0, 13-1,... are queue entries, 14 to 20 are selectors, respectively.
21 is a key access register in which the central processing unit sets the above-mentioned ISK, SSK, and RRB instructions; 22 is a key storage register in which the key memory 2 shown in FIG. An instruction for processing key information is set and a notification is sent to the key memory 2. 23 is an instruction operation code generation section that generates a request in the entry queue section in response to the above-mentioned key information update. Something that generates a predetermined code when notifying you,
24-0 to 24-(N-1) each represent an address comparison circuit.

When the contents of main memory are accessed,
It is necessary to change the contents of the above-mentioned reference bit part of the key information corresponding to 4KB including the memory contents and the contents of the change bit part as necessary, and in order to update the key information, the entry queue part 12
The queue entry B-i is registered as a key information update requesting queue entry. Furthermore, when the process corresponding to the request is performed and the key information in the key memory (KSU) 2 is updated, the key information update requesting queue entry is stored in the entry queue section as the key information updated queue entry. 12 left on top.

FIG. 4 shows an example data format of the queue entry 13-i registered in the entry queue unit 12. 25 is a validity indicator bit; 26 is an indicator indicating whether the queue entry is a requesting queue entry (an entry in a request state) or an updated queue entry (an entry in a history state); 27 is a reference bit part mask bit; 28
29 represents a reference bit, 29 represents a change bit part mask bit, 30 represents a change bit, and 31 represents update target key information address information. The illustrated VAL bit 25 and REQ bit 26 are pattern “1,1”
When the pattern "1, 0" indicates that the entry is a key information update requesting queue entry according to the present invention, it indicates that the entry is a key information updated queue entry according to the present invention. It represents. Also, when the RM bit 27 and the R bit 28 indicate the pattern "1, 0",
It instructs to set the illustrated reference bit section 10 to "0", and when indicating "1, 1", it instructs to set the reference bit 10 to "1". The same applies to the CM bit and C bit. The address information 31 indicates the address information of the key information to be updated or the key information to be updated.

A queue entry 13-i as described above is registered on the entry queue unit 12, and the queue entry requesting key information update is sequentially notified to the key memory (KSU) via the register 22, and the key information is It will be updated, and when the update is finished,
The relevant queue entry is a queue whose key information has been updated.
It is considered an entry.

FIG. 5 explains the processing executed by the key memory control section 7 shown in FIG. 2 in response to access to the storage contents on the main storage device 1. The address information for the main memory device 1 is led to the address comparison circuit 24 via the selector 20, and is compared with the address information in the queue entries 13-0, 13-1, . . . registered on the entry queue section 12. be done.

(1) The matching result matches that of the requesting queue entry (request status, the same applies hereinafter) or the updated queue entry (historical status, the same applies hereinafter),
In addition, if the access to the main storage device 1 is "reading", no entry queue is registered anew. Also, VAL bits and
Leave the REA bit as is.

(2) The verification result matches the requesting queue entry or the updated queue entry, the access type is "write", and the RM, R, CM, and C bits of the matching entry are "1111". In this case, the entry queue is not registered again. Also, leave the VAL bit and REQ bit as they are.

(3) The verification result matches the requesting queue entry or updated queue entry, the access type is "write", and the RM, R, CM, and C bits of the matching entry are "1100". , then RM, R,
Register the CM and C bits as "1111" and set the VAL bit and REQ bit of the matching entry to "0,0".

(4) If the verification result does not match either the requested queue entry or the updated queue entry, take measures as shown in Figure 5.

FIG. 6 describes an example of processing when an ISK instruction is set in the key access register 21 shown in FIG. The operation in this case is also the sixth
It is clear from reading the diagram that it should be noted that the key access register 21
If the address information in the ISK command set in the requesting queue entry matches the address information of the requesting queue entry, the process waits until the request processing by the requesting queue entry is completed.

FIG. 7 describes an example of processing when the SSK instruction is set in the key access register 21 shown in FIG. The operation in this case is also clear by decoding FIG. 7, but if it matches the requested queue entry, it is put on standby.

Conventionally, the same processing as shown in FIG. 7 has been performed for the above-mentioned RRB command, and if it matches the requesting queue entry, it is put on standby.

The present invention attempts to improve this point, and when the above RRB instruction is set, the 8th
The operation shown in the figure is performed. When comparing FIG. 7 and FIG. 8, it can be seen that they are the same in the case of a match with an updated queue entry and in the case of a match with neither a requesting queue entry nor an updated queue entry.

In the control shown in FIG.
If the entry matches, queue the RRB instruction.
The request corresponding to the matched entry is held in the access register 21 and waited until the key memory (KSU) is notified via the register 22 and the corresponding key information is updated.

On the other hand, in the present invention, as shown in FIG. 8, the RRB command is immediately executed by processing the request including the request held by the currently requesting queue entry. That is, as shown in Figure 8, (i) If the RM, R, CM, C bits of the matching entry are "1111", the RM, R, CM bits are set in the instruction to be sent to the key memory (KSU). ,C
Give "1011" as the bit. Then, the VAL bit and REQ bit of the matching entry are set to "0, 0" and emptied. In order to create key information in the same form as when the RRB instruction is executed after the request held by the requesting queue entry is executed, the RM, R,
This is because it is sufficient to set the CM and C bits to "1011".

(ii) RM, R, CM, C of matching entries
If the bit is "1100", RM, R,
Give "1000" as CM and C bits. Then, the VAL bit and REQ bit of the matching entry are set to "0,0" and emptied. In order to create key information in the same form as when executing the RRB instruction after the request held by the requesting queue entry is executed, the RM , R, CM, and C bits as "1000" is sufficient.

Although the control mode has been explained with reference to FIGS. 5 to 8, the control corresponding to FIGS. 5 to 8 is executed by hardware logic on the key memory control unit 7. It is.

(E) Effects of the Invention As explained above, according to the present invention, when executing the RRB command, the key information update request
The requests that an entry has are now included and executed together, and in certain cases when an RRB command is given, what was previously controlled to be in a standby state has been improved so that it can be executed immediately. ing. Frequently used for this purpose
RRB instructions can be executed without waiting time, making it possible to improve processing speed.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of a data processing system to which the present invention is applied, FIG. 2 shows an embodiment of the key memory control section shown in FIG. 4 is an explanatory diagram illustrating the storage mode of general storage contents, FIG. 4 is an example data format of a queue entry according to the present invention, and FIG. 5 is an explanatory diagram illustrating an example of processing for updating key information. 6 is an explanatory diagram illustrating an example of a process corresponding to an ISK (insert storage key) command, and FIG. 7 is an example of a process corresponding to an SSK (set storage key) command. FIG. 8 is an explanatory diagram illustrating an embodiment of processing according to the present invention corresponding to an RRB (reset reference bit) command. In the figure, 1 is the main memory, 2 is the key information storage unit,
3 is a storage control unit, 4 is a central processing unit, 5 is a channel processor, 6 is a main memory control unit, 7 is a key memory control unit, 12 is an entry queue unit,
13 is a queue entry, 21 is a key access register, 22 is a key storage register, 23 is an instruction operation code generator,
24 represents an address comparison circuit.

Claims (1)

[Claims] 1 It has a key information storage part that holds key information corresponding to the storage content on the main storage device, and the key information has at least an access key part, a reference bit part, and a change bit part, and the key information has In a data processing system, a key corresponding to the accessed memory content is executed, in which an instruction is executed to change the key information in response to the key information and reset the contents of the reference bit section by specifying one of the key information. The entry where the information queue entry is registered.
A queue section, a key access register in which the above instruction is set, and a check between the address information in the key access register and the address information in each key information queue entry stored in the entry queue section. When the above-mentioned instruction is set in the above-mentioned key access register, the key information change request is registered on the above-mentioned queue entry as a queue entry and a key information updated queue entry. If the key information corresponding to the key information processed by the above instruction is controlled and registered as a queue entry during the above key information update request, the above in the queue entry A main memory key control method characterized in that the corresponding key information is immediately written on the key information storage section by forcibly resetting the contents of the reference bit section.