JPS6395538A - Control system for instruction processing order - Google Patents

Abstract

PURPOSE:To shorten the processing time with the titled control system by reusing an instruction sequence that is already executed as an instruction group to be applied to an arithmetic part. CONSTITUTION:A read address generating part 25 produces an address to read out successively a stored 1st executing instruction sequence and supplies this sequence to an instruction group selecting part 21. Each instruction of the 1st executing instruction sequence receives a branch information tag and is supplied to an instruction executing order deciding application part 3 to be rearranged here into a 2nd executing instruction sequence. This 2nd sequence is stored in a memory part 41 in place of the 1st sequence by the address supplied from a write address generating part 24. In such a way, the instruction executing order of a group of instruction already executed is reused to decide the instruction executing order. Thus the processing time is shortened with a control system for instruction processing order.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction processing order control method that determines the instruction execution order regardless of the order of instructions in a program.

[Conventional technology]

Conventionally, for the purpose of speeding up instruction processing, a method has been used in which the instruction processing order is dynamically determined and instructions are input to an arithmetic unit regardless of the order specified in the program. (For example, IBM 360/'91 floating point processor: The IBM System, written by D.W. Anderson, F.L. Sparacio, and F.M. Tomasulo,
/ 360 Model 91: Machine Philosophy and
Ins 1~Raction Handling°°IBM Journal on Research and Development I, pp. 8-24, No. 1, Volume 11, January 1967 (D
, W. Anderson, F. J., 5paracio.
, F., M., Tomasulo, The IBM 5ys
t, em/360 Mode January: Machine P
h1lo-sopby and In5truct
, ioo Haodling'' IBM Jour
nalof Re5earch & Develop
ent+PP, 8-24, N(L 1, Voe, 1
1, Jan 1967): ``Instruction Ish Logic'' written by F. W. and Liu E. Smith.
"Four Pie Blind Supercomputers" 11th Annual International Symposium on Computer Architecture, pp. 110-118, 1984 (S.

Weiss, J.E., Sm1th”In
5truct, ion l5sue Logicf
or Pipelined Supercompute
rs"' 11th Annual International
onal Sy+nposiun+ on Compu
ter^architecure, l'l', 110-1
18, +9114 )).

These computers that control the order of instruction processing have a means to determine the conflict between instruction input/output operands and the availability status of the arithmetic unit, and to decide whether to input instructions to the arithmetic unit regardless of the order specified in the program. Hereinafter, this means will be referred to as an execution queue.

As shown in FIG. 7, the execution waiting queue is a mechanism that confirms the arrival of operands 33 required by a group of instructions 32 to be input to the arithmetic unit, and sends the instructions to the arithmetic unit starting with the instructions that have the necessary operands. , holds a plurality of standby instructions 32 waiting for operands.

[Problems to be Solved by the Invention] How optimal is the control of the order of instruction execution by means for detecting conflicts between the input and output operands of the instructions described above and determining the possibility of inputting them to the arithmetic unit based on the usage status of the arithmetic unit? Is it possible to do this?
It depends on the number of entries in the execution waiting queue, that is, the possibility of finding an instruction to be input to the arithmetic unit at a certain time T1 is 0.The number of instructions (number of entries in the execution waiting queue) that can be judged whether it can be input at time T1 is large. The higher the price, the higher the price.

However, there are also factors that prevent the number of entries in the execution queue from being increased. In particular, when trying to determine the possibility of inputting instructions to an arithmetic unit within a set clock time and deciding which instructions to input, there is a natural limit to the number of entries in the execution queue that can be realized. It will be done. Extending the tarock cycle or increasing the number of clocks required to determine the possibility of inputting data to an arithmetic unit poses many problems from the viewpoint of throughput.

That is, in the conventional instruction processing order control method, there is a problem in that it is difficult to determine the effective order of instructions in a small-capacity execution queue.

[Means for solving problems]

The system of the present invention uses a program storage means for storing a program, and determines the collision of input/output operands of each instruction of a supplied instruction group and the availability status of the arithmetic unit, without depending on the order specified in the program. f) an instruction execution order determining supply means that determines the instruction supply order and supplies each of the instructions to the arithmetic unit, and a group of instructions supplied to the arithmetic unit and each instruction of the instruction group to the arithmetic unit; an execution instruction sequence storage means for holding a supply order of the instructions; Execution instruction group selection that generates a write address for sequentially storing the instructions supplied to the arithmetic unit in the execution instruction sequence storage means, and generates a successive address for sequentially reading out the stored instructions from the execution instruction sequence storage means. It is configured to include a writing/reading means.

[Effect]

The operation will be explained using the program example shown in FIG. In FIG. 2, C4-a+b f4-d-te indicates that there are two assignment expressions in a certain loop of the program. FIG. 3(a,) shows the expansion of these two assignment expressions into an object program. This instruction sequence is hereinafter referred to as the original instruction sequence. Here M
(a) represents the value stored at address a in memory, A, B, C.

D, E, and F each refer to a value stored in a corresponding specific register.

When this program is processed by the instruction processing order control method according to the present invention, the first and second loop operations use the given program instruction sequence shown in FIG. 3 <a>, that is, the original instruction sequence, and the third loop operation is the order of instructions input to the arithmetic unit for the second time, the first execution command sequence (described later) shown in Figure 4 (a) is performed manually, and the Nth (N22) is calculated at the N-1st time by repeating the loop. Processing proceeds using the order of instructions input into the device as input.

Figures 4(a) and 5(a) show the execution standby queue.
・The processing order when the number is 2 is shown.

Figure 4(a) shows the order of instructions input to the arithmetic unit for the first and second time (hereinafter referred to as the first execution instruction sequence).
, FIG. 5 (a> is the order of instructions input to the arithmetic unit for the third time (
This is hereinafter referred to as the second execution command sequence),
The execution instruction sequence is more effective during the third execution than during the first and second executions.

FIG. 3(b), FIG. 4(b), and FIG. 5(b) show examples of execution timing when such sorting is performed. FIG. 3(b) shows the case when execution is attempted without instruction processing order control, FIG. 4(b) shows the case when conventional instruction processing order control is executed, and FIG. This is the case when instruction processing order control is executed. As is clear from FIG. 5(b), in the instruction processing order control method according to the present invention, by increasing the number of executions, instructions are executed in the optimum order so that the processing time is shortened. Therefore, it is possible to obtain the optimum processing order even if the number of entries in the instruction waiting queue is small.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The instruction processing order control system shown in FIG. 1 includes a program storage unit 1 that holds programs, an execution instruction group selection/writing/reading unit 2 that obtains a group of instructions to be input to an arithmetic unit, and conflict and calculation of input/output operands of instructions. an instruction execution order determining input unit 3 that determines the usage status of the device and determines input of instructions to the arithmetic unit regardless of the order specified in the program; and an execution instruction sequence storage unit that holds a group of instructions that have already been input and their order. It consists of 4.

The execution instruction group selection writing/reading unit 2 includes an instruction group selection unit 21;
Branch address table 22 and branch address management section 2
3, a write address generation unit 24 that generates an address to hold an instruction input to the arithmetic unit, and a read address generation unit 24 that generates an address for selectively reading out an instruction to be executed from the instruction group input to the arithmetic unit. It consists of 25.

Further, the execution instruction sequence storage unit 4 includes a storage unit 41,
The operation of this embodiment is as follows: a register 42 for storing read addresses, a register 43 for storing read instructions, a register 44 for storing write addresses, and a register 45 for storing write instructions. The following describes a case where the program shown in FIG. 2 is taken as an example and the number of entries in the execution queue in the instruction execution order determining/inputting section 3 is two.

The program storage unit 1 stores the program shown in FIG. 2 with the original instruction sequence shown in FIG. 3(a).

Instructions in the original instruction sequence are supplied from the program storage section 1 to the instruction group selection section 21 of the execution instruction group selection writing/reading section 2. The main operation of the execution instruction group selection write/read unit 2 is started with the execution of a branch instruction. Until then, the instruction group selection unit 21 selects the instruction group supplied from the program storage unit 1, determines whether each instruction is a branch instruction, and supplies the instruction execution order determination input unit 3.

When the instruction supplied by the instruction group selection unit 21 is found to be a branch instruction, a branch information tag is attached to the next supplied instruction and the instruction is supplied to the instruction execution order determination input unit 3. This branch information tag is used to distinguish between instructions supplied to the instruction execution order determination input unit 3 before the branch instruction and instructions supplied after the branch instruction, and in principle, different branch information is provided for each branch instruction. tags are used.

Thus, for the first time, instructions are supplied to the instruction execution order determining input section 3 in the original instruction sequence.

An execution standby queue 61 as shown in FIG. 6 is provided in the instruction execution order determining input section 3. Although the number of entries is n in FIG. 6, the case where n=2 will be described here as described above.

The execution standby queue 61 includes a branch information tag field 64;
There is a standby instruction field 62 and a necessary operand field 63, which store corresponding information, and are output in order from the instruction with the necessary operands. Further, when the execution standby queue 61 is full, the instructions supplied to the instruction execution order determining input unit 3 after the stored instruction are not output to the arithmetic unit even if the necessary operands are in place.

How is the execution order of the instruction group supplied in the original instruction sequence shown in FIG. Explain how it will be done.

In the original instruction sequence, the wait instruction that must wait until the necessary operands are ready is instruction 103.
, 104, 107 and 108. Instructions 101 and 1
Since the necessary operands are ready, instructions 02 are sequentially input to the arithmetic units, and the two instructions 103 and 104 are first stored and held in the execution waiting queue 61. In addition, instructions after instruction 105 are not input to the arithmetic unit because the execution waiting queue 61 is full. As a result of the execution of instructions 101 and 102 in the arithmetic unit, instruction 103 is input to the arithmetic unit because the operands are ready. As a result, the execution waiting queue 61 becomes empty, so instructions 105 and 106 are input to the arithmetic unit through the execution waiting queue 61, and instruction 107 is stored in the execution waiting queue 61. and instructions 104, 107, 108 in the order of operands
is output to the arithmetic unit. Thus, the first execution command sequence shown in FIG. 4(a) is obtained.

In this way, the first instruction input to the arithmetic unit is performed for the program shown in FIG. 2, and the branch instruction at the end of the loop is supplied from the program storage section 1 to the instruction group selection section 21.

When the supplied instruction is a branch instruction, the instruction group selection section 21 attaches a branch information tag to the next supplied instruction and prepares to supply it to the instruction execution order determining input section 3, as described above.

When a branch instruction is supplied to the arithmetic unit via the instruction execution order determination input unit 3 and executed, the branch destination address information (address information in the program storage unit 1) is transferred from the arithmetic unit to the execution instruction group selection write/read unit 2. It is supplied to the branch address management section 23.

The branch address management unit 23 checks whether the supplied branch destination address is registered in the branch address table 22, and if it is not registered, registers this branch destination address in the branch address table 22. In FIG.
1 (represented as i=1 to n)), and further determines the start address of the storage area in which the execution instruction sequence following this branch instruction is stored in the storage section 41 of the execution instruction sequence storage section 4, and stores the execution instruction sequence in the branch address table 22. In FIG. 1, the first address of this node, which is registered as a pair with the branch destination address, is expressed as Lo+-1 (i=1 to n)).

The g-address generation section 24 receives the start address determined as described above from the branch address table 22 (11), and receives the branch information tag from the instruction group selection section 21, and then sends the start address determined as described above to the instruction execution order determination input section. The write address of the storage unit 41/\ stores in order the instructions 1t executed in the arithmetic unit following the branch instruction by referring to the 5-te branch' information tag of the instruction input to the arithmetic unit supplied from 3. and register 44
supply to.

The instruction group selection unit 21 is sequentially supplied with instructions starting from the branch destination address of the program storage unit 1 determined by the execution of the branch instruction, and the program moves to the second loop operation.

The instruction sequence supplied from the instruction execution order determination input unit 3 to the calculation unit in the second loop operation is the same as described above.
This is the execution instruction sequence. Therefore, this first execution instruction sequence is supplied to the arithmetic unit by the instruction execution order determination input unit 3, and is also supplied to the register 45 of the execution instruction sequence storage unit 4, and the branch information tag of the supplied instruction is written. Since the first execution instruction sequence is supplied to the address generation section 24, the first execution instruction sequence is stored in the address of the storage section 41 supplied from the write address generation section 24.

At the end of the second loop operation, another branch instruction is executed, and the branch address management unit 23 checks whether the branch destination address is registered in the branch address table 22.

This time, since the branch destination address has been registered, the branch address management section 23 switches the instruction group selected by the instruction group selection section 21 to the one supplied from the execution instruction sequence storage section 4. branch address table 2.
The start address of the first execution instruction sequence stored from 2 onwards is supplied to the write address generation section 24 and the read address generation section 25. The read address generation unit 25 generates addresses for sequentially reading out the stored first execution instruction sequences, and outputs the first execution instruction sequences to the instruction group selection unit 2.
The operation of the 3-write address generating section 24 that supplies the 3rd address to the 1st bit is performed in the same manner as described above. Each instruction of this first execution instruction sequence is attached with a branch information tag and supplied to the instruction execution order determining input unit 3.

The first execution instruction sequence is executed by the instruction execution order determining input unit 3.
The fifth execution instruction sequence is rearranged from the original instruction sequence to the first execution instruction sequence in the same manner.
The second execution instruction sequence is rearranged into the second execution instruction sequence shown in FIG. This is repeated. In this way, in this embodiment, when determining the instruction execution order, the instruction execution order of a group of instructions that have already been executed is reused.

FIG. 3(b) 7 As shown in FIG. 4(b) and FIG. 5(b), for example, the LOAD instruction and 5TORE instruction are 3'L
n (tn is one clock cycle time), ADD instruction is 4
If the processing time of to is required, the total processing time is improved to 20 to for the original instruction sequence, 16 to for the first execution instruction sequence, and 13 to for the second execution instruction sequence. ing.

In the description of this embodiment, only the improvement of a part of the program of the loop has been shown, but the improvement will be even greater for the entire loop.

Furthermore, although a single loose loop has been described in this embodiment, the present invention can also be applied to a case where there are a plurality of single loops or a case where there are multiple loops. In this case, the branch information tag is effective and execution instruction sequences can be kept distinct in different loops. Furthermore, the present invention can be applied to cases where one instruction group is used repeatedly by using branch instructions, even if it is not a loop.

In this embodiment, the explanation has been made for the case where the instruction execution order determination and input section 3 has only one execution waiting queue, but it can also be applied to the case where the instruction execution order deciding input section 3 has a plurality of execution waiting queues.

〔Effect of the invention〕

In the present invention, by reusing an already executed instruction sequence as a group of instructions to be input to the arithmetic unit, the instruction sequence of the instruction group can be rearranged to shorten the processing time when the arithmetic unit is input. This has the effect that it is possible to obtain an instruction order that can at least reduce the processing time by reducing the number of entries in the execution waiting queue.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a source program diagram for explaining the present invention in detail, and FIG. 3 is a block diagram showing an embodiment of the present invention.
The figure shows an original instruction sequence diagram showing the target program of FIG. 2 and its processing time chart, and FIG. 4 shows a first execution instruction sequence diagram and its processing time chart.
FIG. 5 is a second execution instruction sequence diagram and its processing time chart, FIG. 6 is a layout diagram showing an execution waiting queue of the instruction execution order determining input unit 3, and FIG. 7 is an explanation of the execution waiting queue. FIG. DESCRIPTION OF SYMBOLS 1...Program storage unit, 2...Execution instruction group selection writing successive unit, 3...Instruction execution order determination input unit, 4...
Execution instruction sequence storage unit, 21...instruction group selection unit,
22... Branch address table, 23... Branch address management section, 24... Write address generation section, 25.
... Read address generation section, 31.61 ... Execution standby queue, 32.62 ... Standby instruction field, 33゜6
3... Necessary operand field, 41... Storage section, 42-45... Register, 64... Branch information tag field, 101-108... Instruction. , 74-1 Agent Patent Attorney Uchihara Dai, Pa. -ζ 4th bacterium 1+1-+, lku(/1-J-, I"(ri-~勺size-
111-de:)

Claims (2)

[Claims] (1) A program storage means for storing a program, and a program storage unit that determines the collision of input/output operands of each instruction of a supplied instruction group and the usability status of the arithmetic unit, and determines the usability status of the arithmetic unit and the arithmetic unit in accordance with the order specified in the program. an instruction execution order determining supply means for determining the order in which instructions are supplied to the operating section and supplying each of the instructions to the operating section; a group of instructions supplied to the operating section; and an order in which each instruction of the instruction group is supplied to the operating section; Execution instruction sequence storage means for storing a set of instructions; and receiving a group of instructions from the program storage means and the execution instruction sequence storage means, selects a group of instructions to be supplied to the instruction execution order determination supply means, and selects a group of instructions to be supplied to the instruction execution order determination supply means; execution instruction group selection writing/reading means for generating write addresses for sequentially storing instructions supplied to the arithmetic unit in the means; and generating read addresses for sequentially reading stored instructions from the execution instruction sequence storage means; An instruction processing order control method comprising: (2) The execution instruction group selection writing/reading means is provided with a branch address table that holds the branch destination address of the branch instruction and the start address of the storage area in the execution instruction sequence storage means of the instruction group following the branch instruction, In the first case where the instruction supplied from the program storage means is a branch instruction and the branch destination address of the branch instruction is not registered in the branch address table, the corresponding start address is determined and the branch destination address is A start address is registered in the branch address table, a write address is generated by referring to the start address, a group of instructions supplied from the program storage means is selected, and the instructions supplied from the program storage means are In the second case where the branch instruction is a branch instruction and the branch destination address of the branch instruction is registered in the branch address table, a write address and a read address are generated by referring to the corresponding registered start address. Selecting a group of instructions supplied from an execution instruction sequence storage means, and selecting a group of instructions supplied from the program storage means in a third case where the instruction supplied from the program storage means is not a branch instruction. The instruction processing order control method described in scope item (1).