JP2001350627A - Digital signal processor, parallel processing method and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To schedule a command to make a parallel processing executable without increasing the memory capacity. SOLUTION: This processor is provided with a processing content memory 6 for storing the command and a processing procedure control part 1 for controlling the processing procedure of the command, and scheduling information is stored in a processing procedure map memory 2 within the processing procedure control part 1 to store only the effective command of the processing content to be executed in the processing content memory 6. In the execution of the command, the command is read from the processing content memory 6 according to the scheduling information, and a scheduling is performed to execute the command, whereby the command stored in the processing content memory 6 is minimized, so that the command can be scheduled to perform a parallel processing without increasing the memory capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal processor, a parallel processing method, and a recording medium.
It is suitable for use in a digital signal processor that schedules and processes instructions in parallel.

[0002]

2. Description of the Related Art Recently, with the development of LSI process technology and the increase in complexity of signal processing algorithms, a technology for processing digital video / audio signals by a processor architecture has become active. Further, digital signal processing of a video signal and an audio signal requires a large amount of computation within a predetermined time, and various techniques have been used to improve the processing speed. One technique for improving the processing speed is parallel processing in a processor.

[0003] In parallel processing in a processor, it is necessary to evaluate data dependence of instructions, processing resources, and the like, and perform scheduling so that data hazards and resource contention do not occur. For parallel processing in a processor, a super scalar method in which the above scheduling is performed by hardware or a VLI performed by a program compiler
There is a W (Very Long Instruction Word) architecture and the like.

The super scalar method is a method of guaranteeing the logical execution order of instructions by checking whether or not continuous instructions can be processed in parallel by hardware, and executing instructions simultaneously. However, as described above, since hardware checks whether or not continuous instructions can be processed in parallel, the hardware scale becomes large. Further, in order to increase the average value of the number of executed instructions per cycle, it is necessary to perform advanced branch prediction or execute instructions in a different order, which also increases the hardware scale.

[0005] For this reason, the VLIW architecture uses a program compiler instead of checking whether continuous instructions can be processed in parallel by hardware or not. V
In the LIW architecture, when compiling a program, a plurality of instructions that can be processed in parallel by the compiler are extracted, and an instruction having a long word length is created by combining them. Then, by executing the created instruction having a long word length, simultaneous processing of a plurality of instructions is realized.

In a processor using the VLIW architecture, an already-scheduled instruction sequence is supplied, so that it is not necessary to provide hardware for checking whether or not continuous instructions can be processed in parallel. Therefore, it is possible to speed up the execution of processing by the processor while reducing the hardware scale of the processor.

[0007]

However, in a processor using the above-described VLIW architecture, the number of instructions that can be issued simultaneously is fixed. for that reason,
In order to avoid data hazards and resource conflicts due to data dependencies, the instruction sequence that has been subjected to scheduling has to wait for subsequent processing or machine state such as registers and memory so that sequential processing is performed Is inserted without updating (np). Therefore, there is a problem that the program size becomes large and the required memory capacity increases.

The present invention has been made to solve such a problem, and provides a digital signal processor capable of scheduling instructions and executing parallel processing without increasing the memory capacity. The purpose is to:

[0009]

A digital signal processor according to the present invention comprises a processing content storage means for storing an instruction, and a processing procedure control means for controlling a processing procedure of the instruction stored in the processing content storage means. An instruction execution means for executing an instruction supplied from the processing content storage means under the control of the processing procedure control means; supplying data to the instruction execution means; and storing data processed by the instruction execution means. And a first data storage means.

Another feature of the present invention is that, under the control of the processing procedure control means, any one of a plurality of instructions supplied from the processing content storage means is selected and output to the instruction execution means. It is characterized by further comprising an instruction output means for performing the operation.

According to another feature of the present invention, the command output means includes: a command holding means for holding a command supplied from the processing content storage means; An instruction selecting means for selecting any one of a plurality of instructions supplied from the storage means or the instruction holding means and outputting the selected instruction to the instruction executing means.

Another feature of the present invention is that the processing procedure control means includes processing procedure storage means for storing scheduling information including instruction issue destination information and an integrated value of the number of valid instructions. Features.

Further, in the parallel processing method according to the present invention, the scheduling information and the instruction are separately stored, the instruction is scheduled based on the scheduling information, and the data stored in the storage medium is stored in accordance with the scheduled instruction. The communication is performed, and the instruction is executed.

According to another feature of the parallel processing method of the present invention, the scheduling information includes instruction issue destination information and integrated value information of the number of valid instructions. The generated instruction is generated.

A computer-readable recording medium according to the present invention is characterized in that a program for causing a computer to function as each of the above means is recorded. Another feature of the computer-readable recording medium of the present invention is that a program for causing a computer to execute the procedure of the parallel processing method is recorded.

According to the present invention configured as described above, the instruction is stored in the processing content storage means, and the instruction stored in the processing content storage means is read and scheduled in accordance with the instruction of the processing procedure control means. The scheduled instruction is supplied to the instruction execution means. The instruction execution means exchanges data stored in the first storage means according to the supplied instruction, and executes the instruction. As a result, to avoid data hazards and resource contention,
Without storing non-operational instructions such as registers and memories that do not update the machine state in the processing content storage means, only valid instructions can be stored in the processing content storage means and parallel processing of instructions can be executed. Further, by providing the first storage means for exchanging data with the instruction execution means, the input / output of data when executing the instruction can be easily controlled.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of the digital signal processor according to the present embodiment. Reference numeral 1 denotes a processing procedure control unit that controls an instruction issuing procedure in the digital signal processor according to the present embodiment. The processing procedure control unit 1 includes a processing procedure map memory 2, a division unit 3, and a quotient change detection unit 4, and constitutes a processing procedure control unit of the present invention.

The processing procedure map memory 2 stores scheduling information instructing an instruction issuing procedure, and constitutes a processing procedure storage means of the present invention. The processing procedure map memory 2 stores an instruction issue pattern IPN and an effective instruction count integrated value IAC for each program address PAD, and stores the instruction issue pattern according to a program address PAD supplied from a program counter 10 described later. It outputs the IPN and the effective instruction number integrated value IAC.

The instruction issuance pattern IPN is calculated by an arithmetic processing unit (program counter 10 and first to third arithmetic units 1) provided in the digital signal processor according to the present embodiment.
1, 12, 13) is information indicating whether to supply a valid instruction. The effective instruction number integrated value IAC is an integrated value of the number of valid instructions issued or to be issued from the program start address to the current program address.

The division unit 3 divides the effective instruction number integrated value IAC supplied from the processing procedure map memory 2 by the maximum parallel processing number of the digital signal processor, and outputs a quotient QAD and a remainder MOD, respectively, as the operation result. I do. The quotient change detector 4 monitors the value of the quotient QAD supplied from the divider 3, and outputs a quotient change detection signal RIV when detecting a change in the value of the quotient QAD. The division unit 3 constitutes division means of the present invention, and the quotient change detection unit 4 constitutes detection means of the present invention.

Reference numeral 5 denotes an instruction pointer counter, which is supplied from the quotient change detection signal RIV supplied from the quotient change detection unit 4 or the integrated number of valid instructions IAC supplied from the processing procedure map memory 2 and the program counter 10. An instruction pointer address IAP for reading an instruction from the processing content memory 6 is generated and output based on the control signal CNT. This instruction pointer counter 5 constitutes the address generation means of the present invention.

The instruction pointer counter 5 increments the value of the instruction pointer counter 5 when the quotient change detection unit 4 supplies the quotient change detection signal RIV when a normally continuous instruction is executed. When the quotient change detection signal RIV is not supplied, the value of the instruction pointer counter 5 is held. Then, the instruction pointer counter 5 outputs the value to the processing content memory 6 as the instruction pointer address IAP.

The program counter 10 executes a control instruction for jumping a program address such as an unconditional branch instruction, a conditional branch instruction, and a procedure call instruction, that is, a control instruction for discontinuously updating a program address. Control signal CNT
Is supplied, the instruction pointer 5 holds a value calculated by (effective instruction number integrated value IAC-1) / 4 based on the effective instruction number integrated value IAC supplied from the processing procedure map memory 2. The instruction pointer counter 5
The calculated value is output to the processing content memory 6 as the instruction pointer address IAP.

The processing content memory 6 stores instructions of the processing content to be executed by the digital signal processor according to the present embodiment, and the instructions are sequentially stored. The processing content memory 6 supplies the stored instruction to the instruction output unit 7 based on the instruction pointer address IAP supplied from the instruction pointer counter 5. This processing content memory 6
Constitutes the processing content storage means of the present invention.

The instruction output section 7 comprises a buffer section 8 and an instruction selection section 9 and constitutes an instruction output means of the present invention. The buffer unit 8 is a buffer that temporarily holds the instructions 0t, 1t, 2t, and 3t output from the processing content memory 6, and constitutes an instruction holding unit of the present invention. Buffer section 8
Updates the temporarily held instruction to the instruction 0t, 1t, 2t, 3t output from the processing content memory 6 when the quotient change detection signal RIV is supplied from the quotient change detection unit 4, and holds the instruction otherwise. Keep holding the instruction you are doing. The buffer unit 8 stores the stored instructions 0b, 1b, 2b, 3
b is output to the instruction selector 9.

The instruction selecting section 9 stores the processing procedure map memory 2
, 1t, 2t, 3t supplied from the processing content memory 6 and the instruction supplied from the buffer unit 8 in accordance with the instruction issue pattern IPN supplied from the CPU 3 and the value of the remainder MOD supplied from the division unit 3. 0b, 1b, 2b, 3b
Is selected, and the selected instruction IS
0 to IS3 at the subsequent stage
And to the first to third arithmetic units 11, 12, and 13. This instruction selecting section 9 constitutes an instruction selecting means of the present invention.

The program counter 10 is a counter for outputting the program address PAD. Normally, the value of the program counter 10 is sequentially incremented, and the value is output to the processing procedure map memory 2 as the program address PAD. Also, the instruction IS0 supplied from the instruction selection unit 9 causes the value of the program counter 10 such as a conditional branch instruction, an unconditional branch instruction, or a procedure call instruction to jump, that is, a control for discontinuously updating the value of the program counter 10. If the instruction is an instruction, processing is performed in accordance with the contents of the supplied instruction IS0 to update the value of the program counter 10 and the instruction pointer counter 5
To output the control signal CNT.

The first to third arithmetic units 11, 12, 13 are:
According to the instructions IS1 to IS3 supplied from the instruction selecting unit 9, various arithmetic processes are performed. First to third arithmetic units 11, 1
Normal instructions other than control instructions such as a conditional branch instruction, an unconditional branch instruction, and a procedure call instruction supplied to the program counter 10 are supplied to 2 and 13.

The first to third arithmetic processing units 11, 12,
The computing unit 13 may be provided with many computing units for performing computations that are desired to be processed at high speed, or a computing unit for performing only a specific computation, and may be provided with computing units in consideration of the intended use.
For example, an arithmetic logic unit (ALU: Arithmetic and Log
ical unit), a barrel shifter, a multiplier, a floating point arithmetic unit, a load store unit, and the like. The program counter 10 and the first to third programs
Computing units 11, 12, and 13 constitute a plurality of processing means of the present invention.

Numeral 14 denotes a register unit, which is an arithmetic processing unit (program counter 10 and first to third arithmetic units 1).
1, 12 and 13) store calculation data used when performing calculation processing, and store data output as a result of calculation processing. This register section 14 constitutes the second data storage means of the present invention. That is, when supplying the operation data to each operation processing unit, the register unit 14
In accordance with the register control signal RFC supplied from the instruction selection unit 9, operation data R0 to R3 are supplied to each operation processing unit. In addition, when storing the operation result and the output data of each operation processing unit, the data W0 to W3 supplied from each operation processing unit are stored in accordance with the register control signal RFC supplied from the instruction selection unit 9. . The program counter 10, the first to third arithmetic units 11, 1
The registers 2 and 13 and the register unit 14 constitute an instruction execution unit of the present invention.

Reference numeral 15 denotes a data memory for transmitting and receiving data to and from the register unit 14 via a load store unit or the like (not shown) provided in the first or second operation unit 11, 12, or the like. Yes, and constitutes the first data storage means of the present invention. The data memory 15 can read and write data from and to a specified address by directly specifying and accessing the address.

Further, the data memory 15 has an input / output interface with the outside of the processor, receives digital signal data DTI from outside the processor, and outputs digital signal data DTO outside the processor. Therefore, some addresses of the data memory 15 are
It is allocated in advance for data exchange with a data input / output unit outside the processor (not shown).

For example, when data is input from outside the processor, the digital signal data DTI is written to a predetermined address in the data memory 15. When the digital signal processor issues a load instruction, which is a memory read instruction for the address, to the first or second operation unit 11, 12, the first or second operation unit 11, 12 is issued. Control signal MAC for controlling memory access according to a loaded instruction
1. The MAC 2 is supplied to the data memory 15.

According to the supplied memory control signals MAC1 and MAC2, the data memory 15 stores the first or second data.
Of the addresses MO1 and M2
Supply O2. Further, the first or second operation unit 1
The data MO1 and MO2 supplied to the registers 1 and 12 are stored in the register section 14 as register data W1 and W2.

When data stored in the register section 14 is output to the outside of the processor, an address to which data to be output to the outside of the processor is to be written in the data memory 15 in advance. A store instruction, which is an instruction, is issued to the first or second operation unit 11 or 12.

The first or second operation unit 11 or 12 supplies memory control signals MAC1 and MAC2 for controlling memory access to the data memory 15 in response to the store instruction. In addition, the first or second operation units 11 and 12 read out the data R1 and R2 to be written to the data memory 15 from the register unit 14 and read out the read data R
1 and R2 are supplied to the data memory 15 as memory data MI1 and MI2 to output data to the outside of the processor.

FIG. 2 is a diagram showing an example of the contents of the processing procedure map memory 2 shown in FIG. Processing procedure map memory 2
Is composed of two words, an instruction issue pattern IPN and an effective instruction count integrated value IAC, for each program address PAD. In FIG. 2, the instruction issue pattern IPN is represented by a binary number, and the program address PAD and the effective instruction integrated value IAC are represented by a decimal number.

The instruction issuance pattern IPN is stored in each of the arithmetic processing units (program counter 10 and first to third arithmetic units 11, 12, 1, 1) of the digital signal processor shown in FIG.
3) shows information on whether or not to issue a valid instruction, and "1" indicates that a valid instruction is to be issued, and "0" indicates
Indicates that there is no valid instruction that can be issued due to data dependency or resource contention, etc., and the instruction selector 9 shown in FIG. 1 generates and issues a no-operation instruction (np).

The instruction issue pattern IPN is composed of 4 bits, and each bit corresponds to each of the arithmetic processing units. In FIG. 2, the instruction issue pattern IPN
Correspond to the program counter 10, and the other bits correspond to the first arithmetic unit 11, the second arithmetic unit 12, and the third arithmetic unit 13, respectively, from the most significant side.

The effective instruction integrated value IAC is obtained by integrating the number of effective instructions issued from the program start address (PAD = 0) to each program address.

FIG. 3 is a diagram showing an example of the contents of the processing contents memory 6 shown in FIG. The processing content memory 6 stores instructions 0t, 1t, 2t, and 3t to be supplied to each processing unit of the digital signal processor shown in FIG.
The instructions 0t, 1t, 2t, and 3t to be stored include only valid instructions without including no-operation instructions. For one instruction pointer address IAP, four instructions 0t, 1t, 2
t, 3t are stored, and the four instructions are processed according to the time processed by each of the arithmetic processing units and the order of the arithmetic processing units.
Stored sequentially.

FIG. 4 is a diagram showing an operation example of the instruction selecting section 9 shown in FIG. 4, IPN is an instruction issue pattern supplied from the processing procedure map memory 2 shown in FIG. 1, and MOD is a remainder supplied as a result of the operation by the division unit 3 shown in FIG. IS0 to IS3 are instructions supplied to the program counter 10 and the first to third arithmetic units 11, 12, and 13, respectively, as a result of selection by the instruction selection unit 9. Note that 0t to 3t are instructions output from the processing content memory 6, and 0b to 3b are instructions output from the processing content memory 6 and temporarily stored in the buffer unit 8, and then output. Np is a no-operation instruction.

The instruction selector 9 stores the processing content memory 6 in accordance with the supplied instruction issue pattern IPN and the remainder MOD.
And the instruction supplied from the buffer unit 8 is selected and output according to FIG. For example, when the supplied instruction issuing pattern IPN is “1011” and the supplied remainder MOD is “2”, the instruction selecting unit 9 compares the instruction 2b supplied from the buffer unit 8 with the program counter 10. And supplies the first operation unit 10 with the non-operation instruction np. The instruction 3b output from the buffer unit 8 is supplied to the second operation unit 12, and the instruction 0t supplied from the processing content memory 6 is supplied to the third operation unit 13.

Next, the operation will be described with reference to FIG. FIG. 5 is a timing chart showing the operation of the digital signal processor according to the present embodiment. FIG.
2 stores the information shown in FIG. 2 and the processing content memory 6 stores the instructions shown in FIG.

In FIG. 5, the program counter 10 does not execute instructions for discontinuously updating the value of the program counter 10 such as a conditional branch instruction, an unconditional branch instruction, and a procedure call instruction. The value is sequentially incremented for each cycle time. The instruction issue pattern IPN output from the processing procedure memory map 2 is supplied to the instruction selection unit 9 after being delayed by one cycle time, and the remainder MOD output from the division unit 3 is subjected to instruction selection after being delayed for two cycle times. It is supplied to the unit 9.

In FIG. 5, after the reset operation, the digital signal processor, based on the instruction issue pattern IPN of the processing procedure map memory 2 read in accordance with the program address PAD supplied from the program counter 10 and the effective instruction number integrated value IAC, The instruction pointer address IAP to the processing content memory 6 is controlled. As a result, the instruction sequence is read out from the processing content memory 6 and supplied as a scheduled instruction sequence to each of the arithmetic processing units connected to the subsequent stage to perform parallel processing.

First, the program address PAD supplied from the program counter 10 is sequentially incremented for each cycle time and supplied to the processing procedure map memory 2.

The instruction issuance pattern IPN and the integrated number of valid instructions IAC are based on the supplied program address PAD.
Is output from the processing procedure map memory 2. For example, at time t ₀ , the instruction issue pattern I is set in accordance with the supplied program address PAD “0”.
'1010' is output from the processing procedure map memory to PN, and '2' is output from the processing procedure map memory to the effective instruction count integrated value IAC. When the supplied program address PAD is “1” (time t ₁ ), “0001” is output as the instruction issue pattern IPN, and “3” is output as the effective instruction number integrated value IAC. Similarly, at time t ₂
Thereafter, the instruction issue pattern IPN and the effective instruction count integrated value IAC are output from the processing procedure map memory 2 in accordance with the supplied program address PAD.

The quotient QAD and the remainder MOD output the result of arithmetic processing of the output effective instruction count integrated value IAC by the division unit 3. For example, when the effective instruction count integrated value IAC is "2" (time t _{In (0} ), '0' is output to the quotient QAD and '2' is output to the remainder MOD. When the integrated number of valid instructions IAC is “4” (time t ₂ ), the quotient Q
'1' is output to AD and '0' is output to remainder MOD.

The instruction pointer address IAP is "0" after the reset operation, and thereafter is sequentially incremented with a change in the value of the quotient QAD. That is, in FIG. 5, the value of the quotient QAD changes from “0” to “1” at time t _2.
No and to changes in, the instruction pointer address IAP to time t ₃ is made to '1'. Similarly, times t ₄ , t ₅ , t
With the change in the value of the quotient QAD in _6, the instruction pointer address IAP is sequentially incremented at time t _5, t _6, t ₇ the value is changed after one cycle time quotient QAD.

The instructions 0t, 1t, 2t, 3t are output from the processing content memory 6 according to the instruction pointer address IAP supplied at each time. For example, when the instruction pointer address IAP is “0” (at times t ₀ , t ₁ ,
At t ₂ ), instructions 0t, 1t, 2t, 3t have A0, C
0, D1, and A2 are output. Also, instructions 0b, 1b,
2b and 3b temporarily store the instructions 0t, 1t, 2t and 3t, and outputs the output at one cycle time after the time when the instructions 0t, 1t, 2t and 3t change, ie, when the instruction pointer address IAP changes. Change.

The (delayed) IPN is obtained by delaying the instruction issue pattern IPN by one cycle time as described above. Also, (delayed) MOD
Is the remainder MOD delayed by two cycle times. For example, (delayed) IP at time t ₂
N and (delayed) MOD is a command issued pattern IPN at time t ₁ ( '0001'), is the remainder MOD at time t ₀ ( '2').

The instructions IS0 to IS3 are (delay
d) An instruction selected and output by the instruction selecting unit 9 based on the IPN and the (delayed) MOD. For example, at time t ₀ , (delayed) IPN
Is “1010” and the (delayed) MOD is “0”, so that the instructions IS0 to IS3 include the instructions 0b, np, 1b, np, ie, A, respectively, according to FIG.
0, np, C0, and np are output. Also, at time t ₃ , the (delayed) IPN is “1000” and the (delayed) MOD is “3”,
Instructions IS0 to IS3 include instructions 3b, np, and n, respectively.
p, np, that is, A2, np, np, np are output. Thus, the digital signal processor performs parallel processing.

FIG. 6 is a diagram showing an example of an instruction sequence scheduled by the operation shown in FIG. Despite the fact that the processing content memory 6 includes only valid instructions, in order to avoid data hazards and resource conflicts due to data dependencies, no-operation instructions (such as np ) Is inserted properly.

As described above in detail, according to the present embodiment, the instruction issue pattern I is stored in the processing procedure map memory 2.
The PN and the integrated number of valid instructions IAC are stored, and only the valid instructions of the processing contents performed by the digital signal processor are stored in the processing contents memory 6. Then, the processing content memory 6
When executing the instruction stored in the memory, the instruction is read out from the processing content memory 6 based on the effective instruction number integrated value IAC, and the read instruction is read based on the instruction issue pattern IPN and the effective instruction number integrated value IAC. Scheduling is performed and supplied to each of the arithmetic processing units 10 to 13.

Therefore, in order to avoid data hazards and resource conflicts due to data dependencies, non-operational instructions (n
p) is stored in the processing content memory 6 and only valid instructions excluding useless no-operation instructions (np) need be stored in the processing content memory 6, so that parallel processing of instructions with the minimum program size is possible. Can be. Thereby, the parallel processing can be executed by scheduling the instructions without increasing the memory capacity.

In the present embodiment, the operation unit for executing the load / store instruction can execute other operations. However, the operation unit is provided separately as an operation unit dedicated to the load / store instruction or the load unit / store unit. The configuration may be such that parallel processing can be performed with another arithmetic unit.

Although the present embodiment shows a digital signal processor having four parallel processing units, the present invention is limited to a digital signal processor having four parallel processing units. However, the present invention can be applied to a digital signal processor having a plurality of arithmetic units capable of parallel processing.

In the present embodiment, the processing procedure map memory 2 and the processing content memory 6 are provided separately. However, one memory is divided into areas and stored in the processing procedure map memory 2 and the processing content memory 6. The contents may be stored.

The digital signal processor according to the present embodiment is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, and the like), but is applied to one device (for example, a copying machine,
Facsimile machine).

Further, in order to operate various devices to realize the functions of the above-described embodiment, an apparatus connected to the various devices or a computer in a system is required to realize the functions of the above-described embodiments. The present invention also includes a software program code supplied and implemented by operating the various devices according to a program stored in a computer (CPU or MPU) of the system or the apparatus.

In this case, the program code of the software implements the functions of the above-described embodiment, and the program code itself and means for supplying the program code to the computer are provided.
For example, a recording medium storing such a program code constitutes the present invention. As a recording medium for storing such a program code, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, C
D-ROM, magnetic tape, nonvolatile memory card, R
OM or the like can be used.

When the computer executes the supplied program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) or other operating system running on the computer. Needless to say, even when the functions of the above-described embodiments are realized in cooperation with application software and the like, such program codes are included in the embodiments of the present invention.

Further, after the supplied program code is stored in the memory provided in the function expansion board of the computer or the function expansion unit connected to the computer, the function expansion board or the function expansion unit is specified based on the instruction of the program code. It is needless to say that the present invention also includes a case where the CPU or the like provided in the first embodiment performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0065]

As described above, according to the present invention, a processing content storage means for storing an instruction and a processing procedure control means for controlling a processing procedure of the instruction are provided. When executing stored instructions,
The instruction stored in the processing content storage means is read out, scheduled and supplied to the instruction execution means in accordance with the instruction of the processing procedure control means, and stored in the first storage means by the instruction execution means in accordance with the supplied instruction. Data is exchanged and instructions are executed, so that only the effective instructions are stored in the processing contents storage means without the useless non-operation instructions being stored in the processing contents storage means, and the instructions are processed in parallel. Can be executed. Thus, the number of instructions stored in the processing content storage unit can be minimized, and the instructions can be scheduled and processed in parallel without increasing the memory capacity. Further, by providing the first storage means for exchanging data with the instruction execution means, it is possible to easily control the input and output of data when executing the instruction.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a digital signal processor according to an embodiment;

FIG. 2 is a diagram showing an example of contents of a processing procedure map memory shown in FIG. 1;

FIG. 3 is a diagram showing an example of the contents of a processing content memory shown in FIG. 1;

FIG. 4 is a diagram for explaining an operation of an instruction selecting unit shown in FIG. 1;

FIG. 5 is a diagram showing an operation example of the digital signal processor according to the present embodiment.

FIG. 6 is a diagram showing an example of an instruction sequence scheduled by the digital signal processor according to the embodiment;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 processing procedure control unit 2 processing procedure map memory 3 division unit 4 quotient change detection unit 5 instruction pointer counter 6 processing content memory 7 instruction output unit 8 buffer unit 9 instruction selection unit 10 program counter 11 first operation unit 12 second Arithmetic unit 13 Third arithmetic unit 14 Register unit 15 Data memory PAD Program address IPN Instruction issue pattern IAC Effective instruction number integration value QAD quotient MOD Remainder RIV quotient change detection signal IS0 to IS3 instruction

Claims (14)

[Claims] 1. A processing content storage means for storing an instruction, a processing procedure control means for controlling a processing procedure of the instruction stored in the processing content storage means, and a processing procedure according to the control of the processing procedure control means. An instruction execution means for executing an instruction supplied from the content storage means, and a first data storage means for supplying data to the instruction execution means and storing data processed by the instruction execution means. And a digital signal processor. 2. An apparatus according to claim 1, further comprising an instruction output means for selecting any one of a plurality of instructions supplied from said processing content storage means and outputting the selected instruction to said instruction execution means in accordance with control of said processing procedure control means. The digital signal processor according to claim 1, wherein: 3. The instruction output means includes: an instruction holding means for holding an instruction supplied from the processing content storage means; and an instruction output means provided from the processing content storage means or the instruction holding means under control of the processing procedure control means. 3. The digital signal processor according to claim 2, further comprising: an instruction selecting unit that selects any one of the plurality of instructions to be output and outputs the selected instruction to the instruction executing unit. 4. The processing procedure control means according to claim 1, wherein said processing procedure control means includes processing procedure storage means for storing scheduling information comprising instruction issue destination information and an integrated value of the number of valid instructions. Digital signal processor according to any one of the preceding claims. 5. A digital signal processor having a plurality of processing means, wherein scheduling information comprising instruction issue destination information for the plurality of processing means and an integrated value of the number of valid instructions from a program start address is stored. A processing procedure storage unit for storing, a processing content storage unit for storing an instruction to be supplied to the plurality of processing units, and supplying data to the plurality of processing units, and processing the data processed by the plurality of processing units. A second data storage unit having a function of storing; a first data storage unit for storing data supplied to the second data storage unit and data subjected to processing stored in the second data storage unit; And a data storage means. Based on the scheduling information stored in the processing procedure storage means, an instruction is issued from the processing content storage means. Digital signal processor and supplying to said plurality of processing means out look. 6. A digital signal processor having a plurality of processing means, wherein scheduling information comprising instruction destination information for the plurality of processing means and an integrated value of the number of valid instructions from a program start address is stored. Storage means for storing instructions to be supplied to the plurality of processing means, address generation means for generating an address for reading an instruction from the processing content storage means, Division means for calculating and outputting a quotient and a remainder from the integrated value of the number of valid instructions stored in the procedure storage means and the number of the plurality of processing means; and detection for detecting a change in the quotient output from the division means Means, instruction holding means for temporarily storing an instruction supplied from the processing content storage means, and the processing content storage means or An instruction selecting means for selecting and outputting a plurality of instructions supplied from the instruction holding means in accordance with the outputs of the dividing means and the processing procedure storing means; and one of the plurality of processing means, with an unconditional branch / condition A program counter that performs a process including a branch / procedure call and generates an address for reading the scheduling information from the processing procedure storage unit; and supplies data to the plurality of processing units and is processed by the plurality of processing units. A second data storage unit having a function of storing the processed data, and a storage unit for storing data supplied to the second data storage unit and data subjected to processing stored in the second data storage unit. And a first data storage means. 7. The digital signal processor according to claim 6, wherein said address generation means generates an address according to an output of said detection means. 8. The method according to claim 1, wherein said address generation means generates an address in accordance with an instruction supplied to said program counter and an integrated value of the number of valid instructions stored in said processing procedure storage means. A digital signal processor according to claim 6. 9. The first data storage means comprises:
9. The digital signal processor according to claim 1, further comprising an input / output unit for a digital signal mapped on an address space of said data storage unit. 10. The processing procedure storage means and the processing content storage means store a processing procedure storage area for storing information stored in the processing procedure storage means and information stored in the processing content storage means. 10. The digital signal processor according to claim 1, comprising a storage medium divided into a processing content storage area for processing. 11. A method for storing scheduling information and an instruction separately, scheduling the instruction based on the scheduling information, exchanging data stored in a storage medium according to the scheduled instruction, and executing the instruction. A parallel processing method. 12. The scheduling information includes instruction issue destination information and integrated value information of the number of valid instructions, and reads out an instruction based on the two pieces of information to generate a scheduled instruction. 12. The parallel processing method according to item 11. 13. A computer-readable recording medium on which a program for causing a computer to function as each of the means according to claim 1 is recorded. 14. A computer-readable recording medium on which a program for causing a computer to execute the processing procedure of the parallel processing method according to claim 11 or 12 is recorded.