JPH10260832A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the schedule time to parallelly execute an instruction for successive execution. SOLUTION: An instruction interpretation circuit 204 in a processor 200 generates a group of interpretation instructions to branch blocks of a program and stores it in interpretation instruction memory 201 when a scalar processor 100 carries out the program. Each interpretation instruction includes the numbers of physical resources (a computing element, a register, etc.) of a transfer source and a transfer destination which are decided by an instruction scheduler 104 to each of plural instructions that are decided as parallelly executable by the scheduler 104. When the branch block is executed again later, an interpretation instruction string in the memory 201 is successively carried out. A transfer circuit 203 supplies data to an input of a computing element that is selected for an instruction when the computing element of the transfer source generates the data that is used for an operation which is requested by each interpretation instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superscalar information processing apparatus for executing instructions of a program for sequential execution in parallel.

[0002]

2. Description of the Related Art In order to improve the processing speed of an information processing apparatus controlled by an instruction, there is a method that utilizes the parallel execution potential of an instruction sequence. For example, as shown in Mike Johnson's "Superscalar Processor", Nikkei BP Publishing Center, 1994, pp. 104-118 and 125-144 (hereinafter referred to as Reference 1). In the superscalar method, a plurality of arithmetic units are provided in one processor, and a plurality of instructions are executed in parallel using different arithmetic units. Instructions that can be executed in parallel are extracted by examining the competition of hardware resources used by a plurality of instructions and the dependence of data accompanying instruction execution in a pipeline stage before the instruction execution stage, for example, the instruction decode stage. .

As described on page 125 and subsequent pages of Document 1, an out-of-order method is also possible. In this method, the range of searching for instructions that can be executed in parallel is expanded, and instructions that can be executed in parallel are executed in an order different from the original instruction order.

[0004] As a method of realizing out-of-order execution, Tomasuul described on page 109 of Document 1 is described.
o Algorithms are known. In the Tomasulo algorithm, decoding of a certain instruction is completed, and after an arithmetic unit used by the instruction and necessary input data are decoded, the instruction is stored in a kind of instruction buffer called a reservation station. The reservation station is used as a storage location for instructions waiting to be executed.
The instruction that has been executed by the arithmetic unit notifies the end to all the instructions in the reservation station. Thus, the instruction in the waiting state can check its own feasibility, and is sent to the arithmetic unit sequentially from the executable instruction. As a result, the instructions can be executed in an order different from the original instruction sequence. As a method of using a fine dependency between two instructions, Hennesynd Patt
erson, "Computer Architecture
ureA Quantitative Approach
(Second edition) ", Morgan
Kaufmann Publishers, Inc. 1
995, PP. 147 (hereinafter referred to as reference 2), data forwarding is known. In this method, when there is an instruction using the value of a certain register as input data, the execution of the instruction is not started after the value of the register is determined, but from the arithmetic unit that is going to update the value of the register. Transfers the value directly to the instruction and starts executing the instruction before the register value is determined.

[0005] As described above, the method of recognizing the relationship between the instructions prior to the execution of the instructions is to specifically determine the hardware resources used by the instructions and to execute the instructions as soon as necessary data is prepared. Starting is realized as a control method. However, the combinational logic for realizing this control method tends to be large-scale, and the circuit provided for high-speed execution may possibly consume the entire execution time. As one solution to avoid such a situation, VLIW (VeW
ry Long Instruction Word)
(Literature 2, pages 278 to 289) has been proposed. In the VLIW, a plurality of instructions that can be executed in parallel by a compiler are extracted in advance, and those instructions are put together as one instruction word. This makes it possible to reduce the circuit scale required for the above recognition. However, it is necessary to recompile all programs because the instruction word changes.

[0006]

As described above, the VLI
W cannot make effective use of executable binary file assets. Further, in a supercomputer or a signal processing dedicated processor, a numerical operation program using a lot of loops can be scheduled by compiling, but these are only a few special examples. In a general program, there are dynamic changes in the instruction execution time such as frequent branch instructions and memory accesses, and therefore there is a limit in statically optimizing the order of hardware use by a compiler. Therefore, it is important for a general-purpose processor to extract instruction parallelism using hardware and determine an instruction execution order, that is, scheduling, as in the superscalar method. However, there is a problem that the operation speed of the scheduling portion determines the operation speed of the whole processor because the amount of logic required by the scheduling using hardware is enormous.

In the reservation station,
Even for instructions that are obviously not executable, the feasibility check is performed wastefully. Further, when more instructions than the number of arithmetic units can be executed, it is necessary to perform processing such as selecting an instruction to be executed. This problem leads to a waste of time before the instruction is executed in the arithmetic unit.

An object of the present invention is to provide an information processing apparatus capable of executing a plurality of instructions in parallel with less overhead.

A more specific object of the present invention is to provide an information processing apparatus capable of reducing a decrease in instruction execution speed due to instruction scheduling.

Another object of the present invention is to provide an information processing apparatus capable of starting execution of an instruction with less delay as soon as data required by the instruction is prepared.

[0011]

In order to achieve the above object, an information processing apparatus according to the present invention comprises a plurality of first type arithmetic units and a plurality of first type registers including a plurality of first type registers. Physical resources and a plurality of first resources included in the program to be executed
A plurality of first-type instructions that can be executed in parallel are selected from among the plurality of types of instructions, and a plurality of first-type physical resources used for executing the respective first-type instructions are assigned to the selected plurality of physical resources. Assigned to the first type instructions and using their assigned physical resources to allocate their first type instructions.
An instruction scheduler for controlling execution of the selected plurality of first-type instructions so as to execute the same type of instruction in parallel, and using the instruction scheduler to execute the first-type instructions of the program in the superscalar mode. Be executed. In the present invention, each time a plurality of first type instructions are executed in parallel by the instruction scheduler, the plurality of first type instructions executed in parallel are assigned to the plurality of first type instructions by the instruction scheduler. A memory for storing at least one second type instruction capable of identifying the physical resources of the above, a plurality of second type physical resources including a plurality of second type arithmetic units and a plurality of second type registers, When the program is executed again, at least one second type stored in the memory corresponding to the plurality of first type instructions instead of the plurality of first type instructions included in the program. And an instruction execution circuit for executing the instruction of
A plurality of second type physical resources corresponding to a plurality of physical resources identifiable from the one second type instruction assigned to each of the plurality of first type instructions corresponding to the first type instruction To execute the second type of instruction.

As a result, when re-executing the first type instruction sequence in the program, the second type instruction stored in the memory is executed to execute the original first type instruction at the time of execution. In this case, the information of the execution order of the instruction and the physical resources such as the arithmetic unit to be used is used. As a result, the instruction scheduler does not need to recognize the possibility of parallel execution again, and the second type of instruction sequence can be executed at higher speed.

Further, by increasing the operation clock of the memory and the instruction execution circuit to be higher than that of the instruction scheduler, the execution speed of the second type of instruction sequence can be increased. For this purpose, it is desirable that the plurality of second type physical resources be provided separately from the plurality of first type physical resources. However, it is also possible to realize these physical resources with a common physical resource.

In a more specific aspect of the present invention, each second type instruction has information on a physical resource to be used and a physical resource for generating data necessary for executing the instruction, and the information is corresponded as position information. An instruction queuing circuit for waiting for execution of each second type instruction is provided in the attached second type instruction transfer circuit. As a result, it becomes possible to check the feasibility of an instruction that cannot be executed, which has occurred in the reservation station, and to reduce the logic and time required for selecting an instruction immediately before execution.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an information processing apparatus according to the present invention will be described in more detail with reference to some embodiments shown in the drawings. In the following, the same reference numerals represent the same or similar ones.
In the second and subsequent embodiments, differences from the first embodiment will be mainly described.

<Embodiment of the Invention> (1) Apparatus Configuration In FIG. 1, an information processing apparatus comprises two processors 10
It is composed of 0 and 200. A superscalar processor 100 extracts parallel executable instructions from a program created for sequential execution and can execute individual scalar instructions in parallel. Super scalar processor 1
00 is the instruction cache 101 connected to the main memory 10
And an instruction fetch circuit 102, an instruction decoder 103, an instruction scheduler 104, a plurality of arithmetic units 105, and a register file 107. Reference numeral 200 denotes a processor for executing instructions in the program executed by the superscalar processor 100 at a higher speed than the superscalar processor 100 when the program is executed again. Processor 200 is configured to operate at a faster machine clock than superscalar processor 100. When the above program is first executed in the superscalar processor 100, as a result of scheduling by the instruction scheduler 104, addresses 301,
Supply the numbers of physical resources such as arithmetic units and registers assigned to each instruction, specifically, the number 302 of the destination physical resource to which the execution result data of the instruction is transferred and the data used for executing the instruction The transfer source physical resource number 303 is supplied. In this processor 200, the instruction translation circuit 204 generates an instruction (hereinafter, referred to as a translation instruction) that specifies a process equivalent to those instructions, reflecting the schedule results, and generates the generated translation instruction sequence. It is stored in the translation instruction memory 201.

The processor 200 has a plurality of arithmetic units 205 for executing the translation instructions stored therein and holds data used by these arithmetic units or operation result data generated by these arithmetic units. , And a register IO 207 used for exchanging data between the temporary register 206 and the register file 107. The number of these arithmetic units 205 depends on the superscalar processor 10.
This is the same as that of the arithmetic unit 105 in 0, and the number of temporary registers 206 is also the same as the number of registers that can be specified by the instruction included in the register file 107. Of course, it is also possible to configure with fewer arithmetic units 205 and temporary registers 206 depending on the number of physical resources used in the translation instruction.

Each of the translation instructions stored in translation instruction memory 201 includes instruction information on a plurality of scalar instructions, decoder 202 decodes the translation instruction read from translation instruction memory 201, and transfer circuit 203 , The data required by each of the plurality of operations specified by the instruction decoding information provided by the decoder 202 is the plurality of arithmetic units 2
05, the calculation is started in synchronism with the supply from any one of the components. The plurality of operation units 205 are configured to execute operations requested by the plurality of scalar instructions in parallel and to execute the operation at a higher speed than the plurality of operation units 105 in the superscalar processor 100.

The transfer circuit 203 includes the instruction scheduler 10
Wait for the instruction to be executed as in step 4,
The basic function is to distribute the instruction to any of the computing units when it becomes executable. However, the transfer circuit 203 is different from the instruction scheduler 104 in that, as described later, which of the preceding instructions should wait for the execution end is already decoded as a position on the transfer path. For this reason, the instruction scheduling using the transfer circuit 203 substantially eliminates the need for a circuit for judging the executable instruction and controlling the execution order.
04 can be executed at higher speed.

As described above, the processor 200 controls the instruction scheduler 104 in the superscalar processor 100.
To execute instructions at a faster clock than executing such a schedule. Note that the two processors 100 and 200 do not necessarily need to be physically close to each other, but the signal line 301
305 require an operation speed comparable to that of a normal processor internal signal, and are preferably formed on the same silicon substrate, for example.

(2) Instruction execution mode The instruction fetch circuit 102 in the superscalar processor 100 uses the address of the instruction sent to the instruction decoder 103 as the instruction address 300 as the translated instruction storage area 21
1 is also supplied. Referring to FIG.
Then, the translation instruction for this instruction is stored in the translation instruction memory 20.
1 is searched (step 221).
If there is an instruction line corresponding to the instruction address in the translation instruction memory 201 (step 222), the translation instruction stored in that line is read (step 22).
3). The translation instruction decoder 202 decodes the read translation instruction and converts the information on the source physical resource included in the instruction into the position information inside the transfer circuit 203 (step 224). The transfer circuit 203 sequentially operates the arithmetic unit 205 and the temporary register 20 from an instruction having data necessary for execution.
6. Transfer the data to the register IO207. The arithmetic unit 205 having received the data transmits the operation result again to the transfer circuit 20.
3 and the operation instructions are sequentially executed (step 22).
5). When the same instruction start address as the instruction address 300 is not found in the translation instruction storage area 211 in step 222, the processor 200 does not operate and the superscalar processor 100 executes the instruction. That is, the instruction is decoded by the instruction decoder 103 (226), the instruction execution order is determined by the instruction scheduler 104 (227), and then the instruction is executed by the arithmetic unit 105 (228).

(3) Superscalar processor 100 The outline of this processor is as follows. The instructions stored in the instruction cache 101 are stored in the instruction fetch circuit 10.
2 and is sent to the instruction decoder 103. The instruction decoder 103 decodes information of an input / output register number and an operation type indicated by the instruction word. Each of the instruction fetch circuit 102 and the instruction decoder 103 includes a plurality of instructions (4
~ 8 instructions) can be processed simultaneously. Decoder 1
03 uses the so-called register renaming technique,
It may have a function of converting a logical register number that can be specified by a program into a large number of physical register numbers inside the processor.

The instruction scheduler 104 includes the instruction decoder 1
With respect to a plurality of instructions sent from 03, the assignment of arithmetic units used by the instructions and the order of execution of the instructions are determined. More specifically, in the present embodiment, the branch instruction processing unit is also treated as one arithmetic unit. Multiple arithmetic units 105
, There are a plurality of arithmetic units having different functions, such as an integer arithmetic unit, a floating-point arithmetic unit, and a branch instruction processing unit, and a plurality of arithmetic units having the same function. Although the number of arithmetic units limits the number of instructions that can be executed in parallel by the processor, the present embodiment is not limited to a specific number of arithmetic units. If there are a plurality of input data latches for any of the arithmetic units 105, it is assumed that each input data latch is assigned a uniquely identifiable number. As this number, for example, a number obtained by adding the number of the input data latch to the lower bit side of the identification number of the arithmetic unit that outputs the operation result data to be supplied to the input data latch can be used.

In principle, the order of execution of instructions is to execute them in order from the instruction having input data necessary for executing the instruction.
For this control, for example, the Tomasulo algorithm can be used. In the instruction scheduler 104, an instruction having a preceding instruction to wait for completion of execution is stalled, and the instruction having all input data necessary for executing the instruction is processed by the arithmetic unit 10
5 is sent. When the instruction is completed, the register number having the determined value is transmitted from the register file 107 to the instruction scheduler 104 in the sense that the register value is determined. The instruction scheduler 104 checks whether there is an instruction that uses the register of the transmitted number as an input value among the stopped instructions, and whether there is an instruction having all input values. If there is, the instruction is sent to any of the arithmetic units 105.

The execution order of instructions is dynamically determined by the operation of the instruction scheduler 104 described above, and as a result, an arithmetic unit used by each instruction and an arithmetic unit that has operated data serving as an input value of the instruction can be determined. . Therefore, if a number for identifying a physical resource such as an arithmetic unit or a register is defined as a physical resource number, a dynamic execution history of an instruction can be viewed as a history of data transfer from a certain physical resource to a certain physical resource. The instruction scheduler 104 executes an instruction such as an execution instruction address 301 which is an instruction address of an instruction sent to the arithmetic unit, and a destination physical resource 302 and a source physical resource 303 for a transfer destination and a transfer source of data transfer caused by the instruction. Instruction translation circuit 20 as history
4

In the following, the superscalar processor 1
The details of the circuit of 00 will be further described. The instruction fetch circuit 102 supplies the address 300 of the fetched instruction to the instruction decoder 103 and the processor 200. When the address of the instruction to be executed by the processor 200 is fetched from the instruction fetch circuit 102, the processor 200
Fetches the instruction sequence to be executed as early as possible, and the subsequent superscalar processor 10
0 can perform no processing on the instruction. If the instruction address 300 cannot be fetched from the instruction fetch circuit 102 due to restrictions on the mounting area or the like, the instruction address 300 should be fetched from a place closer to the instruction execution stage, such as the instruction decoder 103, the instruction scheduler 104, or the computing unit 105. Is also possible. The instruction fetch circuit 102 obtains an executable instruction in advance and extra by a branch instruction prediction function, an instruction buffer function, and the like in order to execute the acquisition of the instruction sequence from the instruction cache 101 without delay. It has a function known per se. Therefore, the instruction sent from the instruction fetch circuit 102 to the instruction decoder 103 can be considered as an instruction sequence determined to be executed by the information processing device.

In this embodiment, an instruction in the format shown in FIG. 4 is used. This instruction format is called R
This is a typical example used in an ISC processor, and a register number and the like can be obtained by merely dividing a bit field of an instruction without special interpretation. The X format is a format used for a general arithmetic and logic operation instruction, and includes an operation code (OPCD) field indicating an instruction type at the beginning, a target register field (RT) which is a register number storing an operation result, and an input numerical value of the operation. The stored register number is composed of two operand register fields (RA, RB) and an extended function information field (EO). Load D format,
This is the format of the store instruction. The operation code field, the target register field, and the operand register field have the same function as the X format, and the displacement field (D) stores an added value for calculating a memory address accessed by a load or store instruction. The memory address is the sum of the value of the operand register (RA) and the value of the displacement field. From the operation code (OPCD) field, the type of the arithmetic unit used in the execution of the instruction can be determined.
The registers used by the instruction are determined from the RA and RB fields.

In FIG. 3, the instruction decoder 103 in the superscalar processor 100 divides the instruction sent from the instruction fetch circuit 102 according to the instruction format illustrated in FIG. That is, the latch 110
To 113 are an operation code (opcd), a target register (RT) number 117, an operand register (RA) number 118, and finally an operand register (R
B) or the value of the displacement (D). The operation code decode circuit 115 is connected to the latch 11
It decodes the operation code held by 0 and generates a determination signal 114 as to whether or not to use the operand register (RB) and an operation unit number (FU) 116 which is a physical resource number of the operation unit used in the instruction. When the determination signal 114 is at a high level, the shift circuit 122 shifts the 16-20 bits of the instruction field to the lower 27-31 bits,
The upper 16-20 bits are refilled with 1 and the extension data (E
X) Output as 119. When the determination signal 114 is Low, the displacement information of 16-31 bits of the instruction field is directly stored in the extension data (EX) 11.
9 is output.

The instruction scheduler 104 executes the above-described concept of instruction scheduling using the write scoreboard 120, the read scoreboard 121, and the instruction execution buffers 0 to 3. Both the write scoreboard 120 and the read scoreboard 121 are memories using register numbers as address information. The write scoreboard 120 has a 2-bit area for each register number as memory data, and determines how many preceding instructions from the instruction execution buffer 0 to the instruction execution buffer 3 to read the register to be written exist. Counter. The read scoreboard 121 has a 1-bit area for each register number as memory data, and indicates whether or not there is an instruction to update the register contents to be read among the instructions being executed by the arithmetic unit. . The instruction execution buffer 0 to the instruction execution buffer 3 constitute a first-in first-out (FIFO) queue, and the operation unit number 1 which is the output of the instruction decoder 103
16, the target register number 117, the operand register number 118, the extension data 119, and the instruction address 125 from the instruction fetch circuit 102. The instruction selection circuit 123 selects, from among the instructions stored in the above-mentioned FIFO queue, the one that is executable and that has passed the most time since entering the FIFO queue.

The details of instruction scheduling are as follows:
Information of each register number sent from the instruction decoder 103 is input to the write scoreboard 120 and the read scoreboard 121. In the meantime, the instruction is taken into the instruction execution buffer 0. However, when the hit signal 242 is High, the translation instruction is executed, so that scheduling of the instruction sent from the instruction decoder 103 and subsequent operations are canceled during that time. When the output values of both scoreboards are 0, it means that neither the target register nor the operand register used by the instruction is being used by the preceding instruction. That is, it is understood that the instruction is executable. Instructions that are not executable at this stage need to wait for a change in the state of any of the registers, and as subsequent instructions arrive from instruction decoder 103, deeper positions in the FIFO queue (instruction execution buffers 1-3). Proceed to. The output signals of the write scoreboard 120 and the read scoreboard 121 and the operation end signal 124 from the register file 107 are always notified to the instruction execution buffers 0 to 3 via the broadcast circuit 125.
With this notification, the instruction in which the writing to the operand register has been completed and the reading of the target register by the preceding instruction has been completed can be executed.

The instruction selection circuit 123 has an instruction execution buffer 0
３3, the executable instruction is fetched and the number of the operand register is registered in the register file reading circuit 12.
6, the instruction address, the target register number, the arithmetic unit number, and the extended data are sent to the instruction issuing circuit 127. The register file read circuit 126 reads the contents of the operand register from the register file 107 (FIG. 1) and sends out the operand data to the instruction issuing circuit 127 as operand data.

The instruction issuing circuit 127 sends out a target register number, operand data, and extension data to the arithmetic unit 105 identified by the arithmetic unit number. The maintenance operation of the write scoreboard 120 includes the instruction decoder 1
The number of the operand register (both RA and RB) of the instruction newly arriving at the instruction execution buffer 0 from 03 is sent to the set terminal (S) of the write scoreboard 120, and the counter value of the register is incremented. Also,
The operand register (RA, R
B) is the register file reading circuit 126
Is sent to the reset (R) terminal of the write scoreboard 120, and the counter value of the corresponding register becomes 0. When an instruction to update a register is issued, the read scoreboard 121 receives a notification of the target register number from the instruction issuing circuit 127 at the set terminal (S), and sets a flag 1 indicating that updating is in progress. This flag is used as the operation end signal 124
Reset by The instruction address of an instruction that can be executed from the concept of the translation instruction described above is transferred as the execution instruction address 301, the operation unit number and the target register number are transferred as the destination physical resource number 302, and the operand register number and the extended data are transferred. It is sent to the instruction translation circuit 204 as the original physical resource number 303. The operation of the instruction scheduling circuit described above is a process that requires at least two stages or more if the operation of the instruction decoder 103 takes one pipeline stage.

(4) Processor 200 (4a) Program Example In the following description, the program example shown in FIG. 5 is used. The program example of FIG. 5 is composed of five types of instructions.
The fd instruction 501 loads the floating-point value from the value stored in the sixth register and the memory address indicated by the displacement 8 and stores it in the floating-point register 1. The ai instruction 502 adds 4 to the value of the sixth register and sets the value of the sixth register again. The fm instruction 503 stores again the product of the numbers stored in the floating-point registers 1 and 2 in the floating-point register 1 again.
04 compares whether the numerical value of the floating-point register No. 1 is larger or smaller than the numerical value of No. 0, and stores the comparison result in the condition register No. 6 (CR6). Last bc instruction 505
Is a branch instruction, and as a result of the fcmp instruction 504, when the value of the floating-point register No. 1 is smaller than the value of the No. 0 register, branch to the label_L10.

FIG. 6 is a graph theoretically showing the relationship between the instruction sequence referring and updating registers and the instruction.
This diagram conceptually shows the instruction execution process, and does not directly correspond to the mechanism in the apparatus of the present embodiment.
As can be seen from FIG. 6, the graph nodes 601, 602, 6
After the register indicated by 03 is updated by the preceding instruction, it is immediately referred to by the subsequent instruction.If the register indicated by the preceding instruction can simultaneously transfer the execution result to both the register to be updated and the arithmetic unit requiring the value, , The overall execution time can be reduced. Such an execution control method is called forwarding, and the instruction scheduler 104 determines a transfer path by decoding an instruction sequence before execution. That is, when the superscalar processor 100 executes the instruction sequence shown in FIG. 5, the execution history corresponds to the graph shown in FIG.

By the above-mentioned forwarding, the operation result is scheduled to be transferred by the shortest path. The register numbers (register names) storing the input values for the instruction sequence in FIG. The register numbers (register names) in which the results are stored are arranged. If a node indicating an instruction type in this graph is read as an arithmetic unit, the branch of the graph indicates data transfer between the register and the arithmetic unit or between the arithmetic unit and the arithmetic unit.

(4b) Generation of Branch Block The translation instruction in the present embodiment is a set of data transfer represented by this branch, and the circle number attached to the side of the branch to identify the branch is the minimum of the translation instruction. Is a unit. Also, as indicated by blocks surrounded by broken lines in FIG. 7, the group of instructions shown in FIG. 5 can be classified into a block 670 as an input value, a block 671 as an operation content, and a block 672 as an operation result. It is possible. This means that when considering block 671 as one macroinstruction, block 670 corresponds to an initialization condition for its execution and block 762 corresponds to an end condition. Based on the above concept, the instruction translation circuit 204 creates a translation instruction according to the following procedure.

The input signals are the execution instruction address 301, the transfer destination physical resource number 302, and the transfer source physical resource number 303 described above. The outputs are the three types of translation instructions shown in FIG. Instruction body 702,
This is an end instruction 703. The translation instruction forms one unit by a set of an initialization instruction 701, an end instruction 703, and one or a plurality of translation instruction bodies 702 sandwiched therebetween. First, the translation instruction generation circuit 204 divides an input signal sent every time one instruction is executed into branch blocks according to the following criteria.
A plurality of instructions included in this branch block correspond to one of the translated instructions.
Corresponds to the unit.

The translation instruction generation circuit 204 observes the transfer destination physical resource number 302 and recognizes that the branch instruction is executed when the transfer destination is the branch instruction processing unit. A branch block is an instruction sequence sandwiched between a branch instruction and a branch instruction, and starts with a non-branch instruction as in the example shown in FIG.
End with a branch instruction. However, since the dynamic instruction execution order is based on the instruction execution result here, it does not matter whether or not one of the instructions 501 in FIG. 5 is a branch instruction as an assembler language, for example. In other words, when the execution address is changed by a certain branch instruction in the program and jumps to the instruction 501, the instructions 501 to 505 form one branch block. Also, if the branch instruction 505 is
Is not satisfied and the branch to the instruction 501 is not taken, a new branch block is started from the instruction executed next to the branch instruction 505. Therefore, from this definition, an instruction in a program may belong to a plurality of branch blocks. Further, since the entire program is formed by a plurality of branch blocks, it is considered that the entire executed program is sequentially converted into a translation instruction.

(4c) Translation Instruction The function of generating a translation instruction is roughly classified into two functions. One is generation of a translation instruction body 702. As shown in FIG. 11, the field of the translation instruction body 702 includes the transfer destination and the transfer source of the data transfer, and the transfer destination physical resource number 30 output from the superscalar processor 100.
2 in the transfer destination field 704 and the transfer source physical resource number 3
03 may be stored. The instruction length of the translation instruction body 702 is finite, and if it exceeds the instruction length, a new translation instruction body 702 is separately generated. The second of the roughly classified functions is generation of an initialization instruction 701 and an end instruction 703. As will be described later, the instruction translation circuit 204 includes an instruction translation circuit that is semantically equivalent to the scoreboard 751 shown in FIG. The scoreboard records, for each register incorporated in the superscalar processor 100, the number of the computing unit that has performed the writing operation and the computing unit number that has performed the reading operation in the register.
When the branch block is changed, the entire scoreboard is cleared to zero. Since the recording of this number follows the instruction execution order of the superscalar processor 100, the number of the arithmetic unit that has recently read or written is recorded when the branch block ends.

In this embodiment, a processor for executing a translation instruction exists independently of the superscalar processor 100, and a temporary register 206 is used as a register. Therefore, the temporary register 206 needs to be initialized. The translation instruction generation circuit 204 extracts a register that is read out but not written in the scoreboard 751, and generates an initialization instruction 701. That is, the register satisfying the above condition is the block 67 in FIG.
A register whose value is set outside the branch block of interest, such as 0. The transfer destination field of the initialization instruction 701 is the number of a temporary register provided inside the processor 200, and the transfer source is the physical resource number of the register IO207. The register IO 207 has a data transfer function between the register file 107 of the superscalar processor 100 and the temporary register 206. The instruction start address of the initialization instruction 701 stores the address of the head instruction of the branch block.

Similarly, the end instruction 703 is sent to the scoreboard 75.
1 is generated with reference to FIG. The end instruction 703 exists to store the result when the branch block ends from the temporary register 206 to the register file 107. The transfer destination field of the end instruction 703 is the physical resource number of the register IO 207, and the transfer destination field is the register number that has been written on the scoreboard 751 when the branch block ends. The translation instruction generated as described above is transferred to the writing circuit 214 in the translation instruction memory 201 at the same time when the branch block ends. The above is a brief description of the generation of a translation instruction.

(4d) Instruction Translation Circuit 204 As shown in FIG. 8, the instruction translation circuit 204 includes scoreboards 751a and 751b, an initialization instruction buffer 130, a translation instruction body buffer 131, an end instruction buffer 132 and the like. . Scoreboards 751a and 751b
The read section and W of the scoreboard shown in FIG.
This is a scoreboard that holds information described in the write section, and holds the arithmetic unit numbers held in the read section and the write section, respectively. When the operation unit number is the branch instruction processing unit, the branch detection circuit 133 generates a reset signal 134 and a translation instruction transmission request signal 133a. Thus, the above-described branch block can be recognized. Scoreboard 751 receiving reset signal 134
a and 751b clear all stored contents to zero.

The translation instruction body is generated by the instruction scheduler 1
The process is executed every time the execution instruction address 301, the transfer destination physical resource number 302, and the transfer source physical resource number 303 are sent from 04. That is, as in the concept described with reference to FIG. 12, the physical resource of the transfer source is the arithmetic unit if the arithmetic unit number is stored in the scoreboard 751b.
If the arithmetic unit number is not stored in the scoreboard 751b, the operand register is the transfer source. The selection is performed by the selection circuit 135. The transfer destination is either the target register or the arithmetic unit. Therefore, a maximum of three sets of transfer sources and transfer destinations are generated from the instruction with two operands and one target, and these are stored in the translation instruction buffer 131. The initialization command and the termination command are generated in synchronization with the reset signal 134. The reset signal 134 is input to the 0 detection circuits 136a and 136b, and outputs a register number whose stored value in each scoreboard is 0. The output of the 0 detection circuit 136a of the scoreboard 751a specifies the transfer destination of the end instruction and is stored in the end instruction buffer 132. 0 detection circuit 136b of scoreboard 751b
Is output by the condition determination circuit 137 to the scoreboard 7
It is combined with the output result of 51a. The operation of the condition determination circuit 137 is to select a register number having a read record among register numbers having no write record output from the 0 detection circuit 136b. Condition judgment circuit 13
The register number output from 7 is a number required for initialization, that is, for transferring the contents of the register file 107 to the temporary register 206. The initialization instruction of the processor 200 is transmitted to the register file 107 through the register IO207.
Is transferred, the transfer source is the register IO20
7. The transfer destination is the temporary register 206. This initialization instruction is stored in the initialization instruction buffer 130. Finally, the translation instruction sending circuit 138 combines the initialization instruction, the translation instruction body, and the end instruction in this order, and outputs the result to the translation instruction memory 201.

(4e) Translation Command Memory 201 Referring to FIG. 9, the translation command memory 201 includes a writing circuit 214, a translation command storage area 211, and a reading circuit 213. The figure shows the translation instruction decoder 2
02 is also shown. Translation instruction storage area 211
Are a plurality of memory cells 23 composed of MOS transistors
3 and 234, and an associated control circuit (A) 235;
This is a memory array including a control circuit (R) 236 and other circuits. Although the translation instruction storage area 211 has a larger number of memory cells repeatedly and forms a cell array as a whole, these memory cells are not shown for simplicity. Translation instruction storage area 211
Are a plurality of memory cells (M1) 233 for storing an instruction start address included in a translation instruction and a plurality of memory cells (M) 234 for storing a physical resource number as a transfer source.
It is composed of Each memory cell is a one-bit cell. To hold the information, memory cells for a plurality of bits provided in the translation instruction storage area 211 are used. All the memory cells 233 and 234 for several minutes are not shown. For convenience, a group of memory cells arranged in a horizontal direction is called a line, and a group of memory cells arranged in a vertical direction is called a column.

The write circuit 214 is provided for the instruction translation circuit 20
When the translation instruction supplied from line 4 via the line 219 is not stored in the translation instruction memory 201 yet, the translation instruction is stored in the translation instruction storage area 211. At this time, the translation instruction is the initialization instruction 701 shown in FIG.
When, the instruction 701 is stored in any one line in the translation instruction storage area 211. Each transfer source in this instruction corresponds one-to-one with a plurality of physical resources that can be transfer destinations, and is stored in a horizontal storage position defined for the corresponding physical resource. That is, the transfer source paired with the transfer destination is stored in the horizontal position corresponding to each of the plurality of transfer destinations in the translation instruction 701. For this purpose, in the write circuit 214, the column decoder 270 decodes each transfer destination in the translation instruction, and calculates the position of the translation instruction storage area 211 in the x direction. The write amplifier 271 writes the source data paired with the destination at the calculated position. A plurality of translation instructions sequentially given from the instruction translation circuit 204 are stored in the translation instruction storage area 21.
Instructions are sequentially written to columns in which no instruction has been stored. Such writing is performed by the write control circuit 21.
2 is performed. Depending on the translation command, the same transfer destination may be included. When storing such a translation command in the translation command storage area 211, it is necessary to store the transfer source information in the translation command storage area 211 by dividing it into a plurality of lines. As a result, these translation instructions are stored in a state where the transfer source is not densely packed, unlike in FIG.

When the instruction given from instruction translation circuit 204 is initialization instruction 702, the transfer destination is decoded,
The translation instruction is stored in the translation instruction storage area 211 as the translation instruction 702A. When this translation instruction given from the instruction translation circuit 204 is the end instruction 703, all 1s are stored in the memory cell (M1) 233 of the line in which the last transfer source specified by the instruction has been written into the translation instruction storage area 211. Written. Whether or not the instruction given from the translation circuit 204 is recorded in the translation memory 201 is transmitted to the write control circuit 212 by a hit signal 242 as described later. If the translation instruction does not hit, the hit signal 242 becomes Low.

Each memory cell (M1) 233 has a content matching search function, and performs a matching check between the instruction address 300 generated by the instruction fetch circuit 102 and the data held in the memory cell. If the instruction start address of a certain line, that is, all the contents of the memory cell (M1) 233 match, the potential of the signal line 230 becomes Low,
The control circuit (A) 235 outputs the read line selection signal 216
Is raised to High. Read line selection signal 21
When 6 becomes High, the memory cell of the corresponding line becomes:
The memory cell (M1) 233 is also a memory cell (M) 234.
Is output to the data output line 218. Since no selection in the column direction is performed for this read operation, data for one line reaches the read circuit 213. That is, the translation memory 201 is a kind of CAM (Contents) using the instruction start address as tag information.
It functions as an Associate Memory.

The most basic memory cell (M) 234 is
As shown in FIG. 10B, charges are stored in the capacitance between the gates of the transistor T1 and the transistor T2. When the write line selection signal 215 is High, the transistor T1 opens, and the value of the data input line 217 is stored in this inter-gate capacitance. Read line selection signal 216 is Hi
At gh, the transistor T3 opens and the stored information appears on the data output line 218 in negative logic. The data output line 218 is pulled up to a high level by a precharge transistor 238 (FIG. 9) provided for each column before reading the memory cell.

The memory cell (M1) 233 corresponds to FIG.
As shown in (a), the transistors T4, T5 and T6 are respectively the transistors T1 and T1 of the memory cell (M) 234.
Corresponds to T2 and T3 and has an equivalent role. The two inverters in the cell exist for generating the data input line 217 and the inverted signal of the instruction address 300, respectively. However, these are described in the cell for the sake of simplification of the drawing, and originally, It is only necessary that one set of these inverters exist for each column. Both the positive logical value and the negative logical value of the written data are stored in the connections of the transistors T7 and T4 and the transistors T8 and T9, and the data stored in this cell and the instruction address 300 are stored in the gate of the transistor T10. Is finally generated. That is, when the instruction start address given as the inquiry information matches the information stored in this cell, the signal line 230 connects to the memory cell (M1) 23
3 becomes conductive.

The control circuit (A) 235 comprises the circuit shown in FIG. Before the rising of the clock, the transistor T14 precharges the signal line 230 to the power supply potential. As described above, the memory cell (M1) 23
When all the transistors T10 in 3 are conducting,
After the rise of the clock, the signal line 230 goes low. Forced read request (Instruction request) 237 given by the read circuit 213
Is at a low level except during the operation described below. Therefore, the match detected in the memory cell (M1) 233 sets the read line selection signal 216 to High via the gate g1. In this manner, from the translation instruction storage area 211, the data of the line corresponding to the instruction address 300 appears on the data output line 218.

The control circuit (R) 236 is a circuit for refreshing the memory cells in cooperation with the refresh control 240 and the line decoder 239, and has a structure shown in FIG. Refresh control 2 when refreshing
40 performs a normal read operation with the refresh signal 232 at a high level. That is, the read line selection signal 216 of the line to be refreshed by the line decoder 239 is set to High. Control circuit (R)
Data is held between the gates of the 236 transistors T11 and T12. Next, the line decoder 239 raises the write line select signal 215 to High level, and the refresh control 240 changes the refresh signal 232 to Low, so that the data held in the control circuit (R) 236 passes through the precharge inverter and returns to the original state. Is written back to the line. The OR gate 241 generates a hit signal 242 in the above-described search of the instruction start address by performing a logical OR of all the read line selection signals.

In this manner, the hit check is also performed on the instruction supplied from the instruction translation circuit 204 to the translation memory 201 for the first time. If the instruction is not hit, as described above, the instruction is Memory 2
01 is written. Further, when the instruction has already been written to the translation memory 201 and is executed again, as a result of the hit check on the instruction address of the first instruction of the instruction block to which the instruction belongs, the first instruction is hit. As a result, a plurality of translation instructions for a series of instructions starting from this instruction are sequentially read from the translation memory 201.

The readout circuit 213 has a plurality of FIFO queues 2 corresponding to a plurality of physical resources which can be transfer destinations.
60 are provided, and each FIFO queue 260 is connected to a data output line 218 provided for a corresponding physical resource via a sense amplifier. Translation instruction storage area 2
The analog signal read from 11 to the transfer destination data output line 218 is written into the FIFO queue 260 after being determined as a logic signal by this sense amplifier. This writing is repeated until all 1s are read into the latch 261, that is, until the end instruction is read. At this time, the increment of the line address is transmitted from the FIFO queue 260 to the line decoder 239.

(4f) Execution Mode of Translation Instruction In FIG. 9, the translation instruction decoder 202 includes a plurality of partial decoders 202A for decoding each source field of the translation instruction and an instruction request 808 which is a transfer request from the instruction waiting unit 802. And an OR gate 202B for generating a transfer request signal 202c to the FIFO queue 260 inside the instruction reading circuit 213. All the physical resources, that is, a plurality of arithmetic units 205, a plurality of temporary A plurality of instruction signals 801 corresponding to all of the register 206 and the register IO 207 are provided. As described above, in the translation instruction memory 201, the number of the destination physical resource requested by the instruction is stored as position information in the translation instruction storage area 211, so that the translation instruction decoder 202 Only the resources need to be decoded. That is, each partial decoder decodes the corresponding transfer source field in the read translation instruction, and outputs one instruct corresponding to the transfer source physical resource.
Select and activate the Ction signal. The decoding result is based on the physical resource of the transfer destination corresponding to the partial decoder, that is, the physical resource of the transfer source in which the data to be waited by any one of the arithmetic unit 205, the temporary register 206, and the register IO 207 is generated. Is shown. Each instruction signal 801 is composed of a 1-bit data line.

In FIG. 14, the transfer circuit 203 corresponds to all the physical resources, that is, the plurality of arithmetic units 205, the plurality of temporary registers 206, and each input terminal of the register IO 207, and corresponds to the physical resources. An instruction waiting unit 802 is provided at an intersection of a plurality of instruction signals 801 of the partial decoder and an output line of a physical resource corresponding to each of the instruction signals 801. The outputs of the plurality of instruction waiting units 802 provided corresponding to the respective input terminals of the respective physical resources are wired-ORed and supplied to the input terminals.

FIG. 1 shows the internal configuration of the instruction waiting unit 802.
It is shown in FIG. The instruction signal 801 is a signal generated by the translation instruction decoder 202 described above.
This signal indicates that data transfer is necessary between the transfer source and the transfer destination related to the instruction waiting unit 802 of interest.

[0057] instruction request
Reference numeral 808 denotes a data transfer request from the instruction waiting unit 802 to the translation instruction decoder 202.
OR logic is taken by the gate in the readout circuit 213
The new transfer source data is taken out from the FIFO queue in the. The data-in signal 803 is a data line having a predetermined data width, for example, a 32-bit width, and transmits data from a transfer source. The arrival of new data in the data-in signal 803 indicates that the data-in-valid signal 80 has been received.
5 is enabled. Similarly, data-o
The out signal 804 is a data transfer line to the transfer destination,
As in the case of the ta-in signal 803, a width such as 32 bits is prepared. The validity of the data-out signal 804 is data
Indicated by a-out-valid signal 806.
The basic role of the instruction waiting unit 802 is instruct
When the ction signal 801 is valid, that is, when there is an instruction that requires data transfer, the data-in signal 803
Is output to the data-out signal 804. The operation unit and the register at the transfer destination start operation when data necessary for realizing the respective functions is prepared.

More specifically, the above control is realized by the transfer control circuit 807. The circuit and function of the transfer control circuit 807 are as shown in the circuit diagram and time chart of FIG. That is, the set of the latch 8000 and the gate 8002 and the set of the latch 8001 and the gate 8003 are i
Nstruction signal 801 and data-in-v
The state in which the “alid” signal 805 becomes High is “data”.
The signal is held until the -out-valid signal 806 becomes High. The gate 8004 outputs the signal H
The state of the latch 8005 is detected, and the state of the latch 8005 is inverted for one cycle. The output of this latch 8005 is a data-out-valid signal 806, inst
It is output as the function request 808. When the instruction signal 801 is valid, the instruction waiting unit 802 is in a state of waiting for data from the transfer source.
3, the data-out signal 804 means that the storage operation of the destination arithmetic unit or register is started.
Output the same data. Returning to FIG.
The in signal 803 and the data-in-valid signal 805 are all connected to the command waiting unit 802 located at the same horizontal position, and are connected so as to transmit electric signals all at once. Therefore, as described above, the operation of waiting for execution at the position where the instruction intersects the connection between the transfer source and the transfer destination can be realized.

Next, for the purpose of visually grasping the execution form of the translation instruction, FIGS. 17 to 20 show examples of execution of the program illustrated in FIG. In FIGS. 17 to 20, the circled numbers correspond to the circled numbers in FIG. 7, and represent the data transfer of the translation command. The circled numeral 0 corresponds to a translation instruction initialization instruction, and the circled numeral 12 corresponds to an end instruction. FIG.
7 represents a translation instruction stored in the translation instruction memory 201, and a lower area 901 corresponds to FIG.
Corresponds to the area where the instruction waiting unit 802 is provided. It corresponds to the arithmetic unit 205 to the register IO 207 in FIG. 1 arranged below the area 901, and the correspondence is indicated by the same operation name and register name as the program executed for convenience of explanation. Although only one register IO 207 is illustrated in FIGS. 17 to 20,
This is for the convenience of the drawing, and there are as many register IOs as the number of registers requiring data transfer. The black circle below the circled number 12 in FIG. 17 exists to activate the initialization instruction of the translation instruction, and is provided for each initialization instruction and for the register IO.
207. Also, from the principle of the present invention, the physical resource number of the temporary register 206 is stored in the register file 107.
Must match the register number in. When the initial value of the register data is transferred to the temporary register by the initialization instruction, the physical resource number of the temporary register 206 is also given at the same time, and the physical resource number is used in the subsequent instruction execution.

The translation instruction is the instruction signal 8
If 01 is empty, immediately from area 900 to area 901
Is transferred to the instruction waiting unit 802. That is, the execution of the translation instruction immediately shifts from the state of FIG. 17 to the state of FIG. The data transfer instruction indicated by a black dot in FIG.
, The desired data (initial contents of fp0, r6, and fp2 in this example of the program as can be seen from FIG. 7) is read as the output result of the register IO. An instruction with a circle number 0 is waiting on the output line 902 of the instruction waiting register IO in FIG. 15 (FIG. 18). When the contents of the register file 107 are output to the signal line 803 via the register IO, the circle is output. The data is transferred to each of the computing units positioned immediately below the numeral 0, and the computation is started. Here, the signal line 80
3 is a data-in signal 80 of the instruction waiting unit 802
3 and the output contents of each arithmetic unit and temporary register are sent to the instruction waiting unit 802 all at once.

The subsequent processing proceeds in a so-called thrust state. For example, when the content of r6 (register 6) is read by the circled number 0, as shown in FIG. 18, ai corresponding to the circled number 1 and the circled number 10 waiting on its output line
The data of r6 is transferred to a computing unit that performs (addition) and ifd (load floating-point data). fp2 (floating-point register 2), fp0 (floating-point register 0)
The same applies to the data transfer instruction of the circled number 0 corresponding to (No.), and as a result, the state of FIG. 19 is obtained. From the state of FIG. 19, 12 is executed by the circled number 11, and r6 after the addition is performed.
Are written back to the register file, and the state shown in FIG. 20 is obtained. Finally, the data transfer indicated by the circled numeral 12 is performed, and the values of r6, the condition register CR6, and the floating-point register fp1 are written to the register file 107, as indicated by the block 672 in FIG.

In the above translation instruction execution, the instruction waiting in the instruction waiting unit waits only for truly necessary data.
Unlike the prior art executed by the instruction scheduler 104, it is not necessary to collate all the data whose operation has been completed with all the instructions in the standby state, and thus it is possible to realize high-speed instruction standby and execution.
The fact that this process is faster than in the prior art means that even if the instruction sequence has the same execution
Are stored in the instruction decoder 10 of the related art.
3. It means that it is faster than the execution via the instruction scheduler 104.

According to the above-described embodiment, the allocation and determination of the physical resources required for the execution of the instruction are recognized at the time of the first execution of the instruction by means similar to the prior art, so that the processing time is not improved. However, since the information of the data transfer destination and the data transfer source stored in the translation instruction memory 201 is used for the second and subsequent executions of the same instruction, the processing by the instruction decoder 103 in the superscalar processor 100 and the instruction scheduler The processing by 104 can be omitted, and the speed can be increased accordingly. The substantial effect depends on the ratio of using the same instruction sequence, that is, the hit ratio of the translation memory. As is known from researches on instruction caches and the like, the locality of execution instructions is high.
And so on, it is possible to achieve a hit rate of almost 100%.

Further, in this embodiment, since an instruction to be executed waits for data necessary for execution on a path through which data is transferred, an instruction which is clearly unrelated, such as a reservation station, cannot be executed. There is no need to check for instruction executability. In fact, in the prior art, due to the above-mentioned redundant function, an instruction waiting to be executed manages data required by itself by a number, and needs to be compared with a number notified at the end of operation. For this reason, the number of instructions that can wait in one reservation station is limited to about four, and the comparison requires time. In the present embodiment, the physical resource information of the transfer destination and the transfer source is used as the position information in the transfer circuit 203, and the instruction that finally waits in the transfer circuit 203 as the instruction is a 1-bit instruction for starting the execution. Information only. Thus, the determination of the satisfaction of the execution condition is fast, and the structure is simplified, so that many instructions can be put on standby. Further, since the execution of the instruction is waited for at a place corresponding to the data transfer destination, there is no attempt to execute the instructions more than the number of the existing arithmetic units, and the arbitration circuit thereof is not required.

<Modifications> The present invention is not limited to the above embodiments, but can be implemented as the following modifications and various other modifications.

(1) In the first embodiment, apart from the plurality of arithmetic units 105 and the register file 107 of the superscalar processor 100, a plurality of arithmetic units 205 and a plurality of temporary registers 206 are provided for the processor 200. However, it is also possible to use the arithmetic unit and the register included in the former in place of the latter arithmetic unit and the register. To this end, the transfer circuit 203 of the first embodiment is
These arithmetic units and registers are connected so that data is transferred between the arithmetic unit 105 in the superscalar processor 100 and the registers in the register file 107. At this time, the translation memory 201 in the processor 200,
The clock for operating the circuits such as the translation instruction decoder 202 and the transfer circuit 203 is the super scalar processor 10
It is realistic to use the same clock as that for operating 0. Therefore, although the high-speed operation as described in the first embodiment cannot be realized, the translation instruction can be executed without using the instruction scheduler 104 as a result of using the translation instruction. .

(2) In the above embodiment, the destination of the translated instruction shown in FIG.
As shown in FIG. 13, information of only the transfer source is recorded in the translation instruction memory 201. This is because, as shown in FIG. 14, the time from the fetching of the translation instruction to the execution of the instruction is reduced by associating the data in the translation instruction memory with the associated registers and arithmetic units. However, in this method, the efficiency of using the translation instruction memory 201 is not always high, so that the translation instruction form shown in FIG. 11 can be stored in the translation instruction memory 201 as it is. However, in this method, the decoding related to the transfer destination is performed at the time of reading the translated instruction, so that the processing time until the instruction execution, which is the main feature of the present invention, is slightly sacrificed.

(3) Although a semiconductor memory such as an SRAM or a DRAM is assumed as the translation instruction memory, for example, as shown in FIG. 21, a form in which the translation instruction memory is stored in an external storage device 201A such as a hard disk is also possible. The translation instruction fetch circuit 201B stores the translation instruction in the same manner as the readout circuit 213 (in this modification, the external storage device 2
01A), the source information of the translation instruction is read. The register file 107A has the same logic as the register file 107,
The register file is the same on both physical sides. However, in this case, unlike the above-described embodiment, the translation instruction is not executed simultaneously with the operation of the scalar processor 100, but is executed separately on the processor 200.

[0069]

According to the present invention, the schedule processing is performed on the instructions of the program for sequential execution, the instructions are executed in parallel, and the result of the schedule processing is stored in the memory. Is executed, there is no need to execute the schedule process again, and the program can be executed again at a higher speed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an information processing apparatus according to the present invention.

FIG. 2 is a flowchart of instruction execution in the apparatus of FIG. 1;

FIG. 3 is a scalar processor 1 used in the apparatus of FIG.
FIG.

FIG. 4 is a diagram showing a format of an instruction used in the apparatus shown in FIG. 1;

FIG. 5 is a view showing an example of a program executed by the apparatus shown in FIG. 1;

FIG. 6 is a diagram showing a graph representation of the program of FIG. 5;

FIG. 7 is a view showing a graph representation representing data transfer of the program of FIG. 5;

FIG. 8 is a schematic block diagram of an instruction translation circuit used in the apparatus of FIG. 1;

FIG. 9 is a schematic block diagram of a translation memory used in the apparatus of FIG. 1;

FIG. 10 is a circuit diagram of a plurality of types of memory cells and a plurality of control circuits used in the device of FIG. 9;

FIG. 11 is a diagram showing a format of a translation instruction generated by the device of FIG. 8;

FIG. 12 is a diagram showing an equivalent scoreboard that holds the same content as the content held in two scoreboards included in the apparatus of FIG. 8;

FIG. 13 is a view showing a format of a translation instruction stored in the apparatus of FIG. 9;

FIG. 14 is a schematic configuration diagram of a translation instruction decoder and a transfer circuit included in the device of FIG. 1;

FIG. 15 is a block diagram of a command waiting unit used in the apparatus of FIG. 14;

16 is a circuit diagram and a time chart of the device in FIG.

FIG. 17 is a diagram showing a first execution example of a translation instruction in the device of FIG. 1;

FIG. 18 is a view showing a second execution example of a translation instruction in the apparatus of FIG. 1;

FIG. 19 is a diagram showing a third execution example of a translation instruction in the device of FIG. 1;

FIG. 20 is a view showing a fourth execution example of a translation instruction in the apparatus of FIG. 1;

FIG. 21 is a schematic block diagram of another information processing apparatus according to the present invention.

Claims (9)

[Claims] A plurality of first type physical resources including a plurality of first type arithmetic units and a plurality of first type registers; and a plurality of first type instructions included in a program to be executed. Selecting a plurality of first-type instructions that can be executed in parallel, and assigning a plurality of first-type physical resources to be used for execution of each first-type instruction to the selected plurality of first-type instructions Of the plurality of first-type instructions selected to execute the first-type instructions in parallel using physical resources allocated to each of the plurality of first-type instructions. An instruction scheduler for controlling execution; and each time a plurality of first type instructions are executed in parallel by the instruction scheduler, the instruction scheduler executes each of the plurality of first type instructions executed in parallel by the instruction scheduler. A small resource that can identify multiple allocated physical resources A memory for storing at least one second-type instruction; a plurality of second-type physical resources including a plurality of second-type operation units and a plurality of second-type registers; An instruction for executing at least one second-type instruction stored in the memory corresponding to the plurality of first-type instructions, instead of the plurality of first-type instructions included in the program; An execution circuit, wherein the instruction execution circuit is identifiable from the one second type instruction assigned to each of the plurality of first type instructions corresponding to the second type instruction. An information processing apparatus that executes a second type instruction using a plurality of second type physical resources corresponding to various plurality of physical resources. 2. The plurality of second-type arithmetic units are provided separately from the plurality of first-type arithmetic units, and the plurality of second-type registers are connected to the plurality of first-type registers. The information processing apparatus according to claim 1, wherein the information processing apparatus is provided separately. 3. The plurality of first-type arithmetic units are used as the plurality of second-type arithmetic units, and the plurality of first-type registers are used as the plurality of second-type registers. Item 10. The information processing apparatus according to Item 1. 4. The plurality of second type operation units include the same operation unit as the plurality of first type operation units, and the number of the plurality of second type registers is equal to the plurality of first type operation units. The information processing apparatus according to claim 1, wherein the number of registers is equal to the number of registers. 5. The plurality of second type arithmetic units include a different number of arithmetic units from the plurality of first type arithmetic units, and the number of the plurality of second type registers is equal to the plurality of second type arithmetic units. 2. The information processing apparatus according to claim 1, wherein the number of registers is different from the number of one type of register. 6. A plurality of physical resources including a plurality of arithmetic units and a plurality of registers, and a plurality of second-type instructions respectively corresponding to a set of a plurality of first-type instructions executable in parallel. A memory, and an instruction execution circuit for sequentially executing a plurality of second type instructions stored in the translation memory, wherein each of the plurality of second type instructions corresponds to a corresponding one of the plurality of second type instructions. A plurality of physical resources used to execute an operation required by the first type of instruction are stored in the memory so as to be identifiable, and the instruction execution circuit comprises a plurality of first resources corresponding to each second type of instruction. The second instruction assigned to each of the
An information processing apparatus that executes a second type of instruction using a plurality of physical resources that can be identified from the type of instruction. 7. An executable state by determining a plurality of operation units, a plurality of registers, an operation unit and a register used by an instruction, and monitoring update of data in the register which is an input of instruction execution. An instruction scheduler for sequentially inputting the instructions into the arithmetic unit, a memory for storing an instruction word storage address of the instruction input to the arithmetic unit, an arithmetic unit to be used, and register information, which are already stored in the memory An information processing apparatus comprising: an instruction execution circuit that executes an instruction based on information about an arithmetic unit to be used and a register stored in the memory when executing an instruction at an instruction word storage address again. 8. A plurality of operation units, a plurality of registers, an operation unit and a register used by an instruction are determined, data in the register as an input of instruction execution is updated, and a register in the register as an input of instruction execution is updated. A transfer circuit that determines a transfer path from the arithmetic unit to the register or from the arithmetic unit to the arithmetic unit by monitoring an arithmetic unit that generates data, and an instruction of the instruction input to the arithmetic unit; A memory for storing a word storage address and transfer path information of data necessary for executing the instruction, and when executing again the instruction of the instruction word storage address already stored in the memory, the transfer circuit includes: An information processing apparatus having a circuit for executing a command by switching a data transfer path between a computing unit and a register based on transfer path information stored in the memory. 9. A plurality of arithmetic units, a plurality of registers, and a plurality of intersections between output lines and input lines enabling data transfer between the plurality of arithmetic units and the plurality of registers. A plurality of instruction waiting circuits for waiting for an instruction waiting to be executed, an arithmetic unit for generating data required for instruction execution, or a register holding data necessary for instruction execution, and an arithmetic unit for executing arithmetic An instruction waiting to be executed having the identification information as the data transfer information is provided at the intersection of the input / output lines of a computing unit or a register which requires data transfer to execute the instruction among the plurality of instruction standby circuits. And a circuit for inputting the instruction into one instruction standby circuit.