JPH07182168A - Arithmetic unit and its control method - Google Patents

Abstract

PURPOSE:To attain the sharing of a function executing device among the instruction flows by providing a constitution where a resources allocation controller permits an instruction decoding device which issues an instruction next to use the function executing device based on the present instruction executing state. CONSTITUTION:An instruction acquiring device 11 takes the instructions out of a storage, etc., in an arithmetic unit which simultaneously processes the information to plural instruction flows. An instruction decoding device 12 decodes the instruction acquired from the device 11 and starts the processing to a necessary function executing device 13. The device 13 carries out a necessary function by an instruction. Then a resources allocating device 14 checks the present instruction executing state by means of the devices 11, 12 and 13 and permits the device 12 which issues an instruction next to use the device 13. Thus the application factor of the device 13 is improved in a practical range, and the device 13 can be shared among plural instruction flows (programs).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor used in an information processing device, and more particularly to a plurality of instruction streams (programs).
The present invention relates to a high-performance processor capable of processing in parallel.

[0002]

2. Description of the Related Art As a technique for accelerating a processor, a method of preparing a plurality of function execution devices and issuing instructions to a plurality of function execution devices at the same time by utilizing instruction parallelism to improve the processing speed Has been put to practical use. When this method is used, it is ideally possible to process instructions at a rate higher than the operating clock frequency. In order to perform such processing, in addition to adding a function execution device, a logic circuit for ensuring the validity of the result of instruction execution is required. This method is generally called the superscalar method, and was announced by Digital Equipement Corporation of the United States.
pha architecture and Power from IBM, Motorola, Apple
Architecture, Hewlett-Packard PA-RISC architecture, etc.

However, there is a limit to the utilization of parallelism on an instruction-by-instruction basis, and the performance improvement in this method is actually suppressed to 3 to 4 times even if the number of function execution devices is increased infinitely. It is said. The factors that limit the parallelism are the dependency between instructions and the disturbance of the instruction flow due to branching. Various methods have been proposed to solve these restrictions, but the performance improvement is limited to about 40 times due to the extreme complexity of hardware. Such a limit is
Paper published in 1992 by Monica S. Lam et al. (Monica SL
am and Robert P. Wilson, "Limits of Control Flow on
Parallelsim ", IThe 19th International Symposium on
Computer Architecture, IEEE Computer Society Press,
1992, pp.46-57).

On the other hand, there has been proposed a method of increasing the utilization efficiency of the function execution device by executing instructions in a plurality of instruction streams in parallel, rather than the parallelism of instruction units, and improving the processing speed. In this method, since there is no dependency between the instruction streams, it is easier to improve the performance than the instruction unit parallelism.

This system was published in 1993 by Hirata et al. (Hirata Hirata, Kozo Kimura, Satoshi Nagamine, Sadaji Nishizawa, Noriyuki Sagishima, "Element Processors Using Multiple Threads and Multiple Instructions, Architecture", Information Processing Society of Japan Magazine 1993 Vol34
No.4 pp.595-605). Figure 2
Shows a schematic configuration of this embodiment. Hereinafter, this embodiment will be described as an embodiment of the prior art.

In FIG. 2, 11 is an instruction acquisition device, and 12
Is an instruction decoding device, 13 is a function execution device, and 21 is a dependency analysis device between instructions. Further, 22 is a function execution device 13
Is an instruction arbitration device that schedules. The instruction decoding device 12 issues an instruction when the instruction arbitration device 22 is in a state in which the instruction can be accepted and when the instruction dependent device 21 receives an instruction that the instruction can be issued. The instruction issued from each instruction decoding device 12 is assigned to the required function execution device 13 by the instruction arbitration device 22 and is actually executed. The instruction arbitration device 22 enables the function execution device 13 to share the commands among them and improve the utilization efficiency. Further, by distributing the instruction arbitration device 22 for each function execution device 13, the instruction arbitration device can be simplified.

[0007]

The above-mentioned conventional function execution device sharing mechanism has the following problems. First, by adding instruction arbitration processing to the instruction execution pipeline, the latency of instruction execution increases, and as a result, the processing speed decreases when executing instructions that do not conform to the pipeline structure such as branch instructions and exception processing. To bring. Secondly, the instruction arbitration device has a complicated structure because the number of instructions to be arbitrated increases and the number of instruction decoding devices increases, and the arbitration logic also becomes complicated. Be a factor that can be prevented. Thirdly, when the instruction flow increases and the number of instruction decoding devices increases, the connection between the function execution device and the temporary storage device (register) necessary for function execution and the buffer storage device (cache memory) is established. Since it has to be realized by a complicated switch, the delay is increased and it becomes a factor to prevent the improvement of the operating frequency. These problems limit the instruction streams and operating frequencies that can be concurrently executed by the above mechanism.

An object of the present invention is to increase the utilization rate of a function execution device within a practical range without increasing the number of instruction execution latency at a high operating frequency, and to share the function execution device between instruction streams. It is to provide the control method of.

[0009]

In order to solve the above problems, in the present invention, a processor in which a plurality of instruction streams operate in parallel, that is, a plurality of instruction acquisition devices, a plurality of instruction decoding devices, and a plurality of functions. A resource allocation control device is added to a processor having an execution device, a plurality of temporary storage devices (registers), and a buffer device (cache).

The resource allocation control device is a mechanism for determining a usable function execution device for each clock of an instruction stream from the instruction execution information and internal setting information from each device. The instruction decoding device can issue an instruction to the function execution device that can execute the instruction based on the function execution device use permission information determined by the resource allocation control device. That is, the resource allocation control device determines the availability of all the function execution devices in the processor for each instruction stream.
The instruction decoding device determines, from among the available function execution devices, a function execution device that executes an instruction according to the program counter of the instruction stream, and issues the instruction. Further, the instruction issue information is notified to the resource allocation control device to select a temporary storage device or a buffer storage device for storing the result of function execution by the function execution device.

There is one resource allocation control device in the system,
Alternatively, the number of function execution devices is prepared and distributed to each function execution device. In addition, each instruction decoding device issues one instruction at a time, or sets the number of simultaneous instruction transmissions from the instruction acquisition device to the instruction decoding device to a plurality of instructions, and determines the number of instructions to be executed according to the available function execution device. Using sequential issue and superscalar technology, multiple commands are issued simultaneously according to available function execution devices.

Further, the resource allocation device allocates resources equally to each instruction stream, or checks the utilization status of the function execution device for each instruction stream in advance by software, such as a compiler, and informs the resource allocation control device. By this, the allocation for each instruction stream of the function execution device in the resource allocation control device is determined. Alternatively, the resource allocation control device monitors the command issuance information from the instruction decoding device to the function execution device for each instruction stream, thereby dynamically detecting the instruction issuing tendency of the instruction stream and allocating resources accordingly. It is performed by the allocation control device.

Between the temporary storage device, the buffer storage device and the function execution device, a logic circuit is implemented so that the instruction flow can use all the function execution devices, or the function execution device that each instruction flow can use is limited. It depends on the design of the processor whether or not the method of simplifying the connection is adopted, and the means for simplifying the logic of the resource allocation device can be selected by further distributing the resource allocation control device accordingly.

[0014]

In the processor according to the first aspect of the present invention, the instruction decoding device issues an instruction to the function execution device according to the permission of the resource allocation control device. Since the use permission information of the function execution unit is obtained at the same time as entering the instruction decoding unit and the function execution unit to be used is determined when the instruction is issued, the pipeline stage to arbitrate the function execution unit after issuing the instruction is increased. It is possible to realize sharing between the instruction streams of the function execution device without using the function execution device and efficiently use the function execution device. Further, the number of function execution units, which are rarely used, is set to one in the processor or less than the simultaneous operation instruction stream, so that the resources in the chip can be effectively used. This resource allocation control device determines an available function execution device for each clock of an instruction stream based on the information from each device and internal information. Since the resource allocation is determined from the information up to the previous instruction execution, the utilization efficiency of the function execution unit cannot be expected as much as the conventional method, but the clock frequency is reduced by the simplification of the structure and the reduction of the instruction execution latency due to the shortened pipeline The processing speed can be improved. Further, in the invention described in claim 2, the resource allocation control devices are distributed to simplify the structure of each resource allocation control device.

In order to increase the utilization rate of the function executing device and improve the efficiency, in the invention according to claim 3, the number of simultaneous instruction transmissions from the instruction acquiring device to the instruction decoding device is made plural, and the usable function executing device can be used. The commands are issued out of order according to In the invention according to claim 4, the number of simultaneous instruction transmissions from the instruction acquisition device to the instruction decoding device is made plural.
Furthermore, the superscalar technology is used to simultaneously issue instructions according to the available function execution devices. The use of these techniques makes it possible to efficiently use a plurality of function execution units from a single instruction stream, and is particularly effective when the number of function execution units is larger than the number of simultaneously operating instruction streams. .

According to the fifth aspect of the invention, the utilization status of the function execution device for each instruction stream is checked in advance by software such as a compiler. By transmitting this information to the resource allocation control device, the allocation for each instruction stream of the function execution device in the resource allocation control device is optimized, efficient execution is performed, and the processing speed is increased. Also,
In the invention according to claim 6, the resource allocation control device dynamically monitors the instruction issuing information from the instruction decoding device to the function executing device for each instruction stream, thereby dynamically detecting the instruction issuing tendency of the instruction stream, The resource allocation control device performs the resource allocation according to it, so that efficient execution is performed and the processing speed is increased. By combining these, it becomes possible to allocate resources according to the code and preferentially allocate the function execution device to the code whose execution is delayed.

In the function execution device, when an event that must be interrupted occurs, for example, when a necessary data cannot be obtained due to a cache miss, the hardware takes necessary measures. Until it is done, the function execution device cannot be used. In the invention according to claim 7, when such an event occurs, the data necessary for restarting execution is saved in the storage device attached to the function execution device,
By making the function execution device usable for execution of other instructions, the utilization rate of the function execution device is improved.

When a plurality of function execution units are shared by a plurality of instructions, the instruction flow increases, and when the number of instruction decoding units increases, the function execution units and temporary storage required for function execution are stored. Since the connection between the device (register) and the buffer storage device (cache memory) needs to be realized by a complicated switch, there arises a problem that the number of necessary logic circuits increases. According to the invention described in claim 8, the temporary memory device is not realized by implementing a logic circuit so that the instruction stream can use all the function execution apparatuses, but by limiting the function execution apparatus that can be used by each instruction stream. , To simplify the connection between the buffer storage device and the function execution device.

Furthermore, by restricting the function execution devices that can use the instruction stream, the resource allocation control devices are distributed and the logic is simplified.

The present invention will be described in more detail below with reference to the drawings, but the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention described in claim 1 will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a processor to which a control system according to the present invention is applied. The processor shown in FIG. 1 has two instruction acquisition devices 1
1, 2 instruction decoding devices 12 and 3 function execution devices 1
3. It is assumed that the three function execution units 13 each of which is composed of the resource allocation control unit 14 and shares two instruction streams are simultaneously executed. The function execution unit 13 may have the same function or different functions without affecting the main feature of the present invention, but here, for convenience, an integer arithmetic unit, a floating point unit, and a load / store unit are used. In this case, the aim is not to increase the processing speed but to use the computing unit efficiently. In addition to this, when a processor performs an operation, a temporary storage device (register), a buffer storage device (cache memory), etc. exist, but they are not directly related to the inventions of claims 1 to 7. Therefore, it is omitted. Also, two instruction streams that are executed simultaneously are referred to as instruction stream A and instruction stream B.

From the instruction acquisition device 11 to the instruction decoding device 12
Is sent to the function execution unit 13. The instruction decoding unit 12 sends the instruction decoding result to the function execution unit 13. From the resource allocation control device 14 to the instruction decoding device 12, each function execution device 1
The availability information of 3 is sent. Further, the execution state information is sent from the instruction acquisition device 11, the instruction decoding device 12, and the function execution device 13 to the resource allocation control device 14.

The instruction acquisition device 11 acquires an instruction from the main storage device (main memory) or the buffer device (cache memory) according to the values of the program counters of the instruction streams A and B. Next, the instruction decoding device 12 receives the instruction content from the instruction acquisition device 11, and the availability information of each function execution device 13 from the resource allocation control device 14, for example, the instruction stream A is an integer arithmetic unit and a floating point. The decimal point unit is available and instruction stream B receives the information that the load store unit is available. If the instruction decoding result of the instruction stream A is an integer operation or a floating point operation, the instruction is unconditionally issued to the integer operation unit or the floating point operation unit. If it is a load store instruction,
An interlock occurs in the instruction decoding device 12, and no instruction is issued until the next cycle. In the case of command flow B, on the contrary,
If the instruction decoding result is an integer operation or a floating point operation, interlock is performed, and if it is a load / store instruction, the instruction is issued. In the next cycle, when the instruction is issued in the previous cycle, the instruction decoding device 12 causes the instruction acquisition device 11
Receive new orders from. When no instruction is issued in the previous cycle, no new instruction is received, and only the availability information of the function execution device 13 is received. For example,
In this cycle, the instruction stream A can use the load / store unit, and the instruction stream B can use the integer arithmetic unit and the floating point unit. Therefore, similarly to the previous cycle, the instruction is determined by comparing the instruction with the usable function execution device 13. The resource allocation control device 14 has a mechanism such that resources are allocated evenly among instruction streams. This is shown in display 1. Further, it receives the execution state information from each of the other devices and determines the availability of the next function execution device 13 based on the information.

[0024]

[Table 1]

As a result, the plurality of function executing devices 1
3 can be shared among a plurality of instruction streams, and the function execution device 13 can be effectively used.

Next, the invention described in claim 2 will be described with reference to the drawings. FIG. 3 shows an embodiment of a processor to which the control method according to the present invention is applied. The processor shown in FIG. 3 is composed of two instruction acquisition devices 11, two instruction decoding devices 12, three function execution devices 13, and three distributed resource allocation control devices 31, and shares two instruction streams. It is assumed that the two function execution devices 13 simultaneously execute the functions. The feature of this embodiment resides in that the resource allocation control device 14 in the processor according to claim 1 is distributed for each function execution device 13. As a result, it is possible to simplify the resource allocation control device.

Next, the invention described in claim 3 will be described with reference to the drawings. FIG. 4 shows an embodiment of a processor to which the control method according to the present invention is applied. The processor shown in FIG. 4 has two instruction acquisition devices / instruction queues 41, 2.
It is assumed that three instruction execution units 12 and three function execution units 13 and a resource allocation control unit 14 are simultaneously executed by three function execution units 13 that share two instruction streams. The present embodiment extends the instruction acquisition device 11 of the processor according to claim 1 by adding a queue so as to hold a plurality of instructions, and further, the instruction decoding device 12 receives a plurality of instructions from the instruction acquisition device. If there is no dependency before or after the instruction, or if the dependency can be resolved, and if the first permission instruction of the function execution device obtained from the resource allocation control device 14 is unexecutable, 2 It is characterized in that it is extended to execute out-of-order execution when the second and subsequent instructions are in an executable state.

Similarly to the invention described in claim 1, the function execution unit 13 is an integer arithmetic unit, a floating point unit, and a load store unit, respectively. In addition, two instruction streams that are simultaneously executed are an instruction stream A and an instruction stream B,
The instruction decoding device 12 receives two instructions at the same time by the instruction acquisition device /
It will be received from the instruction queue 41. The instruction acquisition device / instruction queue 41 acquires an instruction from the main storage device (main memory) or the buffer device (cache memory) according to the values of the program counters of the instruction flow A and the instruction flow B. Here, since there is an instruction queue, it is assumed that a plurality of instructions are acquired. Next, the instruction decoding device 12
The two command contents are received from the command acquisition device 11, and the individual function execution devices 1 are received from the resource allocation control device 14.
3, the instruction stream A receives the information that the integer arithmetic unit and the floating point unit can be used, and the instruction stream B can use the load store unit. Command decoding can be performed for multiple commands received,
In addition, the dependency between instructions can be examined. If the first instruction is an integer operation or a floating point operation result of the instruction decoding of the instruction stream A, it is unconditionally issued to the integer operation unit or the floating point operation unit. If the first instruction is a load store instruction and the second instruction is an integer operation instruction or a floating point operation instruction, and there is no dependency between the first and second instructions, the second instruction is an integer operation. Issued to a unit or floating point arithmetic unit. If this condition is not satisfied, an interlock occurs in the instruction decoding device 12, and no instruction is issued until the next cycle. The instruction stream B is the same, and the operation in the next cycle is
The same is repeated.

In a processor embodiment as claimed in claim 1,
When the first instruction cannot be executed in the function execution unit for which the use is permitted, the interlock is unconditionally performed. However, in the processor example in this section, the out-of-order issuance of the instruction is allowed. The occurrence probability is reduced, and the throughput and the program execution processing speed are improved.

Next, the invention according to claim 4 will be described with reference to the drawings. FIG. 5 shows an embodiment of a processor to which the control method according to the present invention is applied. The processor shown in FIG. 5 has two instruction acquisition units / instruction queues 41, 2.
It is assumed that three instruction execution units 12 and three function execution units 13 and a resource allocation control unit 14 are simultaneously executed by three function execution units 13 that share two instruction streams. The present embodiment extends the instruction acquisition device 11 of the processor according to claim 1 by adding a queue so as to hold a plurality of instructions, and further, the instruction decoding device 12 receives a plurality of instructions from the instruction acquisition device 11 and depends on them. When the relationship is checked, there is no dependency before and after the instruction, or when the dependency can be resolved, and when the usage permission status obtained from the resource allocation control device 14 enables the plurality of function execution devices 13 to be used. It is characterized in that the superscalar technology is used to extend the simultaneous issue of instructions to a plurality of function execution units 13.

Similarly to the invention described in claim 1, the function execution unit 13 is an integer operation unit, a floating point unit, and a load store unit, respectively. In addition, two instruction streams that are simultaneously executed are an instruction stream A and an instruction stream B,
The instruction decoding device 12 receives two instructions at the same time by the instruction acquisition device /
It will be received from the instruction queue 41. The instruction acquisition device / instruction queue 41 acquires an instruction from the main storage device (main memory) or the buffer device (cache memory) according to the values of the program counters of the instruction streams A and B.
Here, since there is an instruction queue, it is assumed that a plurality of instructions are acquired. Next, the instruction decoding device 12 receives two instruction contents from the instruction acquisition device 11, and the availability information of each function execution device 13 from the resource allocation control device 14, for example, the instruction stream A is an integer arithmetic unit. And a floating point unit is available and instruction stream B receives information that a load store unit is available. Instruction decoding is performed on a plurality of received instructions, and the dependency relation between the instructions is also checked. If the first instruction is an integer operation in the instruction decoding result of the instruction stream A, the second instruction is a floating point operation instruction, and 1
If there is no dependency between the second and second instructions, the first instruction is issued to the integer arithmetic unit and the second instruction is issued to the floating point arithmetic unit. If the first is a floating point operation and the second is an integer operation and there is no dependency between instructions, the first instruction is issued to the floating point operation unit and the second instruction is issued to the integer operation unit. When this condition is not satisfied, only a single instruction is issued or the interlock state is set, as in the first aspect. This operation is the same for the instruction stream B, and the operation in the next cycle is similarly repeated.

In a processor embodiment as claimed in claim 1,
Even when the resource allocation control device 14 gives permission to use the plurality of function execution devices 13, only one of them is used. However, in the processor embodiment in this section, it is possible to issue instructions simultaneously by using superscalar technology. Since the instruction decoding device 12 is expanded, throughput and program execution processing speed are improved. In particular, the function execution devices 13 that are frequently used are provided in a number larger than the instruction stream to be processed in parallel, and the function execution devices 13 that are rarely used are provided in the processor in a very small number, thereby performing the functions It is possible to improve the utilization factor of the device and further improve the throughput. Further, it is possible to apply the inventions of claims 3 and 4 at the same time to further improve the performance.

Next, the invention described in claim 5 will be described with reference to the drawings. FIG. 6 shows an embodiment of a processor to which the control system according to the present invention is applied. The processor shown in FIG. 6 is composed of two instruction acquisition devices 11, two instruction decoding devices 12, three function execution devices 13, and a software priority instruction type resource allocation control device 51, and shares two instruction streams. It is assumed that they are simultaneously executed by the three function execution devices 13. In the present embodiment, a function is added to the resource allocation control device 14 of the processor according to claim 1 so as to allocate a function execution device 13 suitable for the property and priority of the instruction stream by software. It is characterized by having done. This priority control is realized by incorporating an instruction for priority control in the instruction stream.

Similarly to the invention described in claim 1, the function execution unit 13 is an integer arithmetic unit, a floating point unit, and a load store unit, respectively. Also, two instruction streams that are executed simultaneously are referred to as instruction stream A and instruction stream B. Here, in the instruction stream A, a resource allocation instruction that the compiler does not use the floating point unit is placed at the head of the instruction stream if the code does not perform floating point arithmetic. When this instruction is decoded, the resource allocation control device 51 is informed that the instruction stream A does not require the use of the floating point unit. After that,
In the resource allocation control device 51, the floating point unit is given only to the instruction stream B unless the setting is changed. However, if the floating-point operation instruction exists in the instruction stream under the condition that it is not assigned, the instruction decoding device 12
It is also possible to select a structure in which a resource allocation request can be made to the resource allocation control device 51. If the instruction stream B is a process having a high priority, system software such as an OS issues an instruction to the resource assignment control device 51 to preferentially allocate resources to the instruction stream B. In this case, in the instruction stream A and the instruction stream B, the resource allocation control device controls the instruction stream B so as to give a large amount of permission to use the function execution device 13.

By carrying out this extension, it becomes possible to perform resource allocation according to the nature of the instruction stream and the processing status, the utilization rate of the function execution device is improved, and the throughput and the program execution processing speed are improved. You can

Next, the invention according to claim 6 will be described with reference to the drawings. FIG. 7 shows an embodiment of a processor to which the control system according to the present invention is applied. The processor shown in FIG. 7 includes two instruction acquisition devices 11, two instruction decoding devices 12, three function execution devices 13, and a dynamic priority variable resource allocation control device 61, and shares two instruction streams. It is assumed that they are simultaneously executed by the three function execution devices 13. In this embodiment, the resource allocation control device 14 of the processor according to the first aspect is monitored by hardware to monitor the instruction execution status and the nature of the code, so that the allocation of the function execution device 13 is suitable for the instruction flow. It is characterized by

Similarly to the invention described in claim 1, the function execution unit 13 is an integer arithmetic unit, a floating point unit, and a load store unit, respectively. Also, two instruction streams that are executed simultaneously are referred to as instruction stream A and instruction stream B. At the initial stage of execution, the resource allocation management device 61 equally gives permission to use the function execution device 13 to the instruction stream A and the instruction stream B, in the same manner as the processor shown in the specific example of claim 1. Of the instruction stream A and the instruction stream B to the respective function execution devices 13 by monitoring the instruction issue rate and the interlock occurrence rate of each of the instruction streams A and B.
Assign as much as possible. For example, command flow A
Then, in the case of a code that mainly uses the floating point unit and mainly uses the integer arithmetic unit, the floating point unit uses the resource allocation control from the instruction decoding device 12 when the execution of the instruction actually occurs. By making an allocation request to device 61, a floating point unit will be allocated. On the other hand, if the instruction stream B is a code that mainly uses the load store unit and the floating point unit, the instruction flow B is controlled so that this unit is mainly assigned.

By performing this extension, it becomes possible to allocate resources according to the nature of the instruction stream and the processing status, the utilization rate of the function execution device is improved, and the throughput and the program execution processing speed are improved. Is possible. Further, the efficiency can be further improved by using the allocation priority control by the software according to the fifth aspect together.

Next, the invention according to claim 7 will be described with reference to the drawings. FIG. 8 shows an embodiment of a processor to which the control method according to the present invention is applied. The processor shown in FIG. 8 includes two instruction acquisition devices 11, two instruction decoding devices 12, three function execution devices 13, a resource allocation control device 14, and an execution information save storage device 71, and shares two instruction streams. It is assumed that the three function execution devices 13 are simultaneously executed. In the present embodiment, the execution information saving device 71 is provided to save the execution information and execute other instructions first for the function execution device 13 of each processor according to claim 1. Is added.

Similarly to the invention described in claim 1, the function execution unit 13 is an integer operation unit, a floating point unit, and a load store unit, respectively. Also, two instruction streams that are executed simultaneously are referred to as instruction stream A and instruction stream B. In the instruction stream A, the load instruction is the instruction issuing device 12
Issued to the load store unit from However, if the desired data does not exist in the buffer device (cache memory), the data is transferred from the main storage device with a large delay. Therefore, the instruction is interlocked in the load / store unit. When this happens,
In the case of the invention described in claim 1, the load / store unit cannot be used until the interlock can be avoided. In the invention of this section, when such a lock state occurs, the execution information is saved in the execution information saving storage device 71 so that the instruction stream B can be permitted to use the load / store unit. To do.

By performing this extension, even if an interlock occurs, the function execution device can be assigned to another instruction stream, the utilization rate of the function execution device is improved, and throughput and program execution are improved. It is possible to improve the processing speed.

Next, the invention described in claim 8 will be described with reference to the drawings. The present invention provides a temporary storage device (register) 81 or a buffer storage device for executing a function prepared for each instruction stream by limiting the function execution apparatus 13 that can be used for each instruction stream. , And the function execution device 13 is simplified in connection.

First, FIG. 9 shows an embodiment described in claim 1. Compared with FIG. 1, a temporary storage device (register) 87 is provided.
3 is different from that shown in FIG. 2 in that the number of simultaneous operation instructions is increased to 3 and the number of function execution units 13 is increased to 6. Next, FIG.
Reference numeral 0 is an embodiment of a processor to which the control method according to the present invention is applied. Compared with FIG. 9, the feature is that the resource allocation is limited. In FIG. 10, assuming that the three instruction streams are the instruction stream A, the instruction stream B, and the instruction stream C, the function execution device 81 and the function execution device 86 have only the instruction flow A and the instruction flow C, respectively.
The function execution unit 82 and the function execution unit 83 execute only the instruction stream A and the instruction stream B, and the function execution units 84 and 85 execute the instruction stream B and the instruction stream C only. Therefore, the connection between the instruction decoding device 12 and the function execution device 13 and the connection between the function execution device 13 and the temporary storage device 87 are simplified. In addition, the internal structure of the resource allocation control device 14 is also simplified by setting the restriction on the allocation. In addition, by limiting the use range of the function execution device 13 for each instruction stream between adjacent instructions, the number of intersections between the connections is reduced, which is advantageous in implementation.

The present invention is particularly effective in a processor having a plurality of function executing devices 13 having the same function. When the integration degree of the processor is improved and the number of simultaneous operation instructions in the processor and the function execution device 13 are increased, the limited allocation mechanism shown in this section enables the simplification of the implementation and the improvement of the operating frequency. It is possible to sufficiently compensate for the decrease in the utilization rate due to the allocation limitation of the function execution device. In addition, claim 3,
By combining the invention described in claim 4, it is possible to further improve the efficiency.

[0045]

According to the present invention, in an arithmetic unit for operating a plurality of instruction streams in parallel, the function executing unit, which is the center of the arithmetic operation, is shared between the instruction streams, so that the function executing unit can be effectively used. . Further, in the conventional example, since the function execution device is scheduled after the instruction is decoded, there is a problem that the instruction execution delay increases and the control becomes complicated. However, in the method of the present invention, it is used before the instruction is decoded. Since the available function execution device is given for each instruction stream, the use efficiency of the function execution device is slightly reduced, but the use efficiency decrease is more than compensated by the advantage that the control is simple and the operating frequency can be improved. Becomes Also,
It is possible to minimize the decrease in utilization efficiency by performing scheduling in software or hardware according to the nature of each instruction. Furthermore, when a plurality of instruction streams are simultaneously executed, the resource execution control device can be simplified by limiting the function execution devices that can be used in advance. From the above, the method of the arithmetic device for operating a plurality of instruction streams in parallel according to the present invention is very effective for high-speed operation of instructions and cost reduction.

[0046]

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a processor for illustrating a method of controlling a processor according to the present invention.

FIG. 2 is a configuration diagram of an embodiment of an inter-instruction flow sharing method of a conventional function execution device.

FIG. 3 is a configuration diagram of an embodiment using a distributed resource allocation control device.

FIG. 4 is a configuration diagram of an embodiment using an instruction decoding device that issues an out-of-order instruction.

FIG. 5 is a configuration diagram of an embodiment using an instruction decoding device that simultaneously issues instructions.

FIG. 6 is a configuration diagram of an embodiment using a software priority indicating resource allocation control device.

FIG. 7 is a configuration diagram of an embodiment using a dynamic priority variable resource allocation control device.

FIG. 8 is a configuration diagram of an embodiment in which an execution information saving device is added to the function executing device.

9 is a configuration diagram of an embodiment equivalent to FIG. 1, in which a temporary storage device (register) is newly represented.

FIG. 10 is a configuration diagram of an embodiment in which usable function execution devices are limited for each instruction stream.

[Explanation of symbols]

 11 instruction acquisition device 12 instruction decoding device 13 function execution device 14 resource allocation control device 21 instruction dependence analysis device 22 instruction arbitration device 31 distributed resource allocation control device 41 instruction acquisition device / instruction queue 51 software priority directed resource allocation control device 61 dynamic priority variable type resource allocation control device 71 execution information save storage device 81-86 function execution device 87 temporary storage device (register)

Claims (8)

[Claims] 1. In an arithmetic device having a plurality of instruction acquisition devices, a plurality of instruction decoding devices, and a plurality of function execution devices, and executing information processing simultaneously for a plurality of instruction streams, the instruction acquisition device is a storage device or the like. The instruction fetching device fetches the instruction, the instruction decoding device decodes the instruction obtained from the instruction acquiring device and activates the processing to the required function executing device, the function executing device executes the required function according to the instruction, and the resource allocation control device, A method for controlling an arithmetic unit, characterized in that the present instruction execution status is checked from an instruction acquisition unit, an instruction decoding unit, and a function execution unit, and the instruction decoding unit that issues an instruction next is given permission to use each function execution unit. 2. The resource allocation control device according to claim 1,
The control method for an arithmetic unit according to claim 1, wherein the function execution units are distributed. 3. The instruction allocation apparatus according to claim 1, wherein there is no dependency before or after the instruction with respect to the available function execution apparatus, or the dependency can be resolved, and the resource allocation control apparatus. When the use permission status of the function execution device obtained from step 1 is that the first instruction cannot be executed and the second and subsequent instructions are in the executable state, the function execution device is expanded to execute the instructions out of order. The method for controlling the arithmetic unit according to claim 1. 4. The instruction decoding apparatus according to claim 1, wherein there is no dependency before or after an instruction with respect to an available function execution apparatus, or the dependency can be resolved, and a resource allocation control apparatus. The control method of the arithmetic unit according to claim 1, wherein when the use permission of a plurality of function execution units is obtained from the above, it is expanded so as to issue instructions simultaneously. 5. The resource allocation control device according to claim 1, wherein the software permits the resource allocation control device to give priority to the permission of use of the function execution device for each instruction stream, and the function execution device is not used in the instruction stream. 2. The method for controlling an arithmetic unit according to claim 1, wherein the permission of use of the instruction is prohibited and the execution of each instruction stream is optimized. 6. The resource allocation control device according to claim 1, wherein information on instruction issuance from an instruction decoding device to a function execution device is checked, and resource allocation for each subsequent instruction stream is optimized based on that information. The control method of the arithmetic unit according to claim 1, wherein 7. The function execution device in the arithmetic unit according to claim 1, when a storage device for saving one or more pieces of execution information is added, and an event of interrupting execution occurs,
The function execution device in which the event of interrupting the execution occurs is used for information processing by another instruction by saving the processing information in the storage device and transmitting the saving information to the resource allocation control device. 1. A method for controlling the arithmetic unit according to 1. 8. An arithmetic unit having a plurality of instruction acquisition units, a plurality of instruction decoding units, and a plurality of function execution units, which is used for each instruction stream in an arithmetic unit which simultaneously executes information processing for a plurality of instruction streams. By setting a limit on the function execution device capable of executing, a temporary storage device and a buffer storage device for function execution prepared for each instruction stream, coupling between the function execution device, and the function execution device and instruction decoding An arithmetic unit characterized by simplifying the connection with the unit.