JPS60263238A - Information processor - Google Patents

Abstract

PURPOSE:To execute efficiently the multiprocessing of plural processes by providing plural high-speed instruction buffers, controlling an execution waiting queue independently of an instruction executing part, transferring an instruction set to the high-speed instruction buffer prior to an execution of the process, and executing it. CONSTITUTION:An instruction executing part 1 can execute immediately a process to a buffer having a busy display F in a high-speed buffer memory 3, and executes it by reading it out of the buffer 3. The read-out instruction is inputted to an instruction register 20 and decoded, the address of a program is given, and each instructing operation is executed by controlling an arithmetic unit 24, a register 23, etc. by a program read out of a control memory 22. When an instruction set is being executed, in case an access has been executed to an instruction which is not in a high-speed prefetch buffer, it is detected by the instruction executing part 1, and the executing process is switched. That is to say, the pre-executing process is halted, information which has displayed an executing state required for a restart is saved to a process control book 14, and re-registered to an execution waiting queue 3 as a halted process.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device, and more specifically, in order to perform multiprocessing of a plurality of processes, a process-compatible device is provided between the main memory and the processor (instruction execution unit). The present invention relates to an information processing device equipped with a high-speed buffer.

[Prior art]

Conventionally, in a processing device with a high-speed buffer, when executing a program stored in the main memory, the program is first uploaded to the high-speed buffer memory and executed, thereby matching the element speeds of the processor and the high-speed buffer memory. The speed of command execution was increased.

FIG. 2 is a diagram showing a conventional processing device having a high-speed buffer memory. In FIG. 2, reference numeral 7 denotes a processor, and an instruction execution section 8 consisting of an arithmetic circuit, a group of registers, etc. It is composed of a high-speed buffer memory 9.

The processor 7 is connected to a main memory 6 that stores programs and data via an external bus 2 consisting of an address bus, a data bus, and the like.

When executing a program, in a processing device that does not have a high-speed buffer, the instruction execution unit fetches an instruction from the main memory and executes the instruction, but in a processing device that has a high-speed buffer as shown in Figure 2, the instruction execution unit 8 is high speed buffer memory 9
Fetch the instruction from and execute the instruction. That is, the instruction execution unit 8 reads the program in the main memory 6 entered at the time of start into the high-speed buffer memory 9 by the size of the high-speed buffer memory 9, and sequentially executes the instructions. Instructions are executed in this way, but a branch condition such as a jump instruction is encountered during instruction execution.

If the branch destination is a program in the main memory 6, the instruction is read from the branch destination into the high-speed buffer memory 9 and executed.

(Conventional problems) Conventional processing devices with this kind of high-speed buffer memory have
When executing a single-processing program with few branch conditions, the instruction execution speed can be increased. However, in multiprocessing where multiple processes are handled and the processes are frequently switched (for example, switching processing at a switch that receives processing requests from many telephones), the process switching corresponds to a branch condition, and therefore the instruction This has the disadvantage that the execution speed does not increase and the effect of providing a high-speed buffer memory cannot be obtained.

[Purpose of the invention]

An object of the present invention is to provide an information processing device that efficiently processes multiple processing of a plurality of processes.

The present invention includes a plurality of high-speed instruction buffers, controls a pending queue independently of an instruction execution unit that executes a process, and transfers an instruction set to the high-speed instruction buffer and executes it prior to execution of a process. Achieve the above objectives.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the invention. In Figure 1, 1
2 indicates an instruction execution unit, and 2 indicates a high-speed buffer memory for processes, which are connected by an external bus 2. Reference numeral 4 indicates a high-speed buffer memory control unit that controls the execution queue of processes, 6 a main memory, and 5 an external bus. The high-speed buffer memory control unit 4 controls a queue of processes waiting to be executed, and transfers the instruction set of the process stored in the main memory 6 to the high-speed buffer memory 3.

FIG. 3 shows the configuration of the high-speed buffer memory 3.

The high-speed buffer memory 3 consists of an n-sided buffer and an indication of whether the buffer is empty, and the instruction set of one process in a waiting state is transferred from the main memory to the high-speed buffer memory 3.
It is transferred to a buffer and made executable. At the same time, the blockage display is made to indicate blockage.

In multiprocessing, execution of objects (processes) that are processed in parallel under independent control proceeds using process entities. For example, in multiprocessing such as switching processing, a plurality of calls are processed in parallel under independent control, so a process entity is created each time a call occurs, and disappears when the call is processed. As shown at 14 in FIG. 5, the process entity consists of a process control book (PCB) 15 that manages the execution and status of the process, and a work area I6 that stores local data used during execution in a stacked manner. As shown in the figure, the PCB 15 has link information, a process status display, a save information area when a process is interrupted, work area information regarding a work area, and the like. The plurality of processes are executed in multiple ways based on the information of the PCB that each process has.

In order to multi-process multiple processes without inconsistency, synchronization and exclusion functions between processes are required, and running processes may be interrupted or stopped. state 2), waiting for execution (state 3)
There are three states, and the state transitions shown in FIG. 4 are performed. In the two states of stopping and waiting for execution, processes are managed by queue control. The generated process is first registered in the execution queue, and the execution of the process in state 1 ends (
(extinction) or transition to state 2 or 3 to move to state l.

The execution queue has a chain structure as shown in FIG. P-CB1 corresponding to processes waiting to be executed
5 has a pointer pointing to the PCB of the next connected process as link information for other processes waiting to be executed. Therefore, the processes waiting to be executed can be known in advance by following the links on the PCB, and FIG. 5 shows how a plurality of processes are queued for the shared instruction set 17 on the main memory.

FIG. 6 is a diagram showing an embodiment of the present invention with correspondence between state transitions and hardware. In the figure, the instruction execution unit 1 includes a register group 23, an arithmetic unit 24, and an instruction register 20.0 to which instructions read from the high-speed buffer memory 3 are set. It is shown that it consists of a microprogram sequencer 21, a control memory 22, etc. Processes registered in the execution queue in state 3 are executed in the order in which they were registered, so by tracing the queue information, it is possible to know in advance which processes are to be executed. The control unit 4 obtains execution information by looking at the PCB 14 of the process registered in the queue, and based on this information, transfers the corresponding instruction set in the main memory 6 to the buffer 3 in a specific unit from the start address or the execution interruption address. The transfer destination balance f has "free space" (E
) will be displayed, and after the transfer, “Flocked” (F) will be displayed. The control unit 4 performs this transfer operation except when the execution queue is empty or when the prefetch buffers are all full. FIG. 7 shows the flow of transfer control in this control section 4.

In the instruction execution unit 1, a process for a buffer indicated as full in the high-speed buffer memory 3 can be executed truly immediately, and is read out from the buffer memory 3 and executed. 8th
The figure shows the flow of this process execution and switching. Instructions read from the buffer are captured in the instruction register 20 and decoded to provide the address of the corresponding microprogram. Based on the microprogram read from the control memory 22, the arithmetic unit 24. It controls hardware resources such as the register file 23 and operates each instruction.

During execution of an instruction set, if an instruction that is not in the high-speed prefetch rebuffer is accessed, the instruction execution unit 1 detects this and
Switch the execution process. In other words, information (P
SW) is saved to the PCB and re-registered in the execution queue as an interrupted process. The buffer is then marked as empty and the next process to be executed is determined.

The instruction set of the suspended processes re-registered to the execution queue is transferred to the buffer memory 3 according to the order in which they are executed.

〔Effect of the invention〕

As explained above, in a multiprocessing system that processes multiple processes in parallel, when using execution queue control for process state transition, by implementing the present invention, high-speed instruction access from the instruction execution unit is possible. It becomes possible. The present invention utilizes the fact that processes to be executed are registered in an execution queue to know in advance which process is to be executed. The second is possible, and the instruction set is transferred to the prefetch rebuffer in advance.

It is characterized by high-speed instruction access.

Furthermore, since reading of queue information, transfer to the preemption rebuffer, and switching of execution processes can all be supported by hardware, the user does not need to be conscious of switching or interrupting processes at the program creation stage.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, FIG. 3 is a diagram showing the configuration of the high-speed buffer memory 3 in FIG. 1, and FIG. 4 is a diagram showing the process. FIG. 5 is a diagram showing the state transition, and FIG. 5 is a diagram showing the structure of the process entity and the configuration of the execution queue. FIG. 6 is a diagram explaining the present invention by associating state transitions with hardware, FIG. 7 is a diagram showing the flow of transfer control in the control section 4, and FIG. 8 is a diagram showing process execution and switching in the instruction execution section 1. FIG. 3 is a diagram showing a control flow. ■...Instruction execution unit, 3...High speed buffer memory. 4...Control unit, 6...Main memory. 11 Figure 2 Figure 3 Figure 6 K”

Claims (1)

[Claims] (1) An information processing device that multi-processes multiple processes is equipped with multiple instruction buffers that can be accessed at high speed from the instruction execution unit, and takes out processes from an execution queue.
The instruction set on the main memory corresponding to the process is transferred to one side of the instruction buffer 1, and the instruction execution unit reads and executes the instruction from one side of the buffer to which the instruction set has already been transferred, and during this execution An information processing device characterized in that when an instruction not in the buffer is accessed, the process is interrupted and registered in an execution queue, and at the same time, processing according to an instruction set for other processes in the instruction buffer is executed. .