JPS60252954A - Program control circuit - Google Patents

Abstract

PURPOSE:To produce no waste time for the working of a microprogram by changing programs successively for each instruction cycle in case plural programs are executed within the same device and therefore eliminating a jump time. CONSTITUTION:A memory 34 stores a group of instructions, and systems of programs P1 and P2 are selected by address selectors 32-1 and 32-2 respectively. A program switch signal X is inverted every instruction cycle. Thus in the case of logic O, for example, the instructions of the program P1 are read out. While the instructions of the program P2 are read out with logic 1. These read-out instructions are executed by a microprocessor in the next instruction cycle. Thus the instructions of two types of programs are read and executed alternately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is a book related to a program control circuit, particularly a program control circuit used when a plurality of programs are executed within the same device.

There are various examples of executing a plurality of mutually unrelated programs within the same device. An example thereof is an in-home interface device provided between a telephone line and a plurality of subscriber terminals. This interface device performs so-called multiplexing and demultiplexing operations, and a microprocessor is used for this purpose. In this MicroZoro 7, there is a program for performing multiplex operations when sending and transmitting data from each subscriber terminal to the telephone line, and a program for transmitting the multiplexed data received from the telephone line to each subscriber terminal. The program for performing the separation operation exists independently from each other. However, even though they are mutually independent, due to reasons such as the use of a single microprocessor and the need to synchronize the timing of data in multiplexing and demultiplexing, the above two programs end up must be carried out under some kind of control. This is the role of the program control circuit.

[Conventional technology]

FIG. 6 is a system diagram showing an example to which the program control circuit of the present invention is applied. In the figure, reference numeral 11 denotes a plurality of subscriber terminals (telephones), which are connected to a terminal station 15 via respective subscriber lines 12, an interface device 13, and a telephone line 14. A multiplexing/demultiplexing device (MUX) 16 is provided in the terminal station 15 and performs data multiplexing/demultiplexing operations. Note that an interface device 17 is also provided between the telephone line 14 and the device 16, and the downlink multiplexed data sent from this to the telephone line 14 is separated by the interface device 13 and distributed to each subscriber line 12. Ru. Conversely, uplink separated data from each subscriber terminal 11 is aggregated for each subscriber line 12, multiplexed by the interface device 13, and sent to the terminal station 15.

The present invention is particularly applicable to the interface device 13, taking the system of FIG. 6 as an example.

As mentioned above, in this interface device 13, a single microprocessor is shared and two types of programs are run, so both programs must be adjusted in some way to avoid job conflicts. . For this purpose, two methods have been proposed in the past. The first method is to separately prepare two program control circuits that separately manage two types of programs. on the other hand,
The second method attempts to manage both programs by interrupt control.

[Problem that the invention seeks to solve]

The first conventional method described above naturally has the disadvantage of increasing the circuit scale. Therefore, the present invention described below does not assume this first method either. On the other hand, since the conventional second method does not have such disadvantages, the present invention is premised on program control that is closer to the second method.

However, this WJ2 method is accompanied by another problem. The problem is that there is wasted time in the processing of the microprocessor, and as a result, the desired program cannot be executed at high speed. FIGS. 7(4) and 7(B) are flowcharts for explaining the problems of the conventional interrupt control method. In FIG. 4, P1 indicates processing based on the first program, and P2 indicates processing based on the second program, which are executed by interrupting the main routine.

(B) is a diagram chronologically showing a part of the flow in (4) of the same figure, and each break (t) is a -instruction cycle. When an interrupt occurs during the flow of the main routine M, a branch (JUMP) L branch instruction is executed in program processing or to the P2 side. What should be noted in FIG. 3B is the extra time indicated by the X mark in the figure, which occurs for each interrupt, so the total time is a waste of time (perhaps in terms of program processing). This waste becomes a problem.

[Means for solving problems]

The present invention provides a program control circuit that solves the above problems, and includes an address selector provided for each of a plurality of programs, and a selector that selectively selects an address from one of these address selectors. , a memory that receives an address from the selector and sends out a corresponding one of a group of instructions for executing the plurality of programs, and an instruction processor, etc. that temporarily holds the instruction sent out from the memory. That's what happens.

[For production]

The selector switches programs sequentially every instruction cycle, and the reading and execution of each instruction of one program is performed alternately with the reading and execution of each instruction of another program. In this way, since a plurality of programs can be run in a time-sharing manner without incurring one long time, there is no need to waste time in the processing of the microprocessor.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a program control circuit according to the present invention, and FIG. i is a flowchart schematically showing the processing of a microprocessor operated by the program control circuit of FIG. FIG. 2 corresponds to FIG. 7(B), and the Zoyande time indicated by the X mark in FIG. 7(B) is completely excluded. Note that t in the figure is one instruction cycle. In this way, program processing can be accelerated.

In FIG. 1, a program control circuit 31 manages two types of programs simultaneously. Two types of examples are shown for the purpose of simplifying the explanation, and those skilled in the art can easily apply the basic idea to the simultaneous management of three or more types of programs.

This program control circuit 31 has two types of programs P.
Address selectors 32-1 and 32-2 provided for each I and P2, and these address selectors 32-1, 32-2
A selector that selectively selects an address (
SEL) 33, a memory 34 that receives an address from the selector 33 and sends out a corresponding one of a group of instructions for executing the programs Pi and P2, and an instruction that temporarily holds the instructions read from the memory 34. It consists of Zosta 35. The memory 34 is a ROM (Rea) that stores the instruction group.
d 0nly M@mory). More specifically, the program processing system address selector 32-1 includes incrementers (If) 41-1. Program counter CP
CI) 42-1, program stacker (8T1)
43-1 and an address switching unit (81) 44-1. The address selector of the program processing system also consists of similar components 41-2.42-2.43-2 and 44-2. Of these, program stacker 43-1, 43-2
and the switching units 44-1 and 44-2 are switching controllers (SC
) 45 performs switching control.

FIG. 3 is a circuit showing a detailed example of the switching controller (8C) 45 in FIG. 1. The switching controller 45 includes a program counter switching section (PC8I') 51-1, a program counter switching section (PGE1) 51-2. Decoder 52.
Others 0Rr-), AND? -) , (Npa~ri IN
It's V. The signals input to the switching controller 45 are a program switching signal X, an external condition old name Y, and an instruction register 35.
The branch instruction display signal 2 and branch instruction type code JC from (Fig. 1) are output signals to the program stacker 43-1 and 43-2 (Fig. 1).
TK1.5TK2 and address switching section 44-1.44
-2 (FIG. 1). Note that CK is a cycle clock signal generated every instruction cycle.

Referring to FIGS. 1 and 3, the program switching signal At this time, an operation for reading instructions on the program P2 side is performed.

The read instruction will be read out in the next instruction cycle.
The process is executed by MPU (MPU).
When the logic of the program switching signal X is 1'', K executes the instruction on the program P1 side, and when the logic is 0'', K executes the instruction on the program P2 side.

In an instruction cycle for reading an instruction on the program Pl side (or P2 side), the address switching unit 44-1 (or 44-2)
selects and outputs an address from the program counter 42-1 (or 42-2). Referring to FIG. 3, suppose that we are currently in an instruction cycle for reading an instruction on the program Pl side (program switching signal X is logic ``0'').
, logic "・1# is ORed by inverter INV)"
The program counter switching section 51-1 passes through the ORI.
On the other hand, the logic "0#" of the signal X is OR dart OR
2, and the program counter switching section 51-2 is made non-driven. The address of the busy program counter 42-1 is selected and applied to the selector 33. It is also applied to the incrementer 41-1.

In this case, the signal X (="0") is applied to the incrementer 41-2 through the signal line L2 in FIG. 1 to stop it, but the inverter r? lJV' becomes logic "1" and is sent to the signal line LX, prompting the incrementer 41-1 to step. In other words, the address currently output from the address switching unit 44-1 is increased by +1f.Program In the instruction cycle for reading the instruction on the P2 side, the switching signal X becomes the logic "'1#", and the same operation as described above is performed on the address selector 3z-2 side.

Next, in an instruction cycle for executing an instruction on the Pl side (or P2 side) of the read program, for example, when executing an instruction on the Pl side, the program switching signal X displays a logic "'0". When executing an instruction on the program Pl side, if the instruction is a non-branch instruction, the branch instruction display signal 2
is the logic "'1", the switching controller 45 drives the program counter switching unit 51-1 through the OR dirt OR1 and the decoder 52, and the program counter 42-
Select 1. Regarding the program P2 side (X-”1
”), if it is a non-branch instruction, the program counter 42-
2, the execution instruction is a branch instruction, and the address corresponding to the branch instruction type code JCK is selected from the memory 34 as the next address NA by the address switching unit 44-1 (
or 44-2). In this branch instruction execution cycle, the code JC is decoded by the decoder 52, the program counter 42-1 (and 42-2) is non-driven, and the incrementer 4l-1 (and 4
l-2) is also not driven. Also, at this time, the decoder 52 simultaneously performs AND )1m-)ANDI (or AND2)
! When the risk occurs, the signal 5TKI (or 5TK2) is output, the program stacker 43-1 (or 43-2) is driven, and the program counter 4 immediately before the branch instruction is
The contents of 2-1 (or 42-2) are retained. This held address is stored in the next instruction read cycle when the execution of the branch instruction is completed (Z="l").
The address switching unit 44-1 (or 44-2) reads out the data again. Note that the external condition signal Y is for making it possible to execute a special command from the outside as necessary.

FIG. 4 is a time chart showing a specific example of the flow of addresses in FIG. 3. Further, FIG. 5 is a flowchart showing a specific example of the progress of the program in FIG. 4. In Figure 4, 'r, I 'r, + T
3...Represents Mori time, X in the left column.

The meanings of 11, PCI, NA, etc. are the same as explained in FIG. 1. For example, 1 is the output of the incrementer, and PCI is the output of the program counter.

Also, N, N+1, A, A+1.8, B+1, M
, N+1, etc. are the N address in the memory (ROM) 34, (
(M-1), N,
(indicates an instruction at an address such as M...). In the figure, at time T1, a non-branch instruction on the program P2 side is being executed.

At this time, address addition by incrementer I2 is prohibited. On the other hand, at this time, the address switching unit S1 forcibly selects the output of the program counter PCI. At time T2 in the figure, a branch instruction (JUM
P) 'A' is executed, and at this time addition by the incrementer 11 is prohibited.

- 10,000, at this time the switching unit S2 is the program counter PC2
force selection of output. At time T3, program P
The branch instruction (JUMP) B' on the 2 side is executed, the non-branch instructions on the program P1 side are executed at time T4, and the non-branch instructions on the P2 and P1 sides are executed at times T5 and T6, respectively.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described in detail, when a plurality of programs are executed concurrently in the same device, although these programs are basically executed simultaneously under interrupt control,
Since switching from one program to another program or vice versa can be performed with almost no jump time, processing speed can be improved, and this can be realized without making any major changes to existing hardware.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a program control circuit according to the present invention, and FIG. 2 is a micro-Zorose operated by the program control circuit of FIG. FIG. 3 is a circuit diagram showing a detailed example of the switching controller (SC) 45 in FIG. 1;
4 is a time chart showing the flow of addresses in FIG. 3 with a specific example; FIG. 5 is a flow chart showing the progress of the program in FIG. 4 with a specific example; FIG. 6 is a time chart showing the flow of addresses in FIG. FIGS. 7(4) and 7(B), which are system diagrams showing an example of application, are flowcharts for explaining problems with the conventional interrupt control method. 31...Program control circuit, 32-1.32-2.
...Apless selector, 33...Selector, 34...
Memory, 35...Instruction register, 41-1.41-2
...Incrementer, 42-1.42-2...Program counter, 43-1.43-2...Stacker,
44-1.44-2 Address switching section, 45...
Switching controller, Pi, P2...program, NA...
・Next address, JUMP...branch instruction. Patent Applicant Fujitsu Limited Patent Application Agent Akira Aoki Patent Attorney Kazuyuki Nishidate Patent Attorney 1) Yukio Patent Attorney Akiyuki Yamaguchi

Claims (1)

[Claims] 1. In a program control circuit that performs control to sequentially read instructions from a group of instructions related to a plurality of programs stored in a memory and execute processing according to the program, the program control circuit comprises: an instruction register that temporarily holds the instruction, and a next address read from the instruction register in the case of a branch instruction, an address output from the program stack in the case of a non-branch instruction, or a stacked program in the case of the branch instruction. an address switching unit that selects one of the addresses from the stack; and an incrementer that increments the output of the address switching unit in the case of the non-branch instruction; 1. A program control circuit comprising: an address selector; and a selector that sequentially switches outputs from a plurality of address selectors every instruction cycle and outputs them to address inputs of the memory.