JP2934003B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly, to a technique for parallel processing of instructions.

[Prior Art] In a conventional parallel computer system, mainly the following 2
The two systems are used to improve performance.

The first is a method of extracting parallelism in one program. Specifically, a method of simultaneously executing a plurality of continuous instructions in one program to improve the operation speed.

The second is a method for improving performance by executing a plurality of programs in parallel.

The former includes technologies such as superscalar processors and VLIW calculators. The latter is called a multiprocessor.

In addition, these devices are "Parallel processing mechanism" edited by Takahashi Yoshizo
It is described in detail in Maruzen Advanced Technology (1989) and Shinji Tomita, "Parallel Computer Architecture", Shokodo (1986).

In particular, regarding the former superscalar processor,
The SIMP computer is described in detail in pages 157 to 162 of the "Parallel Processing Mechanism", and the VLIW computer is described in detail in pages 134 to 142 of the same.

[Problem to be Solved by the Invention] VLIW, a superscalar processor of the former prior art
As for computers, there is a high possibility that a superscalar processor capable of simultaneously processing multiple instructions such as 8 instructions and 16 instructions in one chip will be realized due to the recent development of VLSI integration technology. Since there is almost no program with high parallelism capable of processing 8 instructions and 16 instructions, it is very difficult to fully utilize the performance of such hardware.

This is because the parallelism of the program varies in the first place depending on the processing form of the program, and high parallelism cannot be expected except for a very small part of processing such as array operation.

For this reason, a processor with an advanced dynamic scheduling function analyzes the data dependencies between instructions and suspends the executing instructions frequently to make the program operate properly. With a high-performance compiler as used, it is necessary to supplement a blank instruction code that does not execute anything to a part with low parallelism in a program, and it is impossible to expect an improvement in arithmetic performance.

Regarding the latter multiprocessor of the prior art, when the processor constituting the multiprocessor is a super scalar processor, contrary to the above problem, despite the high parallelism of the program, the The problem is that the number of instructions that can be processed simultaneously is small.

In other words, from another point of view, it is better if there are enough programs to be processed, but if the number of programs is small, some processors are unused and cannot be used.

Further, the former prior art generally has an independent pipeline configuration corresponding to the number of simultaneous processing instructions, but a general-purpose arithmetic unit is provided in each pipeline so that each pipeline can execute general-purpose processing. In the case of having the number of processing units, the number of arithmetic units is required as much as the number of pipelines, which causes a problem that the amount of hardware increases.On the other hand, if the function of processing each pipeline is limited like VLIW, However, there is a problem that the versatility is lost.

Therefore, an object of the present invention is to provide a data processing device capable of executing a plurality of programs at high speed and efficiently.

Another object of the present invention is to maintain the versatility of the pipeline without significantly increasing the amount of hardware in this data processing device.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a data processing device which combines a superscalar processor capable of executing a plurality of instructions in parallel and a multiprocessor, and provides the following data processing device. is there.

That is, in order to achieve the above object, the present invention provides a means for extracting a plurality of instructions that can be executed in parallel from a plurality of programs in parallel, and executing the extracted instructions in parallel.
A first data processing device having a plurality of arithmetic units shared by the plurality of programs is provided.

From a different point of view, this data processing device can be considered as a multiprocessor system comprising a plurality of scalar processors that share a computing unit and that can execute a plurality of instructions in parallel.

Further, in order to achieve the above object, the present invention provides a memory for storing a plurality of programs including a system control instruction indicating the number of instructions that can be executed in parallel, one or more programs executable in parallel according to the system control instruction. An instruction sequence reading unit that retrieves an instruction sequence composed of instructions in parallel from each of a plurality of programs stored in a memory; a plurality of decoders that operate in parallel; and a plurality of instruction units that are retrieved in parallel by the instruction sequence reading unit. Distribution means for distributing a plurality of instructions forming the instruction sequence to the plurality of decoders; a plurality of types of the plurality of arithmetic units for executing the decoded instructions in parallel; a plurality of the decoders and a plurality of the arithmetic units In accordance with the type of instruction decoded by each decoder, and arithmetic unit connection means to be connected to each other, and programs corresponding to instructions to be executed in parallel. Register file connecting means for connecting the plurality of arithmetic units and the plurality of register files according to a program to which an instruction executed by each arithmetic unit belongs, in response to a connection request from the arithmetic unit, And a second data processing device characterized by having:

In the second data processing device, instead of the arithmetic unit connection means, a plurality of instructions decoded by the plurality of decoders and provided in correspondence with the respective programs to be executed in parallel are included in each program. A plurality of dynamic scheduling means for analyzing instruction dependencies and controlling instruction execution; and connecting the plurality of decoders and the plurality of dynamic scheduling means in accordance with a program to which an instruction decoded by each decoder belongs. A second computing unit connection unit that connects the plurality of dynamic scheduling units and the plurality of computing units according to an instruction type of an instruction scheduled by the dynamic scheduling unit. , May be provided.

In addition, the instruction sequence readout unit is provided in correspondence with a plurality of programs to be executed in parallel. The instruction sequence is composed of the parallel executable instructions of each program in accordance with a system control instruction of the corresponding program. , And a plurality of program counters, each having a variable count unit width, which are sequentially generated from the start read address and the number of read instructions that can be executed in parallel.

Further, the register file connection means is configured to provide a program number for identifying a program to which the instruction belongs to the instruction decoded by the plurality of decoders, and to be provided to the instruction to be executed provided in the arithmetic unit. The connection request may include a means for adding a program number to the connection request, and a switch matrix for connecting the arithmetic unit and the register file according to the connection request and the added program number.

Instead of giving a program number for identifying the program to which the instruction belongs to the instruction thus decoded, a plurality of programs stored in the memory are required by the own program in each system control instruction. A configuration control unit that also includes information on the number of arithmetic units and that integrally controls the connection of the connection units according to a system control command may be provided.

Preferably, when the number of a plurality of instructions that can be executed in parallel extracted from the plurality of instructions is larger than the number of the plurality of decoders provided, the distribution means preferably performs priority control on a per-program basis to provide a plurality of instructions. It is preferable to have priority control means for distributing to the decoder.

Further, it is preferable that a plurality of instructions decoded in parallel by the plurality of decoders are executed on a program-by-program basis with priority control for each type of arithmetic unit.

[Operation] According to the data processing device of the present invention, a plurality of instructions that can be executed in parallel are extracted from a plurality of programs, and the extracted instructions are shared by a plurality of arithmetic units by a plurality of programs, and To run.

Accordingly, a plurality of programs can be executed efficiently at high speed, and the amount of hardware is
The versatility of the pipeline can be maintained without much increase.

According to the second data processing device of the present invention,
The instruction sequence reading means takes out, in parallel, an instruction sequence consisting of instructions that can be executed in parallel according to the system control instruction from each of the plurality of programs stored in the memory. A plurality of instructions constituting the plurality of instruction sequences extracted to the plurality of decoders are distributed to the plurality of decoders, and the arithmetic unit connecting means connects the plurality of decoders and the plurality of arithmetic units according to the instruction type decoded by each decoder. Respectively, and the register file connection means is
In response to a connection request from a computing unit, the plurality of computing units and the plurality of register files are connected according to a program to which an instruction executed by each computing unit belongs.

As a result, while maintaining the independence of multiple programs,
A plurality of arithmetic units are shared between programs, and a plurality of programs are executed at high speed and efficiently.

In the second data processing device, when the dynamic scheduling means is provided as described above, the dynamic scheduling means connecting means connects the plurality of decoders and the plurality of dynamic scheduling means, Connect each according to the program to which the decoded instruction belongs,
The second computing unit connection unit connects the plurality of dynamic scheduling units and the plurality of computing units to each other according to the instruction type of the instruction scheduled by the dynamic scheduling unit. In addition, it is possible to analyze the dependency between instructions in each program and control the execution of instructions.

[Embodiment] In this embodiment, for convenience of explanation, a data processing apparatus capable of simultaneously executing four programs and simultaneously processing a total of eight instructions will be described as an example.

First Embodiment Hereinafter, a first embodiment of the data processing device according to the present invention will be described.

FIG. 1 shows the configuration of the data processing apparatus according to the first embodiment.

In the figure, 101 is a 4-port multi-port instruction cache memory, and 1021 to 1024 are variable program counters VPC, which correspond to programs 1 to 4, respectively.

15 is a multi-program instruction sequence fetch control device, 45 is a program number supply unit, 601 to 608 are decoders, 69 is an instruction execution unit connection device, 911 to 914 are LOAD / STORE units L / S, and 921 to 928 are integer arithmetic units IALU, 931 to 934 are floating point adders FADD, 941 to 944 are floating point multipliers FMUL,
75 is a register file connection device, and 81 to 84 are 12-port multi-port register files, which correspond to programs 1 to 4, respectively. 70 indicates a 4-port multiport data cache memory.

Also, 1031 to 1034, 41 to 44, 51 to 54 are control signal lines,
Each corresponds to program 1 to program 4.

401-408, 61-68, 211-214, 221-228, 231-234,
241 to 244 are control signal lines, 11 to 14 are 36 byte width signal lines,
Each corresponds to program 1 to program 4, 21 to
28 is a 4-byte width data signal line, 701 to 704, 711 to 714 are control signal lines + 4-byte width data signal line, 721 to 728, 731 to 7
34, 741 to 744 are control signal lines + 4 byte width data signal lines 3
Books, 8101-8112, 8201-8212, 8301-832, 8401-8412
Represents a 4-byte data signal line.

 Next, the operation will be described.

The variable program counters 1021 to 1024 send an instruction sequence fetch signal to the memory of 101 through the signal lines 1031 to 1034, and the multi-port instruction cache 101 outputs a plurality of simultaneously executable program instructions and one system control instruction. Instruction sequence for four programs.

The fetched four instruction sequences enter 15 multi-program instruction sequence fetch control devices through signal lines 11 to 14, respectively.

The multi-program instruction sequence fetch control device 15 sends a program execution instruction from each of the four instruction sequences sent to the decoders 601 to 608 via signal lines 21 to 28, respectively. Updating of the variable program counters 1021 to 1024 by signal lines of ~ 54,
The parallelism information of each program is sent to 45 program number supply units via signal lines 41 to 44.

The program number supply unit 45 supplies each instruction passed to the decoders 601 to 608 with a program number indicating a program to which the instruction belongs, based on the transmitted signal.

The decoders 601 to 608 decode the transmitted instruction, obtain an instruction execution unit number necessary to execute the instruction, and send the instruction execution unit number to the instruction execution unit connection device. The instruction execution unit is obtained from the decoded instruction type.

Each instruction decoded by the decoders 601 to 608 is connected to a signal line 61
Through ~ 68, with 69 instruction execution unit connection devices,
It is connected to an instruction execution unit necessary to execute the instruction.

From the instruction execution unit connected to the decoder, a connection request is issued to the register file connection device 75 by a control / data signal line connecting the unit and the register file connection device 75 in order to access data.

In the register file connection device 75, the signal line connected to the port of the corresponding register file and the data signal of the control / data signal line depend on the program number of the connection request sent from the control / data signal line and the connection request type (READ / WRITE). Connect the wires.

For example, when the IALU of 921 executes an instruction, the connection request of the program number 1 and the READ request is issued by the signal line of 721, and the register file connection device 75 sets the port input / output lines 8101 and 8102 of the register file 81 to: The two data READ lines in 721 are connected.

In the LOAD / STORE unit L / S of 911 to 914, 70 multiport data cache memories and register files 81 to 84 are provided by control / data signal lines 701 to 704 and 911 to 914.
LOAD / STORE data during the period.

Here, FIG. 2 shows an example of an instruction sequence configuration of a program in the memory 101.

In the figure, reference numeral 1011 denotes an instruction sequence of the program 1, 1012 denotes an instruction sequence of the program 2, 1013 denotes an instruction sequence of the program 3, and 1014 denotes an instruction sequence of the program 4.

The instruction sequence that can be executed simultaneously in each program is composed of a system control instruction and several program execution instructions in parallel, and the system control instruction includes the parallelism information of the program in the upper one byte. Each instruction is composed of 4 bytes.

For example, in program 1 of FIG.
12 bytes of ~ I2 make up one instruction sequence, C11 is the upper 1
System control instructions I1 and I2 each including a parallelism of 2 in a byte represent program execution instructions that can be executed simultaneously.

Next, FIG. 3 shows the configuration of the variable program counter VPC 1021 (see FIG. 1).

In the figure, 501 is an adder, 502 is a register, 51 is an input control signal line, 1031 is an output control signal line, and 503 is a control signal line.

In the VPC 1021, the number of bytes of the instruction sequence is input from the fifteen multi-program instruction sequence fetch control devices via the signal line 51, and the head address of the previously calculated instruction sequence from the register 502 is sent to the signal line 503. Becomes the output of 1031 and further becomes the two input values of the adder 501, and the result is stored in the register 502.

Next, the memory 10
An operation example of extracting the instruction sequence of the program from 1 will be described.

The VPC 1021 stores 1011 in FIG.
By specifying the start address of I1 of the instruction sequence of the program 1 and 12 bytes as the number of data bytes to be extracted, the control instruction C12 of the next instruction sequence from the first instruction I1 is extracted.

At this time, the degree of parallelism of the instruction sequence to be fetched, that is, the number of fetched data bytes is obtained from the fetched control instruction C11.

Next, FIG. 4 shows the configuration of 15 (see FIG. 1) multi-program instruction sequence fetch control devices.

In the figure, reference numeral 151 denotes a switch matrix network to which arbitrary input lines and output lines can be connected by switches on a grid of input lines and output lines.

152 is a multiple program control device, and 153 is a switch control device.

11, 12, 13, and 14 are data input lines having a width of 36 bytes, which are connected to a switch matrix network 151.
The data input line 11 includes signal lines 111 to 119, and 12 includes 121 to 12 data lines.
9, 13 comprise 131-139, 14 comprise 141-149).

Reference numerals 21 to 28 denote 4-byte data output lines, which are output from 151 and are connected to eight decoders 601 to 608, respectively.

41 to 44 and 51 to 54 are output from the control signal output line 152.
The former is connected to the program number supply units 45 and 153, and the latter is connected to the variable program counters 1021 to 1024.

Reference numerals 31 to 34 denote data signal lines having a 4-byte width, and reference numeral 154 denotes a control signal line.

Next, the operation of the multiple program instruction sequence fetch control device 15 will be described.

Each instruction of the instruction sequence of the program 1 fetched from the memory 101 connects the data input lines 111, 112,.
, 121, 122,..., 131, 132,..., And program 4 instruction sequences, 141, 142,. Enter 151.

At 151, the data input line to which the program execution command has been sent is sequentially connected to the output lines 21 to 28 in the order of program 1 to program 4 by the switch control device 153. Also, the data input lines to which the system control commands of the programs 1 to 4 are sent are connected to the output lines 31 to 34, respectively.

The 152 multi-program control device performs scheduling among four programs based on the degree of parallelism of the program in the system control instruction of each program sent by 31 to 34, and executes the program that has become executable. , The parallelism information of the program is sent out using the signal line corresponding to the program among the output lines 41 to 44.

Nothing is sent to the program whose execution has been stopped.

Furthermore, for the executable program, the update degree (instruction string fetch byte width) of the variable program counter VPC, which is obtained from the parallel degree information of the program, is set to 51.
The signal is transmitted using the signal line corresponding to the program among the output lines of .about.54.

No output is output to the program whose execution has been stopped, and the variable program counter does not operate.

The system control instruction of the program whose execution has been stopped is used for the next scheduling.

The switch control device 153 controls the control line 154 based on the parallelism information of each program sent by 41 to 44.
To control 151.

FIG. 5 shows a multi-program instruction sequence fetch control device 15.
1 shows a configuration of 152 multiple-program control devices, which are one of the components of FIG.

In the figure, 301 to 304 are units for extracting the upper 1 byte from the input data of 4 bytes, 30 is a scheduling control device, 331 to 334 are switches, 341 to 344 are quadrupled input values, and further add 4 Computing unit.

Numerals 31 to 34 denote 4-byte data input lines which are connected to the units 301 to 304, respectively.

41 to 44, 51 to 54 are control signal output lines, 41 to 44 are output from switches 331 to 334, respectively, and arithmetic units 341 to 344,
It is connected to the switch control device 153 and the program number supply unit. 51 to 54 exit the calculators 341 to 344, respectively.
It leads to a variable program counter VPC of 1021 to 1024.

 Reference numerals 311 to 314 and 321 to 324 denote control signal lines.

Next, the operation of the multiple program control device 152 will be described.

The system control instruction of each program enters units 301-304 through 31-34, where the upper one byte of the parallelism information is taken out and output to 311-314.
Enter 34 switches and 30 scheduling controllers.

At 30, the scheduling of the four programs is performed based on the parallel degree information of the four programs input through the input lines 311 to 314, and the executable program is
Among the control output lines 321 to 324, a switch ON signal is output to the control output line corresponding to the program, and the program whose execution has been stopped outputs nothing to the corresponding control output line (OF
F).

The switches 331 to 334 are controlled by the control signal lines 321 to 324 from the device 30, and operate to connect the input lines 311 to 314 and the output lines 41 to 44.

Then, the switch corresponding to the executable program is turned ON, and the parallel degree information is transmitted.

The switch corresponding to the program whose execution has been stopped is OF
At F, the parallelism information is not sent to the output line.

The output lines 41 to 44 of the switches 331 to 334 are output lines from the plurality of program controllers 152 to the outside, are input lines of the arithmetic units of 341 to 342, and the degree of parallelism is quadrupled by the arithmetic units.
Further, by adding 4, the update degree (instruction string fetch byte) of the corresponding variable program counter VPC is obtained and output by 51 to 54.

FIG. 6 shows the configuration of 30 scheduling control devices, which are one of the components of the device 152.

9011 and 9012 are 4-input 4-output switch matrix networks,
Reference numerals 9021 to 9023 denote arithmetic units, and 90 denotes a switch control device.

311 to 314 are control signal input lines, each of which has a unit 301
Exit through ~ 304 and connect to switch 9011.

Reference numerals 321 to 324 denote control signal output lines, respectively, which exit the switch 9012 and control the switches 331 to 334. 9001, 9002, 9031 ~
9036, 9041 to 9044 are control signal lines.

FIG. 7 shows a switch 9011 by the switch control device 90,
This is a table showing the operation of the 9012.

The connection between the input lines 311 to 314 and the output lines 9031 to 9034 of the 9011 and the output lines 321 to 324 of the 9012 and the input lines 9041 to 9044 are switched symmetrically in a round robin manner every machine cycle.

As a result, the priority of each program is also switched to round robin as shown in the table. In this embodiment, one cycle of switch switching is four machine cycles corresponding to the number of programs executed simultaneously.

 FIG. 8 is a table showing the operation of the unit 9021.

When 9041 is ON, if the inputs from 9031 and 9032 are a and b, respectively, the output will be 9035,
In 9042, if the output of 9035 is equal to or less than the number of simultaneous instruction processing executed by the system of the present invention (8 in this embodiment), the output is turned ON.

 When 9041 is OFF, 9021 does not operate.

Similarly, the operation of the units 9022 and 9023 also determines the output value according to the control signal line and the two inputs.

FIG. 9 is a flowchart showing the operation of the units 9021 to 9023 inside the unit 30.

As shown, after setting the initial values of the parameters,
Switch 9041 is turned ON by the switch controller 90, and the unit
Activate the 9021.

Unit 9021 adds the two input values and sets the value to 9035
And if the value is greater than 8, end.
If smaller, 9042 is turned on, and the unit 9022 is operated. Thereafter, the same operation is performed up to the unit 9023.

As described above, the input of each unit is switched to the round robin, and when the added value of the two input values is smaller than 8, the next unit is sequentially operated to give the program priority to the round robin.

By the above operation, the degree of parallelism of each program is input to the skeletal ring control device 30 through 311 to 314, and the switch 9011 connects 311 to 314 with 9031 to 9034 to assign the priority of the program. And the sum of the parallelism of each program is
Within the range not exceeding the simultaneous instruction processing execution line of 8, 9041 to
Turn on the control line of 9044.

Then, by the switch 9012, 9041 to 9044 and 321-324
And the switch connection control signal (ON
/ OFF).

FIG. 10 is a flowchart showing an operation of controlling a switch matrix network 151 by a control signal line 154 of 153 switch controllers (see FIG. 4) which are one of the components of the multiple program instruction fetch controller 15. It is a thing.

Since the instruction sequence of each program transmitted by the input lines 11 to 14 of the switch matrix network 151 is composed of a program execution instruction for the degree of parallelism, that is, a program execution instruction for the degree of parallelism, and a system control instruction, each
The instruction sequence flows from the top of the nine 4-byte width input lines constituting the 36-byte width input line to (parallelism + 1).

The switch control device 153 performs the processing in order from the program 1.
Based on the degree of parallelism of the program sent from the controller, input lines corresponding to the first degree of parallelism of 111 to 119 constituting 11 are connected in order from the head of output lines 21 to 28 of 151, respectively. Since the system control command is flowing to the (parallelism + 1) th input line, this is connected to the output line 31 of 151.

The same processing is performed for the program 2, the program 3, and the program 4, and the input lines 42, 43, 44
Based on the degree of parallelism of each program sent, the input line through which the program execution instruction flows is connected to the output lines 21 to 28 from the unconnected ones in order from the top, and the system control instruction flows Input lines to 151 output lines 32 for program 2, 33 to program 3,
34 is connected to the program 4.

Next, the operation of the multiple program instruction fetch control device 15 will be described with a specific example of processing.

In FIG. 2, I1, I2, and C12 are used as the instruction sequence of the program 1 from the memory 101, and J is used as the instruction sequence of the program 2.
1, J2, C22 are K1, K2, C3
Assuming that L1, L2, and C42 are extracted as instruction sequences of program 4 in FIG. 4, in FIG. 4, instruction sequences of respective programs are 111 to 113, 121 to 123, 131 to 133, and 141 to 1 respectively.
Through 43 enter the 151 switch matrix network.

The switch control device 153 includes the system control instructions C11, C21, C3
1. Based on the parallelism information 2, 2, 2, 2 of each program inputted from 41 to 44 by C41, 111 in 151 is 21, 11 in 151.
2 is 22, 113 is 31, 121 is 23, 122 is 24, 123 is 32, 131 is 2.
5, 132 is connected to 26, 133 is connected to 33, 141 is connected to 27, 142 is connected to 28, and 143 is connected to 34.

Connected to 31-34 and sent to 152 multiple program controllers, system control instructions C12, C22,
In C32 and C42, the parallelism information 2, 2, 1, and 8 of each program is extracted from the units 301 to 304 in FIG. The extracted parallelism information is sent to the scheduling control devices of the switches 331 to 334 and 30 by 311 to 314, respectively.

In the scheduling control device 30, the second program priority in the machine cycle shown in FIG.
Assuming that the order is 2, 3, the output line 321 of FIG.
Only the switch 334, the computing unit 344, and the program counter 1024 operate, and the memory 101
Instruction sequence L3, L4, L5, L6, L7, L8, L of program 4
9. Take out only L10 and C43.

The fetched instruction sequence enters the switch matrix network of 151 through 141-149.

Based on the parallelism information 8 of the program 4 input from only 44 out of 41 to 44, the switch control device 153
Within 141 is 21, 142 is 22, 143 is 23, 144 is 24, 145 is 25, 1
46 connects to 26, 147 connects to 27, 148 connects to 28, and 149 connects to 34.

 ..., the same operation is performed.

FIG. 11 is a flowchart showing the operation of the program number supply unit 45 (see FIG. 1).

The program number “1” is output to the output lines 401 to 408 of the program number supply unit in order from the beginning by the degree of parallelism of the program 1 sent from the input line 41. Similarly, the program number “2” is sequentially output from the beginning to the unused portion of the output lines 401 to 408 by the parallel degree of the program 2 obtained from the input line 42, and the same operation is performed for the program 3 and the program 4. Even do.

FIG. 12 shows the configuration of the 69 instruction execution unit connection device (see FIG. 1).

In the figure, 691 is a switch matrix network, 692 is a switch control device, and 61 to 68 are input lines to which instructions, program numbers, and instruction execution unit numbers respectively decoded by the decoders 601 to 608 are sent. Two are 612 each
.About.682 signal lines connect to the switch matrix network 691, and the other one connects to the switch controller 692 by 611.about.681 signal lines, respectively.

Output lines 211-214 are LOAD / STORE units 911-9 respectively
14, 221 to 228 are IALU 921 to 928, respectively, 231 to 234 are FADD931 to 934, respectively, and 241 to 244 are FMUL941, respectively.
Connect with ~ 944.

693 is a control signal line for the switch control device 692 to control the switch matrix network 691.

Next, the operation of the instruction execution unit connection device 69 will be described.

FIG. 13 is a flowchart showing the operation of the switch control device 692 for controlling the switch matrix network 691 by the control signal line 693.

According to 611 to 681, the instruction execution unit number necessary to execute each decoded instruction is stored in the switch control device 69.
Sent to 2.

In 692, in order from 611, based on the instruction execution unit number obtained therefrom, if the number is 1 (L / S), output lines 211-214; if 2 (IALU), 221-228; 3
(FADD) is 231-234, while 4 (FMUL) is 241-244
, 612 to 682 are sequentially connected from the head.

FIG. 14 shows a block diagram of a 75 register file connection device (see FIG. 1).

In the figure, reference numeral 751 denotes a switch matrix network, and 752 denotes a switch control device.

711-714 are input / output lines from each L / S to 75, of which 711
1 to 7141 send a program number and a connection request from each L / S to 752, and 7112 to 7142 are connected to 751 by 4-byte input / output lines. Similarly, 721 to 744 are operation execution units IALU, FADD,
Input / output lines from FMUL to 75, of which 7211 to 7441 transfer program numbers and connection requests from each execution unit to 752
721a-744a, 721b-744b, 4-byte width output line,
721c to 744c are 4-byte input lines and are connected to 751.

8101 to 8112, 8201 to 8212, 8301 to 8312, and 8401 to 8412 are Program 1, Program 2, Program 3,
Multi-port register file corresponding to program 4
These are input / output lines connected to the ports 81, 82, 83 and 84.

753 is a control signal line for the 752 to control the 751.

 Next, the operation of the register file connection device 75 will be described.

FIG. 15 is a flowchart showing the operation of the control signal line 753 for controlling the switch matrix network 751 by the control signal line 753. U (1), U (2), U (3), U
(4) indicates the numbers of L / S, IALU, FADD, and FMUL, respectively.

According to 7111 to 7441, the instruction execution unit sends a program number and a connection request to the switch control device 752.

In 752, in order from 7111, if it has issued a request, based on the program number and connection request obtained from it, if the program number is 1, I / O lines 8101-81
For 12, 2 for 8201 to 8212, for 3 for 8301 to 8312
On the other hand, if it is 4, the necessary number of connections according to the connection request are connected to 8401 to 8412 sequentially from the top.

The required number here is READ / WRIT for L / S
One for the request of E, two for the other instruction execution units, and one for the WRITE request.

In the first embodiment, the VLIW computer is used as a basis, and all register conflicts are examined and resolved by the compiler, and the register conflicts are not checked at the time of execution.

However, it is also possible to use a super scalar processor that checks for register conflicts at the time of execution. In this case, as shown in the second embodiment described below, a scheduler for the number of simultaneously executable programs (4 in this embodiment) ) May be provided so that each scheduler performs scheduling between instructions decoded by the decoders 601 to 608 based on the program number supplied from the program supply unit 45 for each program.

Second Embodiment Hereinafter, a second embodiment of the data processing device according to the present invention will be described.

FIG. 16 shows the overall configuration of the data processing device according to the present embodiment.

In the figure, reference numeral 2101 denotes a multi-port instruction cache memory having a 4-port configuration, and reference numerals 21021 to 21024 denote variable program counters VPC, which are used to read instructions of individual programs. Reference numerals 2601 to 2608 denote instruction decoders, and reference numerals 2041 to 2044 denote dynamic schedulers of a superscalar processor. 2911 to 2914 are LOAD / STORE units (L /
S), 2921 to 2928 are integer arithmetic units (IALU), 2931 to 2934 are floating point adders (FADD), 2941 to 2944 are floating point multipliers (FMUL), 2081 to 2084 are 24-port configurations (16 inputs, 8
Output) A multiport register file that temporarily holds the data of each individual program.

2070 indicates a 4-port multi-port data cache memory.

2015 to 2018 are switch circuits, switch 2015 is memory
2101 and instruction decoders 2601-2608, and switch 20
16 is an instruction decoder 2601-2608 and a dynamic scheduler 2041-
2044 and switch 2017 is a dynamic scheduler 2041
~ 2044 and various ALU 2911 ~ 2914, 2921 ~ 2928, 2931 ~ 2934,
2941 to 2944, and switch 2018 switches to various ALU 2911 to 2
944 is connected to register files 2081 to 2084.

Reference numeral 2050 denotes a configuration control unit that changes the system configuration.

Reference numerals 21031 to 21034 and 2511 to 2514 denote control signal lines, each of which corresponds to an individual program.

2061-2068 are signal lines for transmitting decoded instructions, 41
11-4118 and 4121-4128, 4211-4218 and 4221-4228, 4311
4318 to 4321 to 4328, 4411 to 4418 and 4421 to 4428 are similar signal lines, each corresponding to an individual program. 20
52 to 2055 are control signal lines.

2011 to 2014 are 32-byte signal lines, each corresponding to a separate program.

2021 to 2028 are 4-byte data signal lines, 2701 to 2704,
2711 to 2714 are control signal lines + 4 byte width data signal lines, 27
21 to 2728, 2731 to 2734, 2741 to 2744 are control signal lines + 4 byte width data signal lines x 3 (input 2, output 1), 8101 to
Reference numerals 8124, 8201 to 8224, 8301 to 8324, and 8401 to 8424 represent control signal lines + 4 byte width data signal lines.

Next, a standard operation of the data processing apparatus according to the second embodiment will be described.

VPC 21021 to 21024 send the instruction fetch signal to signal line 21031.
To the memory 2101 through 21021034, and fetches one or more instructions from the memory 2101 for four programs.

The fetched instructions are sent to the switch 2015 via the signal lines 2011 to 2014, respectively.

The switch 2015 makes a circuit connection between the signal lines 2011 to 2014 and 2021 to 2028, and sends the instruction fetched from the memory 2101 to the instruction decoders 2601 to 2608.

The instruction decoders 2601-2608 interpret the transmitted instruction.

Each decoded instruction is sent to the switch 2016 via the signal lines 2061 to 2068. Switch 2016 signal line
2061-2068 and 4111-4118, 4211-4218, 4311-4318, 44
Perform circuit connection with 11 to 4418, instruction decoder 2601 to 2608
The extracted decoded instructions are sent to the dynamic schedulers 2041 to 2044 corresponding to each program.

The dynamic schedulers 2041 to 2044 check the data dependence and the like of the decoded instructions that have been sent, and execute a plurality of instructions simultaneously within a range that does not cause register conflict.

Specifically, execution of an instruction causing a register conflict is delayed. The instructions of each program determined to be simultaneously executable or delayed executable by the dynamic schedulers 2041 to 2044 are stored in a register file corresponding to each program.
The instruction is executed using 2081 to 2084.

At this time, ALU 2911 to 2914, 2921 assigned to each program by switches 2017 and 2018 as arithmetic devices
~ 2928, 2931-2934, 2941-2944 are used.

In the second embodiment, a superscalar processor that checks for register conflicts at the time of execution is assumed. However, a VLIW computer that does not check for register conflicts at the time of execution can be considered as a basis. In this case, the dynamic schedulers 41 to 44 are not required. All register conflicts will be investigated and resolved by the compiler.

Hereinafter, the configuration change operation of the data processing apparatus will be described.

FIG. 17 shows an example of an instruction sequence configuration of a program in the memory 101.

21011 is an execution instruction of program 1, 21012 is an execution instruction of program 2, 21013 is an execution instruction of program 3, 21014
Represents an execution instruction of the program 4.

 Each instruction is composed of 4 bytes.

In the figure, I11, I12... Represent program instructions and C11 and C41 represent system control instructions.

In the second embodiment, the system control instruction includes the required ALU type and the number thereof along with the degree of parallelism of the program.

In the figure, an instruction sequence 21011 has a parallelism of 2 specified by a system control instruction C11, and I11 and I12, I21 and I22, I31 and I32,.

The instruction sequence 21012 is an example of an instruction sequence having no system control instruction.

The instruction sequence 21013 has a parallelism of 4 specified by the system control instruction C31, and K21 to K24 mean instruction sequences that can be executed simultaneously.

The instruction sequence 21014 has a parallelism of 8 specified by the system control instruction C41, and L11 to L18 mean instruction sequences that can be executed simultaneously.

When a system control instruction is used in a user program, a method of inserting the system control instruction every time the configuration of the program is changed, or a method of inserting the system control instruction each time in a read instruction sequence is used. FIG. 18 is a configuration diagram of the VPC 21021. VPC21022 ~
21024 also has a similar configuration.

In the figure, 2500 is a 2-bit shifter, 2501 is an adder, 2502,
2503 indicates a register.

When the configuration is changed, the signal from the configuration control unit 2050 to the signal line 25
The value of the number of executed instructions transmitted via 11 is shifted by 2 bits (quadrupled) by the shifter 2500, and the number of instruction read bytes stored in the register 2503 is rewritten.

The register 2502 stores the instruction read start address calculated last time.
It becomes the output of VPC 21021, and the memory 210 is output via the signal line 21031.
Sent to one. That is, the VPC 21021 is a program counter that outputs the read start address of the instruction and the number of read instructions.

Further, the outputs of both registers become two input values of the adder 2501, and the operation result is stored in the register 2502 as the next instruction read start address.

 FIG. 19 shows the configuration of the configuration control unit 2050.

2551 to 2554 are the degree of parallelism and required AL from the system control instruction.
A unit for extracting the U number, 5631 to 5634 are registers for storing parallel degree information of each program, 5641 to 5644 are registers for storing required ALU number information of each program, and 2571 is for controlling the number of instructions to be simultaneously read from each program. Multiple program control unit, 2572, required for each program
An ALU assignment control unit that assigns ALUs.

Reference numerals 2581, 2582, and 2583 denote switch control units that control switching of the switches 2015, 2016, 2017, and 2018, respectively.

Reference numeral 2059 denotes an inter-program scheduling unit that determines a priority order among the four running programs and controls the execution order of the programs according to the priority order.

 Next, the operation of the configuration control unit 2050 will be described.

When a system control instruction is detected in any of the dynamic schedulers 2041 to 2044, the corresponding signal line 2541 to 2525
By 44, it is conveyed to units 2551-2554. The degree of parallelism included in the instruction and the required number of ALUs are extracted in units 2531 to 2534, and the extracted degree of parallelism is determined by the signal line 5611.
According to 565614, the required number of ALUs is stored in the corresponding registers 5631 to 5634 and 5641 to 5644 by signal lines 5621 to 5624.

The multiple program control unit 2571 and the ALU assignment control unit 2572 are controlled by the inter-program scheduling unit 2059.

The multiple program control unit 2571 has registers 5631 to
Based on the degree of parallelism of each program stored in 5634,
The number of read instructions of each program is determined, and the number of read instructions is output through control lines 2511 to 2514.
024, inform the switch control units 2581, 2852.

ALU allocation control unit 2572 has registers 5641 through 564
Based on the required number of ALUs for each program stored in 4,
The ALU usage number information of each program is determined and transmitted to the switch control unit 2583.

The multiple program control unit 2571 is a unit that obtains the number of read instructions of each program to be executed, that is, the number of instruction decoders assigned to each program.

That is, the multiple program control unit 2571 checks the parallelism of the programs in order from the program with the highest priority indicated by the inter-program scheduling unit 2059. As long as the sum does not exceed the number of instruction decoders (n = 8 in this embodiment), the number of instructions to be taken out in each program is determined, and the number of instructions is determined by signal lines 2511 to 2511.
Output to 2514. Execution of the program is temporarily frozen when the instruction decoder can be assigned. The program whose execution has been frozen is then released if the priority becomes higher.

FIG. 20 is a flowchart showing the operation of the multiple program control unit 2571.

If the program to be executed is converted by the compiler for the system based on VLIW computer (in the figure,
Compile mode ON), and assigns instruction decoders to the program by the specified degree of parallelism in the order of program priority.

Also, for a program for a system based on superscalar, it is basically the same as VLIW, but the surplus instruction decoders are also allocated in descending order of priority.

The ALU assignment control unit 2572 assigns a necessary ALU to each program to be executed. Like the multiple program control unit 2571, the required number of various ALUs is checked in order from the program with the highest priority indicated by the inter-program scheduling unit 2059. As long as the sum does not exceed the total number of various ALUs, the number of ALUs to be assigned to each program is determined, and the information is transferred to signal line 2.
Output to 540.

Programs that cannot be assigned the required ALU are frozen. The frozen program is then unfrozen when the required ALU becomes available.

FIG. 21 is a flowchart showing the operation of the ALU assignment control unit 2572.

If the program to be executed is converted by the compiler for the system based on VLIW computer (in the figure,
Compile mode is ON), and ALUs are allocated by the specified number of ALUs in order of program priority. For a program for a superscalar-based system, at least one ALU is assigned at a time, and the remaining ALUs are assigned one by one in descending order of priority.

The switch control unit 2581 is connected via a control line 2052,
The switch 2015 is switched to transmit the instructions fetched in each program to the instruction decoders 2601-2608.

The switch control unit 2582 is connected via a control line 2053,
The switch 2016 is switched, and the instructions decoded by the instruction decoders 2601 to 2608 are transmitted to the corresponding program dynamic schedulers 2041 to 2044.

The switch control unit 2583 is connected via the control line 2055,
Switch switch 2017, 2018, various ALU 2911-2914, 2
921 to 2928, 2931 to 2934, 2941 to 2944 are connected to the corresponding program dynamic schedulers 2041 to 2044 and register files 2081 to 2084.

FIG. 22 is a configuration diagram of the switch 2017. 1701-1704
Represents an ALU selection switch, and 175 represents an ALU connection switch.

In the figure, 4121-4128, 4221-4228, 4321-4328, 4421-
4428 is an input line from the dynamic scheduler, 2055 is an input line from the configuration control unit 2050, 17101-17120, 17201-1
7220, 17301 to 17320, and 17401 to 17420 are signal lines connecting each ALU selection switch and the ALU connection switch.
221-2228, 2231-2234, 2241-2244 are various ALU2911-
Output lines connected to 2914, 2921 to 2928, 2931 to 2934, and 2941 to 2944.

The number of output lines from each ALU selection switch 1701-1704 is A
Equal to the total number of LUs, signal lines 17101-17120, 17201-17220,
17301-17320, 17401-17420 are ALU2911-294, respectively
Corresponds to 4: 1.

The switching of the ALU connection switch 2175 is controlled via a control line 2055 from the configuration control unit 2050.

Each ALU selection switch 1701-1704 and various ALU 2911-291
4, 2921 ~ 2928, 2931 ~ 2934, 2941 ~ 2944, connect the required ALUs to create a dynamic scheduler 2041-2
044 is connected to the ALU required to execute the instruction.

FIG. 23 is a configuration diagram of the switch 2018. 1801-1804
Represents a port selection switch, and 2185 represents an ALU connection switch.

2711-2714, 2721-2728, 2731-2734, 2741-2744
Are ALU 2911-2914, 2921-2928, 2931-2934, 294
A signal line connecting 1 to 2944 and the ALU connection switch 2185, 2055 is an input line from the configuration control unit 2050, 18101 to 18120, 1820
1 to 18220, 18301 to 18320, 18401 to 18420 are signal lines connecting the ALU connection switch 2185 and the port selection switches 1801 to 1804, 8101 to 8124, 8201 to 8224, 8301 to 8324, 8401 to 8424
Are data lines connected to the ports of each of the register files 2081 to 2084.

Port selection switches 1801-1804 and ALU connection switch 2
The number of signal lines connecting to 185 is equal to the total number of ALUs.
101-18120, 18201-18220, 18301-18320, 18401-184
20 corresponds one-to-one with ALU 2911 to 2944, respectively.

The ALU connection switch 2185 is the same as the ALU connection switch 2175 in the switch 2017.
Switching control is performed via 2055. Then, each register file port selection switch and various ALU 2911 to 291
4, 2921 ~ 2928, 2931 ~ 2934, 2941 ~ 2944, connect the required ALU to register file 2081-2
084 is connected to the ALU necessary to execute the instruction.

As described above, in the second embodiment, ALU 2911-2
914, 2921 to 2928, 2931 to 2934, 2941 to 944 are fixed to each program and connected to the decoder.

However, as in the first embodiment, a method is also conceivable in which the ALU is determined and connected at the time of executing an instruction of each program without fixing the ALU to the program.

 Hereinafter, this case will be described.

In this case, at the time of instruction output, the dynamic schedulers 2041 to 2044 provide a program number indicating which program belongs to each instruction and an A indicating which type of ALU is used.
Add LU number.

In the case of this system, a field indicating the required number of ALUs is not required in the system control instruction as in the first embodiment.

Further, the ALU assignment control unit 2572 and the switch control unit 2583 are not required in the configuration control unit 2050.

Also, within the switches 2017 and 2018, the ALU selection unit 170
Instead of 1-1704 and 1801-1804, switch control units 2176 and 2186 are introduced, and switches 2017a and 2018a are provided.

FIG. 24 shows the configuration of the switch 2017a. In the figure, 2175
Is an ALU connection switch, and 2176 is a switch control unit.

4121-4128, 4221-4228, 4321-4328, 4421-4428
Are input lines from the dynamic schedulers 2041 to 2044, respectively.

Each input line has a decoded instruction, program number,
ALU number flows.

The decoded instruction and the program number are 41212-4
1282, 42212 to 42282, 43212 to 43282, and 44212 to 44282 are input to the ALU connection switch 2175 through signal lines, and the ALU number is
41 211-41281, 42 211- 42281, 43 211- 43281, 44 211-4
The signal is input to the switch control unit 2176 via the signal line 4281.

Output lines 2211-2214, 2222-1228, 2231-2234, 2241-
2244 is ALU 2911-2914, 2921-2928, 2931-2, respectively
Connected to 934, 2941-2944.

Reference numeral 2177 denotes a control signal line for the switch control unit 2176 to control the ALU connection switch 2175.

 Next, the operation of the switch 2017 will be described.

FIG. 25 is a flowchart showing the operation of the ALU connection switch 2175. The signal lines 41111 to 44281 give the switch control unit 2176 an ALU number required to execute each instruction.

In the switch control unit 2176, signal lines 41211 to 44281
If the ALU number indicated by is 1 (L / S), output line 2211
2-22 for IALU, 221-2228 for 3
(FADD) is 2231 to 2234, whereas 4 (FMUL) is 22
Signal lines 41212 to 44282 are connected to 41 to 2244.

FIG. 26 shows a configuration diagram of the switch 2018a. Reference numeral 2185 denotes an ALU connection switch, and 2186 denotes a switch control unit.

2711 to 2714 are input / output lines from each L / S to the switch 2018, of which 7111 to 7141 are signal lines for sending a program number and a connection request from each L / S to the switch control unit 2186, and 7112 to 7142 are for control. It is a signal line + 4 byte width input / output line. Similarly, 2721 to 2744 switch from IALU, FADD, FMUL
Input / output lines to 2018a, of which 7211-7441 are each A
2721a to 2744a and 2721b to 2744b are control signal lines + 4 byte width output lines, and 2721c to 2744c are control signal lines + 4 byte width input lines. 8101-8124, 8201-82
Reference numerals 24, 8301 to 8324, and 8401 to 8424 are input / output lines connected to the ports of the multiport register files 2081, 2082, 2083, and 2084, respectively.

2187 is a control signal line for the switch control unit 2186 to control the ALU connection switch 2185.

 Next, the operation of the switch 2018a will be described.

FIG. 27 is a flowchart showing the operation of the ALU connection switch 2185.

The signal lines 7111 to 7441 enable the switch control unit 21
The program number and connection request are transmitted to 86 from each ALU.

In the switch control unit 2186, based on the program number and the connection request obtained from the signal lines 7111 to 7441, if the program number is 1, the input / output lines 8101 to 8124 are provided; if the program number is 2, the input / output lines 8201 to 8244 are provided. If 3, input / output line 8301 ~
If 8324, 4 signal lines are connected to the input / output lines 8401 to 8424 by the number indicated by the connection request.

Note that the number of signal lines shown here is one for a READ / WRITE request for L / S and a READ request for other instruction execution units, as in the first embodiment. Two for the WRITE request and one for the WRITE request.

As described above, according to the first and second embodiments of the present invention, a multiprocessor configuration in which a sequential structure is changed in a data processing device according to the parallelism of a program to be processed is realized. By compensating the number of instructions that can be processed simultaneously in the device by a plurality of programs, the operating rate of the data processing device is improved, and the hardware performance can be fully utilized.

That is, a superscalar processor or VLIW
On a computer, a multi-processor configuration in which the structure is dynamically changed according to the parallelism of the program to be processed is realized, and the number of instructions that can be processed simultaneously is increased by a plurality of programs, so that the parallel processing mechanism in the data processing device is realized. Operation rate can be improved.

Also, there is no need to force the compiler to match the fixed degree of parallelism on the hardware. It is sufficient to create a multi-instruction processing object file according to the degree of parallelism of each program, reducing the burden on the compiler. Can be.

Furthermore, by sharing various ALU resources, resources can be saved and processing can be speeded up by introducing a high-speed dedicated arithmetic unit.

Also, in a system configuration based on superscalar, even if the number of instructions that can be processed simultaneously in the processor increases or decreases, as long as the same architecture is maintained,
Software compatibility can be maintained.

〔The invention's effect〕

As described above, according to the present invention, since instructions that can be processed simultaneously are fetched from a plurality of programs and are simultaneously executed, the plurality of programs can be executed quickly and efficiently.

Further, in this data processing device, by sharing the arithmetic unit for executing a plurality of programs, the versatility of the pipeline can be maintained without increasing the amount of hardware so much.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a data processing apparatus according to a first embodiment of the present invention, FIG. 2 is an explanatory diagram showing a configuration of a program instruction sequence, and FIG. 3 shows a configuration of a variable program counter. FIG. 4 is a block diagram showing the configuration of a multiple program instruction sequence fetch control device, FIG. 5 is a block diagram showing the configuration of a multiple program instruction sequence control device, FIG.
FIG. 7 is a block diagram showing the configuration of the scheduling control device, FIG. 7 is an explanatory diagram showing the operation of the switches and the priorities of the programs, FIG. 8 is an explanatory diagram showing the operation of the units in the scheduling control device, and FIG. Flow chart showing the operation algorithm of the unit in the scheduling control device, FIG. 10 is a flowchart showing the switch matrix network control algorithm of the switch control device,
FIG. 11 is a flowchart showing an operation algorithm of a program number supply unit, FIG. 12 is a block diagram showing a configuration of an instruction execution unit connection device, FIG. 13 is a flowchart showing a switch matrix network control algorithm of a switch control device, FIG. FIG. 14 is a block diagram showing the configuration of the register file connection device, FIG. 15 is a flowchart showing the switch matrix network control algorithm of the switch control device, and FIG. 16 is the entire data processing device according to the second embodiment of the present invention. FIG. 17 is a block diagram showing the configuration of a program instruction, FIG. 18 is an explanatory diagram showing the configuration of a variable program counter, FIG. 19 is a block diagram showing the configuration of a configuration control unit, FIG. Is a flowchart showing the operation algorithm of the multiple program control unit,
FIG. 21 is a flowchart showing the operation algorithm of the ALU assignment control unit, and FIG. 22 is a dynamic scheduler and AL.
FIG. 23 is a block diagram illustrating a configuration of a switch connecting the ULU, FIG. 23 is a block diagram illustrating a configuration of a switch connecting the ALU and the multi-port register file, and FIG. 24 is another configuration of a switch connecting the dynamic scheduler and the ALU. FIG. 25 is a dynamic scheduler and ALU in another configuration.
26 is a flowchart showing an operation algorithm of a switch for connecting the ALU, FIG. 26 is a block diagram showing another configuration of the switch for connecting the ALU and the multiport register file, and FIG.
The figure is a flowchart showing an operation algorithm of a switch for connecting an ALU and a multi-port register file in another configuration. 15 …… Multi-program instruction sequence fetch control device, 30 ……
Scheduling controller, 45: Program number supply unit, 69: Instruction execution unit connection device, 70: Multiport data cache memory, 75: Register file connection device, 81 to 84: Multiport register file, 101: … Multi-port instruction cache memory, 151, 691, 751, 9011, 9012… Switch matrix network, 152… Multiple program controllers, 15
3, 692, 7522, 90 ... Switch control device, 601-608 ...
Instruction decoder, 1021 to 1024 ... Variable program counter, 1701 to 1704 to ALU selection switch, 1801 to 1804 ... Port selection switch, 2015 to 2018 ... Switch circuit, 2041
2044 ... dynamic scheduler, 2050 ... configuration control unit, 2059 ... ... inter-program scheduling unit,
2070 …… Multi-port data cache memory, 2081 ～
2084: Multi-port register file, 2101: Multi-port instruction cache memory, 2175,
2185 ALU connection switch, 2186 Switch control unit, 2571 Multiple program control unit, 2572
ALU assignment control unit, 2581, 2582, 2583, 2176, 2
601-2608 ...... Instruction decoder, 2911-2914, 2921-292
8, 2931 to 2334, 2941 to 2944 ... Calculator, 21021 to 21024
... Variable program counter.

Continuation of front page (72) Inventor Yoshiki Kobayashi 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-63-254530 (JP, A) Morihiro Kuga (3 outside) Performance evaluation of super scalar “Shinkaze” based on SIMP (single instruction flow / multiple pipeline) ”, Parallel Processing Symposium JSPP '90, (May 1990) 337-344 (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 9/38

Claims (9)

(57) [Claims] 1. A means for extracting a plurality of instructions which can be executed in parallel from a plurality of programs, a plurality of arithmetic units which are shared by the plurality of programs and which can be operated in parallel; Means for distributing to a plurality of arithmetic units based on parallelism information indicating the number of instructions that can be executed in parallel in each program. 2. A memory for storing a plurality of programs, and an instruction sequence including one or more instructions that can be executed in parallel is stored in the memory based on parallelism information indicating the number of instructions that can be executed in parallel in each program. An instruction sequence readout unit that takes out in parallel from each of the plurality of programs, a plurality of decoders that operate in parallel, and a plurality of instructions that constitute a plurality of instruction sequences that the instruction sequence readout unit takes out in parallel. A distribution unit that distributes the instructions to the plurality of decoders based on parallel degree information indicating the number of instructions that can be executed in parallel in each program; a plurality of types of arithmetic units that execute the decoded instructions in parallel; Arithmetic unit connecting means for connecting the decoder and the plurality of arithmetic units according to the instruction type decoded by each decoder; and each program to which instructions to be executed in parallel belong A plurality of register files provided correspondingly, and a register for connecting the plurality of arithmetic units and the plurality of register files in accordance with a program to which an instruction executed by each arithmetic unit in response to a connection request from the arithmetic unit A data processing device comprising: file connection means. 3. A memory for storing a plurality of programs, and an instruction sequence including one or more instructions that can be executed in parallel is stored in the memory based on parallelism information indicating the number of instructions that can be executed in parallel in each program. An instruction sequence readout unit that takes out in parallel from each of the plurality of programs, a plurality of decoders that operate in parallel, and a plurality of instructions that constitute a plurality of instruction sequences that the instruction sequence readout unit takes out in parallel. Distribution means for distributing to the plurality of decoders based on parallelism information indicating the number of instructions that can be executed in parallel for each program; and a plurality of decoders provided for the programs to be executed in parallel and decoded by the plurality of decoders. A plurality of dynamic scheduling means for controlling the execution of instructions by analyzing the dependencies between the instructions in each program of the plurality of instructions; A dynamic scheduling means for connecting the program and a plurality of dynamic scheduling means based on parallelism information indicating the number of instructions which can be executed in parallel in each program; and a plurality of means for executing the decoded instructions in parallel. A plurality of types of arithmetic units; a second arithmetic unit connection unit that connects the plurality of dynamic scheduling units and the plurality of arithmetic units, respectively, according to an instruction type of an instruction scheduled by the dynamic scheduling unit; A plurality of register files provided corresponding to each program to which instructions to be executed in parallel belong, and each of the plurality of arithmetic units and the plurality of register files are executed by each of the arithmetic units in response to a connection request from the arithmetic unit. A data processing device comprising: register file connection means for connecting according to a program to which an instruction belongs. 4. The data processing device according to claim 2, further comprising: a unit for assigning a program number for identifying a program to which the instruction belongs to the instruction decoded by the plurality of decoders, A program number assigned to an instruction to be executed is added to a connection request, and the register file connection means connects the arithmetic unit and the register file according to the connection request and the added program number. Processing equipment. 5. The data processing apparatus according to claim 2, wherein the distribution means stores the program in a case where the number of instructions executable in parallel extracted from a plurality of programs is larger than the number of decoders provided. A data processing device comprising priority control means for performing priority control and distributing to a plurality of decoders in units. 6. The data processing device according to claim 2, wherein the plurality of instructions decoded by the plurality of decoders in parallel are executed in a program unit with priority control for each type of arithmetic unit. Characteristic data processing device. 7. The data processing apparatus according to claim 1, wherein the parallelism information indicating the number of instructions that can be executed in parallel of each program is obtained from a system control instruction included in each program. A data processing device characterized by acquiring. 8. The data processing apparatus according to claim 7, wherein said instruction sequence reading means is provided in correspondence with a plurality of programs to be executed in parallel, and in accordance with a system control instruction of a corresponding program.
A plurality of programs each capable of generating a count unit width, each of which sequentially generates a head read address of an instruction sequence composed of the instructions that can be executed in parallel and the number of read instructions that is the number of instructions that can be executed in parallel. A data processing device, being a counter. 9. The data processing device according to claim 7, wherein the system control command also includes information on the number of arithmetic units required by a program, and the connection is performed in accordance with the system control command. A data processing apparatus comprising configuration control means for integrally controlling connection of means.