JPH01195581A - Image data processing system - Google Patents

Abstract

PURPOSE:To perform the processing and editing of image data and the transfer simultaneously at a high speed by providing a display memory, an editing process memory, a file device, an image data transfer control means, etc. CONSTITUTION:Image data in a file device 700 is sent to a compressing/ expanding circuit 900 for image compressed codes through a high-speed bus 1,000 for image transfer and expanded, and then transferred to a transfer control ler 800. The controller 800 inputs the data as one operand data and also generates an address for rectangular area transfer for the editing process mem ory 300 and an address for rectangular area transfer for the display memory 400. Then data from the memories 300 and 400 are inputted as different data and processed logically, and then outputted to corresponding ports, so that the data are displayed on a CRT 500 and also stored in the device 700. Conse quently, the processing and editing, and transfer of image data which are gener ated frequently are carried out simultaneously at a high speed.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of an image data processing system, an object of the present invention is to provide an image data processing system that can transfer image data at high speed and in a form suitable for display processing. An image of a display memory, an editing memory for editing, a file device, a file buffer memory for transfer control, and a connection between the file device and the file buffer memory. Bidirectional data transfer can be performed between the transfer dedicated bus and the image transfer dedicated bus, [1] Bidirectional data transfer can be performed between the processing memory and the display memory. and an image data transfer control means capable of performing bidirectional data transfer, the image data transfer control means being configured to be able to independently generate an address for the editing memory and an address for the display memory. .

[Industrial application field]

The present invention relates to an image data processing system that handles a large amount of image data and processes the image data.

[Conventional technology]

FIG. 5 is a diagram showing a conventional image data processing system. In the figure, 100 is a central processing unit, 200
is control memory, 300 is editing memory,
400 is a display memory, 500 is a display device, 6
00 indicates a file buffer memory, and 700 indicates a file device.

When displaying image data in the file device 700, image data of a certain size is stored in the file buffer memory 600. Buffer memory 60
The image data of 0 is sent to the display memory 400 or the editing memory 300. Control memory 200 stores various programs. The editing memory 300 is used when editing image data. The image data in display memory 400 is sent to display device 500 and displayed.

[Problem that the invention seeks to solve]

Conventionally, the configuration was as shown in Figure 5, so the image
When transferring and displaying data in a rectangular area, the file buffer memory 600 and the display memory 400 are arranged in the same address space, and the rectangular area is transferred between them. Therefore, from the file device 700, the buffer
Every time data is transferred to the memory 600 or from the buffer memory 600 to the display memory 400, editing processing of display data is interrupted, and high-speed image data transfer and high-speed image data editing processing are performed. They couldn't do it at the same time.

The present invention was created in view of this point, and an object of the present invention is to provide an image data processing system that can transfer image data at high speed and in a format suitable for display processing. It is said that

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention. The image data processing system of the present invention includes a display memory 400 composed of a bit map memory, and a display memory 400 for editing and processing the bit map data composed of the bit map memory. A memory 300, a file device 700 for storing bit map data, a file buffer memory 600 for transfer control, a file device 700 and a file buffer memory 600
Bidirectional data transfer can be performed between the image transfer dedicated bus 1000 that connects the image transfer dedicated bus 1000, and bidirectional data transfer can be performed between the image transfer dedicated bus 1000 and the editing processing memory 300. Image data transfer control means 800 and 900 capable of performing bidirectional data transfer with the display memory 400 are provided.

〔Example〕

FIG. 2 is a block diagram of one embodiment of the present invention.

In the figure, 800 represents a transfer control device, and 900 represents an image compression code compression/expansion circuit.

Note that the same reference numerals as in FIG. 5 indicate the same parts.

As the file device 700, a large capacity storage device suitable for storing image data, such as an optical disk or a magnetic disk device, can be used.

The data stored in the file device 700 is code data compressed using a compression code in order to improve the efficiency of the storage device.

The image transfer dedicated bus 1000 is a high-speed code/data bus suitable for transferring large amounts of image data.
It's a bus. For example, several nodes are arranged on a ring-shaped bus that performs synchronous transfer, and data and tokens indicating the validity of the data are received and passed between each node to perform high-speed transfer.

The code requirement 11 for image compression code 900 is for decompressing the data from the image transfer dedicated bus 1000 and converting the data from the transfer control device 800 into a compression code. For encoding, M” R method, MR method, M
H method etc. can be used.

The transfer control device 800 transfers data between the image compression code compression/expansion circuit 900 and the jW collection processing memory 3001 display memo 1 month OOO, as well as the image compression code compression/expansion circuit 900 and the [collection processing memory 3001]. A logical operation with three operands specified is performed on the memory 3001 and the display memory 400. At this time, the transfer control device 800 can independently and simultaneously generate a transfer area address for the display memory 400 and a transfer area address for the editing memory 300.

FIG. 3 is a block diagram of an example of a transfer control device. In the figure, 801 is a source operand register;
02 is a mask operand register, 803 is a destination operand register, 804 is a logical operator, 805 is a BM address calculation circuit, 806 is a VM address calculation circuit, 807 is a controller, and 808 and 813 are gates, respectively. There is.

BM address calculation circuit 805 is memory 300 for editing processing.
VM address calculation circuit 80
6 generates an address for the display memory 400.

The BM address calculation circuit 805 is provided with a register for setting a start address and memory width, and generates a rectangular area transfer address according to a command from a controller 807. The same applies to the VM address calculation circuit 806.

Data sent from the code expansion path 900 for image compression code is latched into any one of registers 801, 802, and 803. The same applies to data sent from the editing memory 300 and the display memory 400. The output of the logical operator 804 is sent to the editing memory 3001, the display memory 400. It is sent to one of the image compression code compression/expansion circuits 900. One operand per port of the transfer control device 800
If data is specified, different operand data can be read from multiple ports, speeding up arithmetic processing.

Next, an example of the operation of the image data processing system having the above characteristics will be explained. Image data from the file device 700 is sent to the image compression code compression/decompression circuit 900 via a high-speed image transfer dedicated bus. This image data is decompressed by the image compression code compression/decompression circuit 900 and then transferred to the transfer control device 800. The transfer control device 800 receives the data from the image compression code compression/decompression circuit 900. 1
At the same time, it generates an address for transferring a rectangular area to the 1m processing memory 300 and an address for transferring a rectangular area to the display memo January 00, and inputs data from the editing processing memory 300 and the display memory 400. The data from is input as another operand data and logical operation processing is performed. The calculation results can be output to the VM boat and displayed on the display device 500, or output to the C/E boat and stored in the file device 700. FIG. 4 shows an example of a logical operation using three operands.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in an image data processing system, it is possible to simultaneously perform processing, editing, geography, and transfer processing of image data, which frequently occur, at high speed.

[Brief Description of the Drawings] Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of an example of a transfer control device, and Fig. 4 is a block diagram of an example of a transfer control device. Figure 5 showing examples of logical operations on operands.
The figure shows a conventional image data processing system. 100...Central processing unit, 200...Control memory, 300...Editing memory, 400...
・Display memory, 500...Display device, 60
0... File buffer memory, 700...
File mounting W, 800...Transfer control device, 801...
- Source operand register, 802... Mask operand register, 803... Destination operand register, 804... Logical operator, 805... BM address operation circuit, 806... V
M address calculation circuit, 807... controller, 80
8 to 813...gate, 900...compression/expansion circuit for image compression code.

Claims (3)

[Claims] (1) A display memory (400) consisting of a bit map memory, and an editing memory (400) for editing and processing bit map data consisting of a bit map memory.
300), a file device (700) for storing bit map data, and a file buffer memory (600) for transfer control.
), an image transfer dedicated bus that connects the file device (700) and the file buffer memory (600), and bidirectional data transfer between the image transfer dedicated bus, which is suitable for editing and processing. Bidirectional data transfer can be performed between the memory (300) and the display memory (40).
image data transfer control means (800, 900) capable of performing bidirectional data transfer between the image data transfer control means (800 and 900);
An image data processing system characterized in that it is configured to be able to independently generate an address for an editing memory (300) and an address for a display memory (400). (2) Image data transfer control means (800, 900
) transfers data from the image transfer dedicated bus to the source operand register (801) and mask operand register (801).
It can be set in either the register (802) or the destination operand register (803), and data from the editing memory (300) can be set as the source.
It can be set in any of the operand register (801), mask operand register (802), or destination operand register (803), and data from the display memory (400) can be set in the source operand register. (801), mask operand
It can be set in either the register (802) or the destination operand register (803), as well as the output data of the source operand register (801) or the mask operand register (802).
It has a logical operator (804) that performs logical operations on the output data of the output data of the destination operand register (803), and the output of the logical operator (804) is transferred to the image transfer dedicated bus and the editing memory (803). 300) and a display memory (400). (3) Image data transfer control means (800, 900
(1) or (2) characterized in that the image compression code compression/decompression circuit (900) decompresses data from the image transfer dedicated bus and compresses data to the image transfer dedicated bus. 2) The image data processing system described.