JPH07105347A - Image data high-speed processing unit - Google Patents

Abstract

PURPOSE:To attain high-speed processing for data expansion, rotation and movement by preparing plural cross call memories in the image data high-speed processing unit and executing three sets of processing simultaneously in parallel such as writing data already expanded into an area of the cross call memory, moving the data to a bit map memory from other area, reading and rotating the expanded data from an area in other cross call memory and writing the data to other area. CONSTITUTION:An expansion circuit 5 writes expansion data to an area in a cross call memory 7 via an image bus 9 and a movement element 8 reads data from other area in the cross call memory 7 and moves the data to a bit map memory 10 via the image bus 9 and connects other cross call memory 7 to a system bus 1 and a rotating element 3 reads and rotates data from an area and writes the data to other area. The three operations are executed simultaneously in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data high-speed processing apparatus for expanding / rotating image data and moving it to a bit map memory.

[0002]

2. Description of the Related Art A conventional image data processing apparatus, for example, an apparatus having a configuration as shown in FIG. 5, transfers image data to a compression / expansion circuit 25 via a system bus 21 as a block of a plurality of lines and expands it. , Image bus 2
Write to the cross call memory 27 via 9. After that, the data on the cross call memory 27 is moved to the bitmap memory 30 via the image bus 29 by the moving / rotating element 28. When the data is moved to the bit map memory 30, it takes about 8 times as much time to rotate the data as compared to the case where the data does not rotate. For example, when the cross call memory 27 is divided into the upper half and the lower half for use, the image data compression / expansion circuit 2 is used for the upper half.
The decompressed data from 5 is written, and the decompressed data already written in the lower half is moved to the bitmap memory 30. At this time, the compression that expands the image data
Since the time required for the decompression circuit 25 to decompress the upper half block of the cross call memory 27 is longer for moving the data to the bitmap memory 30, the latter process is waited for. Thereafter, the compression / expansion circuit 25 writes the expanded data in the lower half, and moves the expanded data in the upper half to the bitmap data 30. By repeating this, the image data is written in the bitmap memory 30 and displayed.

[0003]

As described above, even if the compression / expansion circuit 25 finishes decompressing one block of data and finishes writing the data in the cross call memory 27, the bit map is removed from the cross call memory 27. Memory 3
You have to wait for the data to move to zero. In particular, when data is rotated / moved from the cross call memory 27 to the bit map memory 30, there is a problem that the waiting time becomes longer and the whole process also takes time. Further, even if two cross call memories 27 are provided, only one of them can be used, and further, even if the system bus 21 and the image bus 29 are empty, there is a problem that processing cannot be performed in parallel. .

The present invention solves these problems.
Plural, for example, two cross call memories are prepared, and the decompressed data obtained by decompressing the data is written in one area (eg, half) of one cross call memory and moved from another area (eg, other half) to the bitmap memory. At the same time, the decompressed data is read from a certain area (for example, half) of the other cross-call memory 7, rotated, and written in the other area (for example, the other half). -The purpose is to speed up the moving process.

[0005]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, a decompression circuit 5 decompresses data from the system bus 1 and writes it in the cross call memory 7 via the image bus 9.

The cross call memory 7 is the system bus 1
And one of the image buses 9 is switched and connected. The rotation element 3 is connected to the system bus 1, the cross call memory 7 is connected to the system bus 1, and the data read from the cross call memory 7 is rotated and written in different areas of the same cross call memory 7. It is a thing.

The moving element 8 is connected to the image bus 9, the cross call memory 7 is connected to the image bus 9, and the data read from the cross call memory 7 is moved to the bit map memory 10 in bit correspondence. It is something to write.

The switching register 6 holds switching information for switching and connecting to either the system bus 1 or the image bus 9 for each of the plurality of cross call memories 7.

[0009]

As shown in FIG. 1, the present invention writes the decompressed data decompressed from the compressed data received by the decompression circuit 5 into a certain area of one cross call memory 7 through the image bus 9 and moves the moving element 8 as well. Reads out the data (expanded / rotated) from the other area of the same cross call memory 7 and sends it to the bit map memory 1 via the image bus 9.
Writing in the form of moving to 0, and the rotating element 7 connects another cross-call memory 7 to the system bus 1, reads data, rotates and writes in another area of the same cross-call memory 7. The three operations are executed simultaneously in parallel.

In these cases, switching information is set in the switching register 6 to switch the cross call memory 7 to either the system bus 1 or the image bus 9 for connection.

Therefore, a plurality of cross call memories 7, for example, two cross call memories 7 are prepared, and the decompressed data obtained by decompressing the data is written in one half of the cross call memory 7 and the bit map memory 1 from the other half.
High-speed data decompression / rotation / movement processing by moving to 0 and reading the decompressed data from the other half of the cross-call memory 7 and rotating and writing to the other half simultaneously in parallel. Can be realized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 2 shows a block diagram of an embodiment of the present invention.
In FIG. 2, the system bus 1 is a main buffer 2,
It is a bus for connecting the CPU 4, the rotation element 3 and the like to mutually exchange data.

The main buffer 2 stores various types of data, and here stores compressed data. The compressed data is read from the main buffer 2 and input to the compression / expansion circuit 51 to be expanded.

The rotating element 3 reads the data (decompressed data) from the upper half and instructs it by setting the connection information in the switching register 6 and connecting one of the cross call memories 7 to the system bus 1. After the rotation is done, write in the lower half.

The CPU 4 controls the entire system. The compression / expansion circuit 51 expands compressed data to generate expanded data.

The switch register 6 sets connection information for switching the plurality of cross call memories 7 to either the system bus 1 or the image memory 9.

The cross call memory 7 writes decompressed data and rotated data. The moving element 8 writes the data read from the cross call memory 7 to the bit map memory 10 via the image bus 9 in a bit-corresponding manner and moves the data.

The image bus 9 includes a compression / expansion circuit 51,
The bus is connected to the cross-call memory 7, the moving element 8 and the bit map memory 10 to exchange data.

The bit map memory 10 includes a moving element 8
Is for reading from the cross call memory 7, writing data corresponding to bits, and displaying. First,
The states 1, 2, 3, 4, and 5, which are the states of the two cross call memories 7 in FIG. 2, will be described with reference to FIG. here,
The two cross call memories 7 in FIG. 2 are a cross call memory (a) and a cross call memory (b), and are divided into an upper half and a lower half, respectively.

State 1: A state in which both the cross call memory (a) and the cross call memory (b) have been cleared (or the state where the cross call memory 10 has been moved to the bitmap memory 10). State 2: The compression / decompression circuit 51 writes the decompressed data obtained by decompressing the compressed data into the upper half of the cross call memory (a) via the image bus 9.

State 3: The rotating element 3 transmits the decompressed data from the upper half of the cross call memory (a) to the system bus 1.
After the data is read out and rotated through, the rotation processing for writing back to the lower half of the cross call memory (a) is performed. In parallel, the compression / decompression circuit 51 writes the decompressed data obtained by decompressing the compressed data into the upper half of the cross call memory (b) via the image bus 9.

State 4: Data for which the moving element 8 has been rotated is transferred from the lower half of the cross call memory (a) to the image bus 9
The compressed / decompressed circuit 51 writes the decompressed data decompressed by the compression / decompression circuit 51 to the upper half of the cross call memory (a) via the image bus 9. In parallel, the rotation element 3 reads the decompressed data from the upper half of the cross call memory (b) via the system bus 1 and rotates, and then writes it back to the lower half of the cross call memory (b). To do.

State 5: In the same manner by exchanging the state 4, the cross call memory (a) and the cross call memory (b), the data in which the moving element 8 has been rotated is imaged from the lower half of the cross call memory (b). The data is read to the bus 9 and written to the bit map memory 10, and the decompressed data obtained by decompressing the compressed data by the compression / decompression circuit 51 is written to the upper half of the cross call memory (b) via the image bus 9. In parallel, the rotating element 3 transfers the decompressed data from the upper half of the cross call memory (a) to the system bus 1.
After the data is read out and rotated through, the rotation processing for writing back to the lower half of the cross call memory (a) is performed.

The following states 4 and 5 are alternately repeated, and the following three processes (1) to (3) are simultaneously executed in parallel, so that image data can be expanded, rotated and moved at high speed. Becomes

(1) The moving element 8 reads the decompressed / rotated data from the lower half of the cross call memory (a) or (b) and writes it in the bitmap memory 10 via the image bus 9.

(2) The compression / decompression circuit 51 decompresses the compressed data and writes the decompressed data into the upper half of the cross call memory (a) or (b) via the image bus 9.

(3) The rotating element 3 reads the decompressed data from the upper half of the cross-call memory (a) or (b) via the system bus 1 and rotates, and then the same cross-call memory via the system bus 1. Write in the lower half of (a) or (b).

Next, the operation of the configuration of FIG. 2 will be described in detail with reference to FIG. In the figure, states 1, 2, 3, 4, and 5 are shown in FIG.
States 1, 2, 3, 4, and 5, respectively. In FIG. 4, in S1, the compression / expansion circuit 5 receives an expansion instruction from the CPU 4.

In step S2, the data is expanded. This generates decompressed data which is decompressed by the compression / decompression circuit 5 which receives the compressed data. Then, the data is written in the upper half of the cross call memory (a), and the state 2 of FIG. 3 is obtained in S4.

In step S3, it is determined whether the decompressed data has been written in the upper half of the cross call memory (a). Yes
In this case, since the writing is completed, the cross call memory (a) is switched to the system bus connection in S5, and S
At 5 ', the cross call memory (b) is switched to the image bus connection.

By the above processing, the state 1 in FIG. 3 changes to the state 2. In S6, the rotation element 3 performs a rotation process, that is, after reading the decompressed data from the upper half of the cross call memory (a) through the system bus 1 and rotating, the cross call memory (a) is passed through the system bus 1. Write in the bottom half. As a result, the state becomes the state 3 in FIG. 3 in S7.

In S8, the compression / expansion circuit 51 performs S2 and S3.
Similarly, the decompressed data is written in the upper half of the cross call memory (b). As a result, in S7 ', as shown in FIG.
It becomes the state 3 of.

The cross call memory (a) is switched to the image bus connection in S9, and the cross call memory (b) is switched to the system bus connection in S9 '. With the above processing, the state 2 in FIG. 3 changes to the state 3.

In S10, the moving element 8 writes the expanded / rotated data from the lower half of the cross call memory (a) to the bitmap memory 10 via the image bus 9 and moves. As a result, the state 4 of FIG. 3 is obtained in S11.

In S12, the compression / expansion circuit 51 performs S2, S
In the same manner as in 3, the decompressed data is written in the upper half of the cross call memory (a). As a result, the state 4 of FIG. 3 is obtained in S11 ′.

In S13, the rotation element 3 performs a rotation process, that is, after reading the decompressed data from the upper half of the cross call memory (b) through the system bus 1 and rotating, the cross call memory is transmitted through the system bus 1. Write in the lower half of (b). As a result, the state 4 of FIG. 3 is obtained in S11 ″.

The cross call memory (a) is switched to the system bus connection in S14, and the cross call memory (b) is switched to the image bus connection in S14 '. By the above process, the state 3 is changed to the state 4 in FIG.

In S15, the moving element 8 writes the expanded / rotated data from the lower half of the cross call memory (b) to the bitmap memory 10 via the image bus 9 and moves. As a result, the state becomes the state 5 in FIG. 3 in S16.

In S17, the compression / expansion circuit 51 performs S2, S
In the same manner as in 3, the decompressed data is written in the upper half of the cross call memory (b). As a result, the state 5 of FIG. 3 is obtained in S16 ′.

In S18, the rotation element 3 performs the rotation process, that is, after reading the decompressed data from the upper half of the cross call memory (a) through the system bus 1 and rotating, the cross call memory is transmitted through the system bus 1. Write in the lower half of (a). As a result, the state 5 of FIG. 3 is obtained in S16 ″.

The cross call memory (a) is switched to the image bus connection in S19, and the cross call memory (b) is switched to the system bus connection in S19 '. With the above processing, the state changes from the state 4 in FIG. 3 to the state 5. Process 1 below
S10 to S14 'and S15 to S19' of process 2
Are alternately repeated, and the three processes (1), (2), and (3) described in FIG. 3 are simultaneously executed in parallel.

[0043]

As described above, according to the present invention,
A plurality of cross call memories 7, for example, two cross call memories 7 are prepared, and the decompressed data obtained by decompressing the data is an area where one cross call memory 7 exists (for example, half).
To and from the other area (eg, the other half) to the bitmap memory 10, while reading the decompressed data from a certain area (eg, the half) of the other cross-call memory 7 and rotating the other area (eg, the other area). Since the configuration is such that three processes of writing to the other half) are executed in parallel at the same time, it is possible to speed up by parallel processing of data decompression / rotation / movement processing.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a state transition diagram of the cross call memory of the present invention.

FIG. 4 is an explanatory diagram of the operation of the present invention.

FIG. 5 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1: System Bus 2: Main Buffer 3: Rotation Element 4: CPU 5: Decompression Circuit 51: Compression / Expansion Circuit 6: Switching Register 7: Cross Call Memory 8: Movement Element 9: Image Bus 10: Bitmap Memory

Claims (2)

[Claims] 1. A decompression circuit (5) for decompressing data transferred from a system bus (1) and writing it in a cross call memory (7) via an image bus (9), a system bus (1) and an image. A plurality of cross call memories (7) that are switched and connected to any of the buses (9) and the system bus (1), and the cross call memories (7) are connected to the system bus (1). The data read from the call memory (7) is connected to the rotating element (3) for rotating and writing the different data in the same cross call memory (7) and the image bus (9), and the cross call memory (7) is connected. ) Is connected to the image bus (9) to write the data read from the cross-call memory (7) into the bitmap memory (10). The decompression circuit (5) writes decompressed data to a certain area of one cross call memory (7) through the image bus (9), and moves the other element from the other area of the same cross call memory (7). 8) reads the data and writes it to the bit map memory (10) via the image bus (9), and connects another cross-call memory (7) to the system bus (1) to connect the rotating element (3). ) Reads data from a certain area, rotates it, and writes it in another area of the same cross-call memory (7), so that three operations are executed in parallel at the same time. apparatus. 2. A switching register (6) for holding switching information for switching and connecting to either the system bus (1) or the image bus (9) for each of the plurality of cross call memories (7). The switching register (6) is set with switching information to switch the cross call memory (7) to either the system bus (1) or the image bus (9) for connection. The described image data high-speed processing device.