JPS6312057A - Bus control system - Google Patents

Abstract

PURPOSE:To perform the data processing similar to a processor of the same system without reducing the processing speed by switching a data selecting signal and a data bus even if processors different in data arrangement system are connected to the same bus. CONSTITUTION:When trying to process data where the arrangement of upper data and lower data is different a processor 11 outputs an address selecting signal. An address control means 12 receives and stores this signal and sends the signal to selecting signal switching means 13 and 14 and a data switching means 17. Selecting signal switching means switch which selects upper data or lower data outputted from the processor, and upper data is converted to output the selecting signal, which selects lower data, to a bus 30 if the processor selects upper data. When lower data is read, an upper data bus 33 and a lower data bus 34 are switched by the data switching means 17 to read out lower data, which is read out from a memory, as upper data of the processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control system for a bus connecting processors with different arrangements of upper and lower data.

[Conventional technology]

As shown in FIG. 2, there are two methods for combining two 1-byte data to create 16-bit data and storing and arranging it in a memory.

Figure 2 (a) is big endian (B i gend
In this method, the upper 8 bits of 16-bit data are stored in the first address, and the lower 8 bits are stored in the next address. (Hereinafter, this method will be referred to as BE method 2.) Figure 2 (b) is called the Little endian method, and 1
Put the lower 8-bit data of 6-bit and 7-bit data in the first address,
This is a method in which the upper 8 bits of data are stored at the next address. (Hereinafter, this method will be referred to as LE method 2.) Which method is used depends on the processor used, and one system is usually unified to one or the other.

[Problem that the invention seeks to solve]

However, it is not uncommon for software to be developed separately for the two types of processor systems mentioned above, and after the software has been accumulated, a new system that combines the two systems becomes necessary. In this case, the data arrangement and storage methods are different, and it is necessary to unify them to one of the processor systems, making the software stored in the other system unusable. This wastes software, and to avoid this, it is also possible to combine the two and, when exchanging data, exchange upper and lower data within the processor. However, this method has the problem that the process of exchanging data is always included in the software processing step, which significantly slows down the processing time.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a bus control system that converts the upper and lower data using hardware in a bus that connects processors with different arrangements.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a bus control method in which processors having different addressing methods for upper byte and lower byte arrangement are connected to one bus. address control means for storing and controlling an address system using the address control means; selection signal switching means for receiving a signal from the address control means and switching between a selection signal for upper data and lower data from the processor; and a signal from the address control means. a data switching means for switching between an upper byte data bus and a lower byte data bus in response to a signal, and is configured to convert the arrangement of upper and lower data of data having different addressing systems. , It was adopted.

[Effect]

When the processor attempts to process data with different arrangements of upper and lower data, the processor outputs an address selection signal.

The address control means that receives this stores it and sends a signal to the selection signal switching means and the data switching means.

The selection signal switching means switches the selection signal for selecting either the upper data or the lower data output by the processor, and when the processor selects the upper data, it converts this and sends the selection signal for selecting the lower data to the bus. Output. Therefore, lower-order data such as memory is read out.

When the lower data is read out, the data switching means switches between the upper data bus and the lower data bus, and the lower data read from the memory is read out as upper data of the processor.

This makes it possible to convert and read data arrays from other memories and the like. The same applies when the processor writes to another memory or the like.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, 10 is a processor module, which includes a processor 11, and the processor 11 is a BE shown in FIG. 2(a).
method.

20 is a memory module, and data is stored in this memory in the LE format shown in FIG. 2(b).

The processor module 10 and the memory module 20 are connected by a bus 30, and an L2 type processor (not shown) is connected to the bus 30.

That is, the configuration is such that the BE processor module 10 reads data written to the memory module 20 from an LE processor (not shown).

Next, details of the configuration of the processor module 10 will be described. The processor 11 is a BE type processor as described above. 12 is an address control circuit, which uses 5WA when the processor 11 reads data in the LE format.
It receives the P command, stores it, and outputs its contents.

Reference numerals 13 and 14 designate selection signal switching circuits, and when reading a BE system signal, an upper data selection signal (*UoS) is output from line 18a of the processor 11 and passes through the selection signal switching circuit 13 as it is. , is output on line 31. However, when reading data in the LE system, the output signal from the address control circuit 2 enables the path shown by the solid line in the selection No. 13 switching circuit 14, and outputs it to the line 32 as a lower data selection signal (*LDS). Then, the lower data is read from the memory module 20.

On the other hand, 15 and 16 are pass buffers, and 17 is a data switching circuit. Normally, when reading BE method data, the upper byte data is read directly from the upper byte data bus 33 via the bus buffer 15.

However, when reading data in the LE format, data from the lower byte data bus 34 is switched to the upper byte data bus 33 by the data switching circuit 17 that receives a signal from the address control circuit 12, and the data from the lower byte data bus 34 is switched to the upper byte data bus 33.
The data is read as upper data through 9a.

Next, details of the memory module 20 will be described. In the figure, memories for 16 bits are shown as an upper byte memory 21 and a lower byte memory 22. 24 and 2
5 is a pass buffer, and internal pass lines 26a and 2
6b to an external upper byte data bus 33 and lower byte data bus 34. As mentioned above, data is written from an LE processor (not shown) and stored in the LE format. That is, as shown in FIG. 2(b), upper byte memory 21 stores upper data, and lower byte memory 22 stores lower data.

The bus 30 is a 16-bit data bus, and the upper data selection signal (0kUDS) line 31 is connected to this as a control signal.
and a lower data selection signal (*LDS) line 32. Note that when converting LE format data to BE format data as in this embodiment, data is transferred in byte units.

Next, I will talk about the operation. As mentioned previously, data is not stored in the memory module 20 in the E format, but the upper byte memory 21 stores upper data and the lower byte memory 22 stores lower data.

The processor 11 is a BE processor, and it is desired to read the upper data into the lower byte and the lower data into the upper byte. Therefore, the processor 11 first issues a S W A P command to the address control circuit 12 to prepare for reading data in the LE format. The address control circuit 12 stores this and outputs a signal to the selection signal switching circuits 13 and 14, and the selection signal switching circuits I3 and 14 control the path shown by the solid line to become valid. Further, the data switching circuit 17 and path buffers 15 and 16 receive signals from the address control circuit 12 and control the data in the upper byte data bus 33 to be output to line 19b and the data in the lower byte data bus 34 to line 19a. .

The processor 11 then sends the upper data selection signal (*UDS)
is output from line 18a and an attempt is made to read the higher-order data. This signal is output to the line 32 as a lower data selection signal (*LDS) by the selection signal switching circuit 14, and is applied to the bus buffer 25 of the memory module 20 so that the data (lower data) in the lower byte memory 22 is changed to the lower byte. Read out to data bus 3,1. This data is switched by the data switching circuit 17 and read into the processor 11 as upper data from the line 19a via the path buffer 15.

Next, the processor 11 outputs a lower data selection signal (*LDS) to the line 18b in order to read the lower data, which is converted by the selection signal switching circuit 13 into an upper data selection signal (*UDS) and output to the line 31. is applied to the path buffer 24 of the memory module 20, and causes the data in the upper byte memory 21, that is, the upper data, to be output to the upper byte data bus 33. This upper data is switched to the lower byte data bus by the data switching circuit 17 and read into the processor 11 as lower data from line 19t via the path buffer 16. In this manner, the processor 11 can convert and read the arrays of upper and lower data. Further, the same operation is repeated and the next data is read in sequence. Therefore, if the processor 11 first instructs to convert and read the data, there is no need to convert each data item, the data processing speed becomes faster, and the burden of software creation is reduced.

In the above embodiment, an example of reading by the processor 11 was shown, but writing can be performed in the same manner. or,
The bus was 16 bits, and each data was 8 bits.
Of course, this value can also be expanded to other values. Furthermore, the problem is not limited to the case where the devices are connected to the same bus, and a similar configuration can be used for external data input/output that is input/output from an external line.

〔Effect of the invention〕

As explained above, in the present invention, even when processors with different data arrangement methods are connected to the same bus, the data selection signal and the data bus are switched, so there is no reduction in processing speed. , data processing can be performed in the same way as processors of the same type, and the burden on software is also reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
FIG. 2(b) is a diagram showing the data arrangement method of the pig endian method; FIG. 2(b) is a diagram showing the data arrangement method of the true endian method. 10--Processor module 11--Processor 12--Address control circuit 13.14--Selection signal switching circuit 17--Data switching circuit 20--Memory module 30-- ...-Bus 31-----First-order byte data bus 32----
First lower height data bus, Figure 2

Claims (2)

[Claims] (1) In a bus control system in which processors having different address systems with different upper byte and lower byte arrangements are combined on one bus, address control is performed to store and control the address system in response to an address system selection signal from the processor. means, selection signal switching means for receiving a signal from the address control means to switch between a selection signal for upper data and lower data from the processor; and receiving a signal from the address control means for switching between an upper byte data bus and a lower byte data bus; 1. A bus control method, comprising: data switching means for switching buses, and configured to convert the arrangement of upper and lower data of data having different addressing systems. (2) The bus control method according to claim 1, wherein the byte data is 8 bits and the bus has a 16 bit configuration.