JPH0344886A - Fast-in fast-out memory constituting system - Google Patents

Abstract

PURPOSE:To constitute a memory with large capacity by informing a low-order device of it by a write mode flag that data to be read out exist in the memory. CONSTITUTION:When a write mode flag generating circuit F is turned to a reset state, for example, it shows that such a state is the write period of input data or the data are not stored. Reversely, when the write mode flag generating circuit F is in the reset state, it shows that the data to be read from a low-order device A are stored and the data can be read. When such a write mode flag (f) is '1', the low-order device A outputs a read signal for reading the data. In such a way, the data are alternatively written and read to a one-port RAM. Thus, the memory with the large capacity can be constituted by using the inexpensive RAM.

Description

[Detailed Description of the Invention] [Summary] Regarding a method of configuring a FIF○ memory using a RAM having one input/output port, the present invention aims to configure a large capacity FIF○ memory and has one input/output port. a memory, a write address register that stores a final write address to the memory, and a read address generation circuit that generates a read address of the memory based on an enable signal from a downstream device;
A comparator that compares the read address from this read address generation circuit with the final write address stored in the write address register, and a comparator that is reset by a first write signal when writing to the memory, and A write mode flag generating circuit outputs a write mode flag by setting the time by a second write signal and a control bit and resetting by a match signal from the comparator, and writing the access address of the memory by this write mode flag. A selector for switching between an address and a read address is provided, and the write mode flag is configured to notify the downstream device that data to be read exists in the memory.

[Industrial application field]

The present invention relates to a method of configuring a first-in first-out memory (hereinafter referred to as FIF○ memory) using a RAM having one input/output port.

[Conventional technology]

FIFO memories are widely used as data buffers, etc., but off-the-shelf FIFO memory elements have a relatively small capacity and are expensive.

[Problem to be solved by the invention]

The capacity of a 2-board RAM type FIF memory is, for example, about 512 words x 9 bits or 1 kiloword x 9 bits, and 64
If a capacity such as KWX32 bits is required, F
Since the capacity of the IF○ memory element is small as described above, a large number of memory elements are required, which requires a large mounting space, and since the memory element itself is originally expensive, the cost becomes enormous.

Also, if the transfer speed of data from the host to the FIFO memory is slower than the transfer speed between a pair of FIF○ memories, the transfer capacity from the input end FIF○ memory to the next stage FIF○ memory may not be sufficient. The problem was that it was not available.

The present invention uses relatively inexpensive RAM to create a large-capacity FIF.
○The purpose is to configure memory.

[Means to solve the problem]

As shown in the principle diagram of FIG. A read address generation circuit R that generates a read address n of the memory M, and a comparator C that compares the read address n from the read address generation circuit R with the final write address m stored in the write address register W. The write mode flag is reset by the first write signal when writing the memory, is set by the second write signal and the control bit when reading the memory, and is reset by the match signal from the comparator C. The data to be read into the memory M includes a write mode flag generation circuit F that outputs a write mode flag f, and a selector Sa that switches the access address of the memory M between a write address and a read address according to the write mode flag f. The downstream device A is notified of the existence of the write mode flag f using the write mode flag f.

[For production]

For example, when writing data from the host to the RAM, a first write signal is supplied from the host to reset the write mode flag generation circuit and set the output of the write mode flag f to "0".

Simultaneously with this write signal, a write address is supplied from the host and stored in the write address register W, and at the same time, this write address is supplied to one input terminal of the first selector Sa, which is switched by the write mode flag f. , from the output side of this selector Sa
This write address is supplied as the AM access address.Then, for example, the input data of the first word to be written to the RAM is written to the above write address via the second selector S (1), and the next When the write address increases by 1 during the period, the second word of manual data is written to the RAM in the same way as above, and the manual data is sequentially written to consecutive addresses from address 1 of this RAM until the end of the series of manual data. .

When the writing of the series of data sent from the host is completed in this way, the host sets the write mode flag generation circuit F using the second write signal and the control bit to set the write mode flag to "1". and switches the first selector Sa. At this time, the last address m to which input data was written is stored in the write address register W.

Reading from this RAM is started by sending a read signal when the downstream device A detects that the write mode flag generation circuit F is set and the write mode flag becomes "1" as described above. be done.

This read signal activates the read address generation circuit R, and at the same time switches the second selector Sd so that the data read from the RAM is output to a subsequent device etc. via the data bus, and furthermore, the data read from the RAM is outputted to a subsequent device etc. It is supplied to this RAM as a read enable signal to enable it.

Therefore, the stored data is read from the RAM in a first-in first-out order by the read address n sequentially increasing from 1 from the read address generation circuit R, and the data bus is transferred from the second selector Sd. After that, it is sent to a downstream device.

The address n from the read address generation circuit R is sent to one input terminal of a comparator C whose other input terminal is supplied with the write address stored in the write address register W, but the address n is not stored in this RAM. When all data in the write mode flag generation circuit F is read out, the read address n becomes equal to the write address m stored in the write address register W, so a match signal is supplied from the comparator C as a reset signal to the write mode flag generation circuit F. Set the write mode flag f to “0” and use the first selector Sa.
switch to the initial state and wait for the next transfer from the host.

As mentioned above, when the write mode flag generation circuit is in the reset state, it indicates the input data write period or a state where no data is stored, and conversely, when the write mode flag generation circuit is in the reset state, it indicates the write period of input data or a state where no data is stored. This indicates that the data to be read from the device is stored and ready for reading, and if the write mode flag f is "1", the subsequent device etc. will send a read signal to perform reading. Appear. In this way, writing and reading from one point RAM is performed alternately.

〔Example〕

FIG. 2 is an embodiment of the present invention, and FIG. 3 is a time chart for explaining its operation.
The present invention can be applied to a FIF◯ memory provided on the input side or output side of an image processing device as shown in the figure.

The image processing device shown in FIG. 5 is a transform-clipping processor that performs processing such as coordinate transformation of image data and clipping in the vertical and horizontal directions, and includes a plurality of digital signal processors (DSPs, , DSPs, etc.).
2,,,,,,,. 1) Relatively small capacity FIF◯ memories Fb++ and Fb+□, Fb21 and Fbzz for absorbing processing time differences.

It is constructed by cascadingly connecting Fbl and Fbh2, and high-speed image processing can be performed by pipeline processing using these digital signal processors.

The input side of this processing device is provided with a FIF○ memory Fa for storing image data from the host processor, and the first stage digital signal processor DSP
This image data is transferred to , via a connection device 11 provided in the preceding stage, and a FIFO memory is provided on the output side of this processing device, which serves as a buffer for storing output image data in a subsequent processor, etc. F a2 is connected to the output side of the final stage digital signal processor DSP, , via a connecting device I2.

For example, the FIF○ memo TJFa on this input side is 64KW.
It is necessary to store image data from the host that is configured as large data blocks such as X32 bits, and the output side FIF○ memo! J F at is also desired to have a capacity comparable to that of the FIF○ memory at the input end, and the FIF○ memory according to the present invention has the FIFO memory Fal provided at this input end and the output side.
Suitable for use as Fa*.

As illustrated in FIG. 4, the write mode flag generation circuit F and the received data end detection circuit E are constituted by bistable circuits such as an R-S flip-flop circuit FF, and as illustrated in FIG. As shown in the figure, when the reset signal is released and becomes "L", the device of this embodiment starts operation, but this light is not activated because there is no human power from the reception data end detection means E connected to the input terminal on the set side. The mode flag generating circuit F maintains a reset state, and its output, the write mode flag shown in FIG. 13(d), is maintained at "0".

When writing from the host to the SRAM, the host transmits a write signal 1 corresponding to the first write signal shown in FIG.
It is supplied as a write enable signal for gates g+, g2 . g
Make s conductive.

In synchronization with this write signal 1, the data shown in FIG. It is supplied as a human power to this SRAM via the data bus DB and the gate g, and is stored at the address shown in FIG.

Note that the selector Sa is switched by the write mode flag, and when the write mode flag is "0"
The write address is configured to be supplied as the SRAM0 write address when .

In this way, m pieces of data are transferred to the SRAM address l-
When the data is stored in m and the data transfer from the host is completed,
Following the above data, the host sends a write signal 2 corresponding to the second write signal and a data end code as shown in Fig. 3(c)', and this is output from the gate g3 which is in a conductive state by the gate signal generating circuit G. The reception data end detection means E which is receiving data sets the write mode flag generation circuit F according to its output and sets the write mode flag to "
Set it to 1”.

This "l" level write mode flag is supplied to the subsequent connected device N to indicate that the data transfer from the host has been completed, and also releases the reset state of the read address generation circuit R and switches the selector Sa. The SRAM access address is supplied from this read address generation circuit R.

The connection device N can tell from the write mode flag at the "L" level that the data to be received is stored in the S RAM, so when it becomes ready to receive data, the data shown in FIG. 3(f) is transmitted. Sends a read signal.

The read address generation circuit R counts this read signal and outputs a read address sequentially incremented by 1 starting from 1, and supplies it as an access address of the SRAM via the selector Sa. Data is sequentially read from the SRAM, and the read data is transferred from the gate g6, which is made conductive by the gate signal generation circuit G, to the data bus DB.
and transmits it to the connected device N or other subsequent device.

By the way, the last write address 'm' is stored in the write address register W, and the comparator C that compares this write address 'm' with the read address from the read address generation circuit R reads S. R.A.M.
Since the value of the read address becomes "m" when the last m-th data is read out, a coincidence output is obtained when reading from the SRAM is completed.

The coincidence output of the comparator C resets the write mode flag generation circuit F to set the write mode flag to "0" and also sends an interrupt signal from the interrupt generation means B to complete the transfer to the host and transfer it to the SRAM. Notifies that there is no more untransferred data in the file.

When the host receives this interrupt signal, if data to be transferred exists in the host, it sends the write signal 11 write data and write address again and transfers this data to the SR.
If there is no data to be transferred, a reset signal is output as shown by the dotted line in FIG. 3(a) to put the device in a standby state.

Note that g3 is a gate for transferring data from the connected device N or other downstream device to the host via the data bus DB, and g4 is a gate for sending a write mode flag to this data bus.

In the above embodiment, SRAM was used as the memory, but the DR
It is clear that any suitable storage device such as AM may be used.

〔Effect of the invention〕

According to the present invention, a large-capacity FI can be achieved using an inexpensive storage device.
The particular effect of being able to configure FOs is achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 28 is a block diagram showing an embodiment of the invention, FIG. 3 is a time chart for explaining the operation of the embodiment shown in FIG. 2, and FIG. The figure shows an example of a received data end detection circuit and a write mode flag generation circuit, and FIG. 5 is a block diagram of an image processing apparatus suitable for using the FIFO according to the present invention. An example of a reception signal termination detection circuit and a remote flow generation circuit.

Claims (1)

[Claims] A memory (M) having one input/output port, a write address register (W) that stores the final write address (m) to this memory, and an enable from a downstream device (A). A read address generation circuit (R) that generates a read address of the memory (M) according to a signal, and a final write address stored in the read address from this read address generation circuit (R) and the write address register (W). a comparator (C) for comparing the address (m); a comparator (C) that is reset by a first write signal when writing the memory, is set by a second write signal and a control bit when reading the memory; The write mode flag (
a write mode flag generation circuit (F) that outputs the memory (M);
) is provided with a selector (Sa) that switches the access address of the memory (M) between a write address and a read address, and the write mode flag (f) indicates that there is data to be read in the memory (M). A first-in/first-out memory configuration method characterized in that a notification is sent to a device (A).