JPS63172332A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize the transfer of data substantially for each n/2 bits by providing a function to a CRT controller to process the data of an n-bit unit after dividing internally into n/2-bit data. CONSTITUTION:The 8-bit data (j4, k4) supplied to a buffer 1 are stored twice repetitively in different areas of a buffer 2. Then the first data (j4, k4) is sent to a data exchange circuit 4 via a buffer 3 for exchange between higher and lower rank 4 bits. The 8-bit data (a4, b4) are read out of a RAM via a switch circuit 6. Then said RAM data are synthesized with the data (k4, j4) received from the circuit 4 via a bit mask circuit 5 and the data (a4, j4) are stored in the original address of the RAM. In the same way, the data (k4, j4) are stored in the original address for the RAM data and the data (c4, d4) adjacent with each other in the RAM.

Description

[Detailed Description of the Invention] [Summary] The CRT controller according to the semiconductor integrated circuit device of the present invention has a 41 rl that internally processes 8-bit data by dividing it into 4-bit first data. ing. This allows data transfer in 4-bit units as well as 8-bit data transfer.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and more specifically to a CRT controller for a semiconductor IIa circuit device that converts data input in units of 8 bits into data in units of 4 bits and transfers data. It is.

[Conventional technology]

A conventional CIIT controller that processes data in 8-bit units only has a data processing function in 8-bit units, and that is sufficient.

[Problem that the invention seeks to solve]

However, recently, transferred character data is used as CR.
A CRT that not only displays text on the screen, but also has the ability to display text at regular intervals to make it easier to see.
A controller is required.

The present invention is intended to meet such demands, and aims to provide a CRT controller that enables data transfer in 8-bit units as well as substantially 4-bit unit data transfer.

[Means for solving problems]

The present invention includes a CPU data buffer that inputs data in units of n bits, and a CPU data buffer that inputs data in units of n bits.
A 32-byte transfer data buffer that can store n-bit medium data in a location specified by , and a VRAM (video RAM) that inputs n-bit data sequentially output by a select signal (SL). ) data buffer, and the upper n/2 bits and lower n72 bits of the n-bit unit output from the VRAM data buffer.
a data conversion circuit capable of interchanging bits; a bit mask circuit for synthesizing data in units of n bits output from the data conversion circuit and data in units of n bits read from the memory; The present invention is characterized in that it includes a VRAM R/11 switching circuit that writes the composite data output from the bit mask circuit into the memory, or reads the data output from the memory and transfers it to the bit mask circuit.

[Effect]

When data is transferred substantially in units of n/2 bits, the CPU and CRT controller operate as follows. First, the CPU specifies in advance a transfer in units of n/2 bits, a transfer address, a method for incrementing the transfer address, and the number of bytes to be transferred.

The transfer specification in n/2 bit units does not change until the CPU next specifies the transfer in n bit units.The transfer address is the address at which the CRT controller accesses the VRAM, and the increment method is continuous at one time. This specifies the number of bytes to increment the transfer address when transferring several bytes. The number of bytes to be transferred can range from 1 byte to a maximum of 32 bytes at a time.

Next, the CPU writes data for the number of bytes to be transferred to a designated transfer data buffer via the CPU data buffer, and provides a trigger (TRG) to the CRT controller to instruct the start of transfer.

The CRT controller receives a trigger from the CPU and starts transfer. First, in response to the select signal (SL), the first data in the 32-byte transfer data buffer is output to the 4-bit data conversion circuit via the VRAM data buffer. The 4-bit data conversion circuit is provided to support the following four transfer methods.

That is, (1) Transfer the upper n/2 bits of n-bit data to the upper n/2 bits of the data at the transfer address.

(2) Transfer the lower n/2 bits of the n-bit data to the lower n/2 bits of the data at the transfer address.

(3) Transfer the upper n/2 bits of the n-bit data to the lower n/2 bits of the data at the transfer address.

(4) Transfer the lower n/2 bits of the n-bit data to the upper n/2 bits of the data at the transfer address.

There are four ways above, but for (3) and (4) above, the upper n/2 bits and lower n/2 bits of n-bit data
This is because it is necessary to insert a bit.

Meanwhile, at the same time, n-bit data at the designated address is read from the VRAM. The data read from this VRAM and the data output from the data conversion circuit are both input to the bit mask circuit.

New n-bit data is synthesized according to the four transfer methods described above.

For example, in the case of (3) above.

The n-bit data input from the VRAM data buffer to the 4-bit data conversion circuit is inputted to the bit mask circuit with the upper n/2 bits and lower n/2 bits switched, and then the upper n 72 bits of this input data are exchanged. and the lower n/2 bits of the n-bit data read from the VRAM and input to the bit mask circuit are combined to generate new n-bit data.

Next, this combined data is transferred to the VRAMR/W address. Although this is essentially a read-modify-write, it is possible to process n-bit unit data as n/2-bit medium data using the above method.

〔Example〕

Next, an embodiment of a 4-bit shift according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a CRT controller according to an embodiment of the present invention, and FIG. 2 is a timing chart of control signals and data of the CRT controller of the present invention. Further, FIG. 3 is a diagram showing the flow of data processed by the CRT controller of the present invention, and FIG. 4 is a diagram showing the wiring state of the CRT controller connected to an external circuit (RAM).

In FIG. 1, l is a CPU data buffer that inputs 8-bit middle-order data via an 8-bit CPU data bus. Reference numeral 2 denotes a transfer data buffer having a 36-byte storage area, in which data output from the CPU data buffer 1 can be stored. 3 is a VRAM data buffer, and data in the transfer data buffer 2 is sequentially read out.

Reference numeral 4 denotes a 4-bit data conversion circuit, which can exchange the upper 4 bits and lower 4 bits of 8-bit medium data. 5 is a bit mask circuit, which can synthesize the 8-bit middle-order output data read from the RAM and the 8-bit middle-order output data of the data conversion circuit using the 4-bit middle order of the upper 4 bits and the lower 4 bits. It is. 6 is VR
The AMR/- switching circuit is capable of storing output data from the bit mask circuit 5 in the RAM according to address designation, or transferring data read from the RAM to the bit mask circuit 5 or the VRAM data buffer 3.

Next, the timing chart in FIG. 2 and the data flow chart in FIG. I will explain while referring to it.

First, 8-bit medium-sized CPU data (the upper 4 bits are expressed as 14 and the lower 4 bits are expressed as 4) inputted to the CPU data back 1 is stored in the transfer data buffer 2. At this time, the CPU uses the same CPU data (j4
, ks) to two adjacent storage areas.

Next, data is sequentially transferred from the transfer data buffer 2 to the VRAM data buffer 3 by the select signal (SL), but first the first CPU data (341kl
) is input to the 4-bit data exchange circuit 4. As a result, the upper 4 bits and lower bits of the first CPU data buffer (ji, ka) are swapped (j4).

k4) is output.

On the other hand, 8-bit middle data C"a + bs is transferred from RAM by the transfer address signal (AD) to RAM.
) is read by VRAMR/WRAM data,
It is latched into the bit mask circuit 5 by the latch clock (LGB). The bit mask circuit 5 stores the RAM data (
as, b4) and the replacement data (k4, j4) in the middle of 4 bits to obtain (as, ja). Then, the VRAMR/- switching circuit transfers the data (a4, j4) according to the transfer data buffer output clock. ) to the original address in RAM.

Similarly, the second CPU data (j4.

11) is input to the 4-bit data conversion circuit 4.

The upper 4 bits and lower 4 bits are swapped (ki
+ja) is output. On the other hand, 8-bit data (04*d*) adjacent to the aforementioned data (am, b4) is read from the RAM, and the data (k4, j
i). At this time, the upper 4 bits of the RAM data are rewritten to 0, which becomes data (ks, d*).Then, this data (ks, d4) is written to the original address of the RAM.

In this way, as shown in FIG. 3, according to the CRT controller of the embodiment of the present invention, 8. CP in bits
Shift the U data (j4, 4) by 4 bits and store it in RAM.
can be written to. That is, while transferring data in units of 8 bits, substantially the same result as performing data transfer processing in units of 4 bits can be obtained.

'In the JAM example, a 4-bit shift was discussed, but in addition to shift processing, various processing can be performed using a bit mask circuit.

In addition, as shown in Figure 4, data transfer in 4-bit units can be done using the same connection status as 8-bit data transfer, so there is no need to increase the number of special terminals for data transfer in 4-bit units. , Therefore, it is possible to suppress an increase in the number of terminals, and it is possible to downsize the device.

Note that, of course, it is also possible to transfer data in units of 8 bits as is, without performing 4-bit processing, as in the conventional case.

In the embodiment, 8-bit data is essentially 4 bits)1
Although the description has been given of the case where the data is transferred as data in units of n bits, it is also generally applicable to the case where data in units of n bits is transferred as data in units of n/2 bits.

〔Effect of the invention〕

As explained above, according to the CRT controller according to the semiconductor integrated circuit device of the present invention, it is possible to transfer data not only in units of n bits but also in units of n/2 bits as necessary. , extremely convenient.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a CRT controller according to an embodiment of the present invention. 2 is a timing chart explaining the operation of the CRT controller shown in FIG. 1, and FIG. 3 is a diagram showing the flow of data within the CRT controller shown in FIG. 1. FIG. 4 is a diagram illustrating the connection state of the CRT controller of the present invention with an external circuit. (Explanation of symbols) 1...CPU data buffer, 2...Transfer data buffer. 3...VRAM data buffer. 4...4-bit data conversion circuit. 5...Bit mask circuit. 6-VRAM R/W switching circuit. Noto J 喰5B Monthly Karipi Bun Ij Reno Day 6 U〉Mi lff1 Figure 1 Crawl (CL in 1 啼”0 2 shi r-da 8 ≧ Kuku L) To me!L4′-ta+l2ac34tl ( Kgdg) Quiminck child yard Figure 2

Claims (1)

[Scope of Claims] A first data buffer that receives data in units of n bits; a transfer data buffer that is capable of repeatedly storing data output from the first data buffer twice in separate areas; a second data buffer that sequentially receives data from the transfer data buffer; and a data conversion capable of interchanging upper n/2 bits and lower n/2 bits of n-bit data output from the second data buffer. a bit mask circuit that synthesizes n-bit data output from the data conversion circuit and n-bit data read from the memory; and a bit mask circuit that combines the n-bit data output from the data conversion circuit with the n-bit data read from the memory; A semiconductor integrated circuit device comprising a switching circuit for writing or reading data output from the memory and transferring the data to the bit mask circuit.