JPH0367294A - Display controller - Google Patents

Abstract

PURPOSE:To quickly change the display of a display screen and simultaneously to eliminate the need for a storage means whose capacity is large by making respective display devices share a frame memory, temporarily storing display data which is actually used for the display of the respective screens in a display data temporary storage means and successively reading out the display data from the display data temporary storage means. CONSTITUTION:The subject controller is provided with plural display devices 5 and 8, the frame memory 13 which is shared by the respective display devices 5 and 8, the display date temporary storage means 14 and 16 which are provided on every display device 5 and 8 and a display control circuit 12 which controls the timing that the display data is transferred to the display data temporary storage means 14 and 16 from the frame memory 13. Then, the storage capacity of the storage means 14 and 16 is one that at least the display data as much as one picture element is stored and the display of the display screen is executted based on the display data stored in the storage means 14 and 16. Thus, the storage device whose capacity is large need not be prepared and the display of the display screen can be quickly changed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a display control device that controls display of a plurality of display devices.

(Prior Art) At financial institutions, customers sometimes perform personal withdrawal transactions, transfer transactions, etc. by orally informing an operator of transaction details without creating various transaction slips. In this case, a terminal device is used that has two display devices, one for the operator and the other for the customer. When conducting a transaction using such a terminal device, the customer uses a dedicated keyboard or the like to input an account number, password, etc.

This inputted information is displayed on a display device dedicated to the operator, and once the information necessary for the transaction is collected, the operator displays the various information on a display device dedicated to the customer for confirmation and obtains customer confirmation. .

Now, in the terminal device that processes transactions as described above, two display control circuits control and manage the two display devices.

FIG. 2 shows a block diagram of a conventional display control device (terminal device).

In the figure, a main storage device 2, a first display control circuit 3, a first display memory 4, a second display control circuit 6, and a second display memory 7 are connected to a processor l via a data bus 9. It is connected. A first display device 5 is connected to the first display control circuit 3, and a second display device 8 is connected to the second display control circuit 6. Furthermore, the first display memory 4
and second display memory 7 are connected to first display control circuit 3 and second display control circuit 6, respectively. If the first display device 5 is a display device exclusively for the operator, the second display device 8 is a display device exclusively for the customer.

The processor 1 is a circuit including a microprogram and the like for controlling and managing each block.

The main storage device 2 is composed of a random access memory (RAM) and the like that stores control information for the operation of the processor 1. The first display control circuit 3 and the second display control circuit 6 output display synchronization signals and the like for driving the first display device 5 and the second display device 8, respectively. The first display memory 4 and the second display memory 7 temporarily store data (parallel image data) etc. to be displayed on the first display device 5 and the second display device 8, respectively, and have a storage capacity of about 128 Kbytes, for example. Random access memory (RAM) with storage capacity
) etc.

In the device configured as described above, when displaying on the first display device 5, the processor 1 writes parallel image data to the first display memory 4 and also instructs the first display control circuit 3 to perform a display operation. give. The first display control circuit 3 that has received the display operation instruction transfers the parallel image data written in the first display memory 4 together with a display synchronization signal to the first display device 5 . The first display device 5, based on the parallel image data and the display synchronization signal,
A predetermined display is performed on the display screen 5a.

Similarly, on the display screen 8a of the second display device 8, a predetermined display is performed using the second display control circuit 6 and the second display memory 7.

(Problem to be Solved by the Invention) Here, in order to obtain confirmation from the customer as described above, the operator directly displays the image displayed on the display screen 5a of the first display device 5 on a second screen dedicated to the customer. A case will be described in which an attempt is made to switch to the display screen 8a of the display device 8 for display.

The parallel image data of the image displayed on the display screen 8a of the second display device 8 must always be the one written in the second display memory 7. Therefore, the parallel image data written in the first display memory 4,
It is necessary to transfer it to the second display memory 7 via the pass line 9.

However, transferring parallel image data from the first display memory 4 to the second display memory 7 or vice versa takes a very long time. Therefore, the first display device 5
There was a problem in that the images on the display screen 5a of the second display device 8 and the display screen 8a of the second display device 8 could not be quickly switched. Further, the transfer of parallel image data between the first display memory 4 and the second display memory 7 has also become a burden on the processor 1 that controls this.

In order to solve this problem, a common display memory is provided that stores the display data to be displayed all at once, and the contents of this common display memory are transferred to the frame memory provided for each display device, and the display data is transferred to the frame memory provided for each display device. A display control device that performs this has been proposed.

In the case of this display control device, since each display device shares the contents of the common display memory, the same display can be easily displayed on each display device. However, the common display memory requires a storage capacity of at least one display screen. Further, a frame memory having a capacity to store display data for one screen is prepared corresponding to each display screen. For this reason, a problem arises in that a large-capacity storage device must be prepared to support the common display memory and each frame memory, resulting in increased costs. Furthermore,
A problem has arisen in that even if the contents of the common display memory are changed, the display on the display screen is not immediately changed and a delay occurs. This delay is because the contents of the frame memory do not change immediately in response to the contents of the common display memory. This is because, in order to transfer the contents of the common display memory to the frame memory, processing such as predetermined address conversion must be executed, and a delay time occurs corresponding to the time required for such calculation.

The present invention has been made with attention to the above points, and an object of the present invention is to provide a display control device that does not require the preparation of a large-capacity storage device and can quickly change the display screen display. It is something.

(Means for Solving the Problems) A display control device of the present invention collectively stores a plurality of display devices that display predetermined display screens and display data corresponding to the display screens displayed on each of the display devices. a display memory circuit; and a display control circuit that controls the timing of display data output from the display memory circuit to the display device; the display memory circuit includes a frame memory that stores the display data; Display data temporary storage means is provided for each device and temporarily stores the display data read from the frame memory corresponding to at least one pixel of the display screen, and the display control circuit is configured to store each of the display data. The temporary storage means selects and reads out the display data to be displayed on each of the display screens from the frame memory and sequentially stores it in each of the display data registers.

(Function) The above device includes a plurality of display devices, a frame memory shared by each display device, display data temporary storage means provided for each display device, and display data from the frame memory to the display data temporary storage means. A display control circuit that controls the timing of data transfer is prepared. Note that the storage capacity of the display data temporary storage means is such that display data for at least one pixel can be stored. Display on the display screen is performed based on the display data stored in the display data temporary storage means.

That is, when the display screen is composed of n pixels and display data for one pixel is stored in the display data temporary storage means, the display data temporary storage means is rewritten 0 times and further read out to display the display screen 1. Display the screen. In this way, the display device can display the display screen based on the contents of the display data temporary storage means.

(Example) FIG. 1 shows a block diagram of a display control device of the present invention.

In the figure, a main storage device 2, a memory circuit 11, a display control circuit 12 are connected to a processor l via a path line 10.
is connected. Further, a first display device 5 and a second display device 8 are connected to the display memory circuit 11. The processor 1, the main memory 2, and the first and second display devices 5.8 are similar to those previously described in FIG. 2. Therefore, duplicate explanations will be omitted.

The display memory circuit 11 includes a frame memory 13, a first display data temporary storage means 14, a first digital-to-analog converter (D/A converter) 15, a second display data temporary storage means 16, a second digital An analog converter (D/A converter) 17 is provided.

The frame memory 13 stores display data for at least one display screen to be displayed on the display screen of each display device.
It is composed of AM, etc., and usually has a storage capacity of several hundred bytes. The first and second display data temporary storage means 14.16 respectively include a display screen 5a,
It is composed of a serial data register, etc., which stores display data (serial data) to be displayed on 8a. Note that this serial data register is a FIFO
It is of the form. Also, the display data (for 1 pixel) is 1
When displaying in six colors, a 4-bit register is used. The first and second D/A converters 15.17 receive serial data from the first and second display data temporary storage means 14.16 and convert it into analog data for display on the display screens 5a and 8a, respectively. It is something to do.

When displaying the display screens 5a and 8a, the display control circuit 12 controls the timing for reading display data from the frame memory 13 and generates a read address, and also temporarily stores the first and second display data. Means 14.16
It is composed of a timing generator and the like that controls the timing of writing display data into the display.

The display control circuit 12 and the frame memory 13 are connected by control lines 21, 22 and address lines 23. A data line 24 connects the frame memory 13 and the first and second display data temporary storage means 14,16. The display control circuit 12 and the first display data temporary storage means 14 are connected by a control line 25, and the first display data temporary storage means 14 and the first D/A converter 15 are connected by a data line 26. connected by. Similarly, there is no control between the display control circuit 12, the second display data temporary storage means 16, and the second D/A converter 17.
7 and data line 28, it is connected ↑ and sold.

The operation of the display control device having the above configuration will be explained with reference to FIG.

FIG. 3 is a timing chart according to the present invention.

FIGS. 3(a) and 3(b) show read timing signals output from the display control circuit 12 to the frame memory 13 on the control lines 21 and 22, respectively. Figure 3 (C
) indicates an address signal output from the display control circuit 12 to the address line 23 toward the frame memory 13. FIG. 3(d) shows a serial data signal output from the frame memory 13 to the data line 24 toward the first and second display data temporary storage means 14.16. FIG. 3(e) shows a control signal output from the display control circuit 12 to the control line 25 toward the first display data temporary storage means 14.

FIG. 3(f) shows a serial data signal output from the first data temporary storage means 14 to the first D/A converter 15. FIG. FIG. 3(g) shows a control signal outputted from the display control circuit 12 to the control line 25 toward the second display data temporary storage means 16. FIG. 3(h) shows data from the first data temporary storage means 14 to the second D.
A serial data signal output to the /A converter 17 is shown.

Now, the display control circuit 12 is shown in FIG. 3(a).

As shown in (b), high level pulses P, .

. . . and P R++ P 221 . . . are output. Furthermore, as shown in FIG. 3(c), the display control circuit 12 generates pulses P++, P+□, . . . P21 .
One offering address is output in synchronization with P2□, .

Now, read address signal a, “boo.

Assume that a' and "b"' are output. As shown in FIG. 3(d), the display data stored in the frame memory location indicated by the read address is read out and output to the data line 24.

Now, the display data d'° outputted to the data line 24 at the same time as the pulse Pl+ is stored in the first display data temporary storage means 14. Similarly, the display data line 24 output to the data line 24 in synchronization with the pulse P21 is stored in the second display data temporary storage means 16. Note that the first and second display data temporary storage means 14.16
It is determined whether the data on the data line 24 is to be stored or not depending on which of the control lines 21 and 22 a pulse is output. That is, when a pulse is output to the control line 21, the first display data temporary storage means 14 stores the display data. Further, when a pulse is output to the control line 22, the second display data temporary storage means 16 stores the display data.

Here, the display on the first display device 5 will be explained.

As shown in FIG. 3(e), the display control circuit 12
It outputs readout control pulses at a constant cycle to the display data temporary storage means 4. As shown in FIG. 3(f), the first display data temporary storage means 14 outputs display data to the data line 26 one bit at a time. The display data is output in synchronization with a control pulse input from the control line 25. The first D/A converter 15 converts the display data input from the data line 26 into analog format display data when 4 bits are complete, and outputs the data to the first display device 5. In the first display device 5, upon receiving this display data, the display screen 5a
will be displayed. Note that when the first display data temporary storage means 14 stores the display data output to the data line 24, it does not output data to the data line 26.

Next, the display on the second display device 8 will be explained.

As shown in FIG. 3(g), the display control circuit 12
It outputs readout control pulses at a constant cycle to the display data temporary storage means 16 of. Note that the period of this control pulse is contradictory to that of the pulse output to the first display data temporary storage means 14. As shown in FIG. 3(h), the second display data temporary storage means 1
From 6 onwards, display data is output to the data line 28 one bit at a time. The display data is output in synchronization with a control pulse input via the control line 27. The second D/A converter 17 converts the display data input from the data line 28 into analog format display data when 4 bits are complete, and outputs it to the second display device 8.

When the second display device 8 receives this display data, it will display the display screen 8a. Note that when the second display data temporary storage means 16 stores the display data output to the data line 24, it does not output data to the data line 28.

As explained above, after the display data stored in the frame circuit 13 is once stored in the first display data temporary storage means 14 and the second display data temporary storage means 16,
Since the data is transferred to the first display device 5 and the second display device 8, respectively, the contents of the frame memory 13 can be changed at any time except when data is stored in each display data temporary storage means. Further, when data is transferred from the frame memory to the respective time storage means, it can be directly stored without performing procedures such as address conversion, so that rapid processing can be performed. That is, the display screen is displayed based on the latest display data stored in the frame memory 13.

The display control device of the present invention is not limited to the above embodiments.

In the embodiment, first and second display data temporary storage means 1
4.16 is composed of serial data registers of 4 bits each, but for example, the display data is not divided into one pixel but one character, for example, 32 pixels or 4 bits.
It may be configured with 88 pixels. In this case, the capacity of each display data temporary storage means will be changed as appropriate.

(Effects of the Invention) The display control device of the present invention described above shares the frame memory with each display device, temporarily stores the display data actually used for displaying each screen in the display data temporary storage means, Since the display data is sequentially read from the display data storage means, when changing the contents of the frame memory, there is no possibility that the change cannot be executed because each display device is accessing it. Furthermore, when the contents of the frame memory are changed, the display data temporary storage means always uses the frame memory 13.
Since the latest contents of the frame memory are stored, there is no possibility that the contents of the frame memory are changed but the display on the display screen is not changed immediately. Furthermore, since there is no need to prepare a storage device with a large storage capacity other than the frame memory, the cost of the device can be easily reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a display control device according to the present invention, FIG. 2 is a block diagram of a conventional display control device, and FIG. 3 is a timing chart according to the present invention. DESCRIPTION OF SYMBOLS 1... Processor, 2... Main storage device, 5... First display device, 5a, 8a... Display screen, 8... Second display device, 10... Pass line, ■... Display memory circuit, 12... Display control circuit, 3... Frame memory, 4... First display data temporary storage means, 5... First
6. Second display data temporary storage means, 7. Second digital to analog converter. Front diagram of conventional display control circuit Figure 2

Claims (1)

[Scope of Claims] A plurality of display devices that display predetermined display screens; a display memory circuit that collectively stores display data corresponding to the display screens displayed on each of the display devices; a display control circuit that controls the timing of display data output to a display device; the display memory circuit includes a frame memory that stores the display data; and a frame memory that is provided for each display device and that controls at least the display screen. display data temporary storage means for temporarily storing the display data read out from the frame memory corresponding to one pixel; A display control device characterized in that the display data to be displayed on each of the display screens is selected and read and sequentially stored in each of the display data registers.