JPH064067A - Still picture reproducing device - Google Patents

Abstract

PURPOSE:To simultaneously execute the transfer of image data and the switching control of a display screen as for a still picture reproducing device. CONSTITUTION:As for the still picture reproducing device provided with a control host processor 2, plural image processors 17 and 18 and an image extension processor 7, the local busses 19 and 20 of the processors 17 and 18 are made independent. Then, the image data from an I/O controller 3 is transferred to image memories 4 and 5 through one bus 19, and a key signal memory 8 and screen refresh address counters 9 and 10 are controlled through the other bus 20. Besides, the processor 7 is connected to one local bus and the compressed image data from the controller 3 is extended and transferred to the memories 4 and 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still image file system or a general image file system which requires processing of a still image or image processing for switching images and displaying the processing result at the same time. The present invention relates to a still image reproducing device applicable to an image device.

[0002]

2. Description of the Related Art Conventionally, as this type of still picture reproducing apparatus, for example, there is one having a configuration shown in FIG. 2, and this still picture reproducing apparatus controls and manages the entire apparatus via a system bus 1. 2, an I / O controller 3 for controlling data transfer of input / output images, a plurality of image memories 4 and 5 corresponding to the transfer destination of the image data, and a predetermined process of the image data of the plurality of image memories 4 and 5. An image processor 6 (including data transfer), an image expansion coprocessor (hereinafter referred to as a coprocessor) 7 that expands and transfers the compressed image data from the I / O controller 3 to a predetermined image memory, and the plurality of the above. Key signal memory 8 for selecting the image data read from the image memories 4 and 5 according to the display area, and the screen refresh address of the plurality of image memories 4 and 5. Screen refresh address counters 9 and 10 for outputting signals (data), and screen switching for switching the image data of the image memories 4 and 5 read by the screen refresh address signal by the selection signal from the key signal memory 8. Circuit 11,
The D / A conversion unit 12 that converts the image data switched by the screen switching circuit 11 into an analog image and outputs the image, and the control host processor 2 are the same in order to enable control and management of the image processing processor 6. It is composed of a host interface 13 for connecting the image processor 6 to the system bus 1.

Further, in this still picture reproducing apparatus, a command is issued from the control host processor 2 when an image is input, a predetermined processing of the input image and a switching display of the processed image are performed, and the I / O controller is issued by this command. 3. The image processor 6 and the coprocessor 7 execute predetermined processing.

Therefore, the image memories 4 and 5, the key signal memory 8 and the screen refresh address counters 9 and 10 have a data bus (including address data) 1
4a and the local bus 14 of the address line 14b is connected to the image processor 6, the data of the key signal memory 8 is rewritten by the image processor 6, and the address data of the screen refresh is the screen refresh. It is output to the address counters 9 and 10, and the output timing of the screen refresh is taken. Further, the buffer selectors 15 and 16 are switched according to the output timing of the screen refresh, and one of the image data in the image memories 4 and 5 is input to the image switching circuit 11 by this switching. The coprocessor 7 is connected to the system bus 1 and the local bus 14.

In the still picture reproducing apparatus having the above construction, the display picture can be arbitrarily switched by rewriting the data corresponding to the display pixel of the key signal memory 8 connected to the local bus 14 of the image processor 6. You can do it.

In addition, by combining the screen refresh function for continuously moving the display area such as horizontal / vertical rolls and slide-in / out with the switching of display images by the key signal memory 8, various images can be obtained. It is possible to switch.

[0007]

In the still picture reproducing apparatus, when the control host processor issues an image input command, the I / O controller 3 stores the input image data in the predetermined image memory 4.
Transferred to.

Since this image data is transferred via the local bus 14, the input image data is I
/ O controller 3, system bus 1, host interface 13, image processor 6, local bus 1
The image data is transferred to the image memory 4 or the image memory 5 through the route 4, and the input image data is transferred to the I / O controller 3,
The data is transferred to the image memory 4 or the image memory 5 via the system bus 1, the coprocessor 7, and the local bus 14.

Therefore, the input image data cannot be transferred when the screens are switched, and conversely, the screen switching control cannot be performed when the input image data is transferred.

That is, bus conflict occurs in the local bus 13, which makes it difficult to smoothly perform the transfer of the input image data and the switching control of the screen at the same time, and the execution efficiency of the device control is low. Was.

In addition, the instruction from the control host processor 2 to each processor may conflict on the system bus 1, and it may not be possible to control each processor at an arbitrary time.

The present invention has been made in view of the above problems, and an object thereof is to smoothly perform transfer of image data (or compressed image data) and screen switching control at the same time without occurrence of locus bus competition. Another object of the present invention is to provide a still image reproducing device which can be controlled by the control host processor at any time.

[0013]

In order to achieve the above object, the present invention provides a control host processor, an image processing processor, an image expansion coprocessor, an I / O processor for performing at least image processing and switching of a plurality of images. An O controller, a key signal memory, a plurality of image memories and a screen refresh address counter
The image data from the O controller is transferred to a predetermined image memory, the compressed image data from the I / O controller is decompressed and transferred to the image memory, the data in the image memory is processed in a predetermined manner, and the data in the key signal memory is transferred. The data corresponding to the display pixel is processed in a predetermined manner, the data of the predetermined image memory is switched, and the address signal of the image memory is output by the screen refresh address counter to continuously display the image display area by the data of the image memory. A still image reproducing apparatus that is movable in a static manner, in which a first image processor performs predetermined processing on image data from the I / O controller, and an image expansion coprocessor compresses an image from the I / O controller. The data is processed in a predetermined manner, and the second image processor processes the data. -In order to control the data rewriting of the signal memory and the data output of the screen refresh address counter, the first image processor and the plurality of image memories are connected by a first local bus, and the second image processing is performed. Second processor, key signal memory and screen refresh address counter
Connected to the system bus of the control host processor via the host interface, and the image decompression coprocessor to the second local bus. The gist is that the control host processor is connected to manage and control at least each of the processors at an arbitrary time.

[0014]

In the still picture reproducing apparatus having the above structure, the first local bus and the second local bus are independent of each other, and the image data input by the I / O controller is transferred to the predetermined image memory. At this time, the transfer function of the image data is shared by the first image processor, and the image data is transferred to the predetermined image memory via the first local bus.

When the compressed image data from the I / O controller is expanded and transferred to the predetermined image memory, the image data is expanded by the image expansion coprocessor, and the expanded image data is the first image data. Is transferred to a predetermined image memory via the local bus.

Since the transfer of the image data (or the compressed image data) does not use the second local bus, the key signal memory may be used depending on the second image processor connected to the second local bus. Can be rewritten and the data of the screen refresh address counter can be written simultaneously with the transfer of the image data.

As described above, since the first and second local buses can cause the first and second image processors to perform different processing independently of each other, the transfer of the image data and the screen switching control are performed. Is done smoothly at the same time.

In the control host processor, the image expansion processor may be connected to the first local bus when controlling the processors and the I / O controller as sub processors. It is possible to control the instruction of each processor at an arbitrary time without causing bus contention on the system bus.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION A still image reproducing apparatus of the present invention connects two image processing processors and I / O controllers controlled and managed by a control host processor to a system bus, and a plurality of image processing processors are connected to a local bus. An image memory and an image decompression processor are connected, a key signal memory and a screen refresh address counter are connected to a local bus of the other image processing processor which is independent of this image processing processor, and the I / The image data is processed from the O controller, the compressed image data from the I / O controller is processed (expanded and transferred) by the image expansion processor, and the display screen switching control is performed by the other image processing processor. ing.

Therefore, the still picture reproducing apparatus has the structure shown in FIG. In the figure, the same parts as those in FIG. 2 and corresponding parts are designated by the same reference numerals, and a duplicate description will be omitted.

In FIG. 1, reference numeral 17 is a first image processor for performing a predetermined process (including data transfer process) on the image data of the image memories 4 and 5, and 18 is a screen switching of the key signal memory 7 at least. This is a second image processing processor that rewrites data and outputs switching address data to the screen refresh address counters 8 and 9, and the first and second image processing processors 17 and 18 are connected to the system bus via the host interface 13. 1 and is managed and controlled by the control host processor 2.

First of the first image processor 17
Image memories 4 and 5 and an image expansion coprocessor (hereinafter referred to as a coprocessor) 7 are connected to the local bus 19 of the above, and a key signal memory 8 is connected to the second local bus 20 of the second image processor 18. And the screen refresh address counters 9 and 10 are connected.

The coprocessor 7 is connected to the I / O controller 3 so that the compressed image data from the I / O controller 3 is expanded and transferred to the image memories 4 and 5. The output timing (screen refresh timing) of the screen refresh address counters 9 and 10 is controlled by the second image processor 18.

As before, the first and second local buses 19 and 20 are data buses (including addresses) 19 as well.
a, 20a and address lines 19b, 20b, the address line 19b serves as a screen refresh timing, that is, a selection signal for the buffer selectors 15, 16, and the address line 20b serves as an address for the key signal memory 8. There is.

As a result, the I / O controller 3, the first image processor 17 and the second image processor 18 are connected to the control host processor 2 via the system bus 1, and the first and second image processors 17 and 18 are connected to each other. The image processing processors 17 and 18 may have a common host interface 13.

The first image processor 17 is also provided.
The first local bus 19 provides a transfer path for transferring the image data from the image device connected to the I / O controller 3 to the first or second image memory 4 or 5. In this case, as a transfer path for transferring the image data as it is, I
A path for the I / O controller 3, the system bus 1, the host interface 13, the first image processor 17, the first local bus 19, the image memories 4 and 5 is secured, and an I / O controller for the image compressed data. 3, the path of the coprocessor 7, the image memories 4 and 5 is secured.

Here, the control host processor 2 issues separate commands to the first and second image processing processors 17 and 18, and transfers image data input via the I / O controller 3, for example, and When the screen switching control command is issued, the image transfer control by the first image processor 17 and the first local bus 19 and the screen switching control by the second image processor 18 and the second local bus 20 are performed. It will be done almost in parallel at the same time.

That is, the first local bus 19 and the second local bus 20 are independent of each other, and, for example, input image data is transferred to the I / O controller 3, the system bus 1,
When transferring to the image memory 4 or the image memory 5 through the path of the host interface 13, the first image processor 17 and the first local bus 19, it is necessary to use another second local bus 20 for the image data transfer. Because there is no.

On the other hand, with respect to the compressed image data input from the I / O controller 3, the compressed image data is decoded into the restored image data by the coprocessor 7, and the restored image data is transferred to the first local bus. It is directly transferred to the designated image memory via 19.

As described above, the transfer of the image data (expansion transfer of the compressed image data) or the image processing by the first image processing processor 17 and the screen switching processing can be performed independently and in parallel. Can be performed smoothly at the same time.

The first image processor 17 is also used.
Since all the image memories are connected to the first local bus 19 of the above, it is possible to cause the control host processor 2 to perform arbitrary transfer between all the image memories. The screen can be switched at the time of data transfer, and for example, the screen can be switched between horizontal and vertical rolls and slide in / out.

That is, the second image processor 18 independently sets the initial values of the screen refresh address counters 9 and 10 of the image memories 4 and 5 as in the conventional case, and the reference display position based on the screen refresh function. Is given to the key signal memory 8.

Furthermore, when decompressing and transferring compressed image data by the coprocessor 7 and image processing by the first and second image processing processors 4 and 5, it is not necessary to use the system bus 1, and the coprocessor 7 is I The control host processor 2 is connected to the I / O controller 3 and the first and second image processing processors 17 and 18 are connected to the host interface 13.
Is an I / O controller 3 connected to the system bus 1, the first and second image processors 17,
18 can be managed equally as sub-processors, and each processor can be controlled at any time, which facilitates system control of the still image reproducing apparatus.

[0034]

As described above, according to the still image reproducing apparatus of the present invention, the local buses of the two image processing processors are made independent, and one image processing processor processes the data in the plurality of image memories. A key signal memory for writing screen switching data in the other image processor, setting screen refresh address data for a plurality of image memories, and controlling the two image processors through a common host interface An image decompression coprocessor that is connected to the bus and that decompresses the input compressed image data from the I / O controller that inputs and outputs the image data that is connected to the system bus and transfers it to the image memory. , And control each processor with the above control host processor. . Thus managed, in the one image processor and the other image processing processor of the can perform different processing independently, the transfer processing or I image data of a plurality of images memory
Even when the process of decompressing and transferring the compressed image data from the / O controller is being performed, the screen can be switched without bus contention on the local bus, that is, the transfer of the image data (compressed image data) and the screen switching process. Can be done smoothly at the same time.

Further, in the control host processor of the still picture reproducing apparatus of the present invention, the system bus can be utilized when the image data is transferred and the screen is switched at the same time as described above. The processors and the I / O controller can be equally managed as sub-processors, each processor can be controlled at an arbitrary time, and the system control of the still image reproducing apparatus can be easily performed. .

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a still image reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram of a still image reproducing device.

[Explanation of symbols]

 1 System Bus 2 Control Host Processor 3 I / O Controller 4,5 Image Memory 7 Image Decompression Coprocessor 8 Key Signal Memory 9, 10 Screen Refresh Address Counter 11 Screen Switching Circuit 12 D / A Converter 13 Host Interface 17 First Image processor 18 Second image processor 19 First local bus 20 Second local bus

Claims (1)

[Claims] 1. A control host processor, an image processing processor, an image expansion coprocessor, an I / O controller, a key signal memory, a plurality of image memories, and a screen refresh address for performing at least image processing and switching of a plurality of images. A counter, and the I /
The image data from the O controller is transferred to a predetermined image memory, the compressed image data from the I / O controller is decompressed and transferred to the image memory, the data in the image memory is processed in a predetermined manner, and the data in the key signal memory is transferred. The data corresponding to the display pixel is processed in a predetermined manner, the data of the predetermined image memory is switched, and the address signal of the image memory is output by the screen refresh address counter to continuously display the image display area by the data of the image memory. A still image reproducing apparatus that is movable in a static manner, in which a first image processor performs predetermined processing on image data from the I / O controller, and an image expansion coprocessor compresses an image from the I / O controller. The data is processed in a predetermined manner, and the second image processor processes the data. In order to control data rewriting of the key signal memory and data output of the screen refresh address counter, the first image processor and the plurality of image memories are connected by a first local bus, and the second image processing is performed. The processor, the key signal memory and the screen refresh address counter are connected by a second local bus, and the first and second
Image processing processor via the host interface to the system bus of the control host processor and the image decompression coprocessor to the second local bus, at least at any time by the control host processor. A still image reproducing device characterized in that each processor is managed and controllable.