JPS60181859A - Control system of collected channel - Google Patents

Abstract

PURPOSE:To reduce the capacity of a microprogram area and improve the processing efficiency of a common control part by writing a branch destination address in an address area which corresponds to the i-th input/output interface in 1:1. CONSTITUTION:A microprogram address area 10 has N-number of address area which correspond to I/O interfaces in 1:1, and the branch destination address is written in the i-th address area if the branch destination address is based on an execution and test instruction for execution of the processing of the i-th I/O interface, and contents of the i-th address area are counted up by +1 if the indication of address +1 is based on a micro instruction for execution of the processing of the i-th I/O interface. If I/O interfaces l-(n) are provided, addresses are read out from the 0th - the second address areas when the value of a time counter becomes 0-2. That is, a micro instruction l0 for execution of the processing of the I/O interface l is executed in the first time slot, and hereafter, the similar processing is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improved control method for an aggregate channel having a common control section and a plurality of I10 interface control sections.

[Prior art and problems]

FIG. 1 is a diagram showing an example of a conventional collective channel, and FIG. 2 is a time chart for explaining its operation. 1st
In the figure, 1-0 to 1-N-1 are interface control units, 2 is a priority circuit, 3 is a microprogram area,
4 indicates a microprocessor, and 5 indicates a microprogram address control section. The interface control unit 1-i (i=0.1.2... or N-1) is an I/
l) Connected to an input/output control device via an interface. The I10 interface consists of a tag in line, a tag bus line, a bus in line, and a bus out line. Requests sent from input/output devices (for example, service-in, data-in, etc.) are input to the priority circuit 2 via the interface control section. Priority circuit 2 is
If there are multiple requests, one of them is selected according to priority and the selected request is sent to the microprogram address control section 5. The microprogram address control section 5 generates an address based on the incoming request and sends this address to the microprogram area 3. Upon receiving this address, the microprogram area 3 reads the microinstruction stored in the storage location specified by this address, and sends the read microinstruction to the microprocessor 4. The microprocessor 4 executes this microinstruction, generates the next address, and sends it to the microprogram address control section 5. Note that parts 2 to 5 constitute a common control section.

21 is a time chart illustrating the operation of the conventional example shown in FIG. 1; For example, the priority circuit 2
If a request from the 0 interface is selected, this request is sent to the microprogram address control unit 5, and the microinstruction 1 is sent from the microprogram area 3. is read out, and this microinstruction 10 is executed by the microprocessor 4. Then microinstruction 1+, i
Jt is executed. At the final step of processing for the th I10 interface, the priority circuit 2 becomes ready to accept requests. Next, when the request from the Mth I10 interface is accepted, the microinstruction m0. m, , m, is executed.

In the final step of processing for the M-th I10 interface, when a request from the N-th I10 interface is accepted, the microinstruction n6 Relais to process this request is executed. In a channel that is connected to an input/output control device through Very often, when a message is sent, the next process is performed. Note that whether or not a response or request has been sent can be determined by checking the state of the tag line. In the conventional aggregate channel, there are many branch instructions to check the status of the tag line, and this useless microprogram area is dedicated to the A separate time slot was needed.

[Purpose of the invention]

The present invention is based on the above consideration, and provides a control method for collective channels that can reduce the capacity of the microprogram area and improve the processing efficiency of the common control unit compared to conventional methods. It is intended to.

[Structure of the invention]

However, the collective channel control method of the present invention is
A microprogram area that stores microprograms including execution and test instructions and reads microinstructions specified by read addresses, a microprocessor that executes the read microinstructions, a branch execution unit, and interface control for multiple units. an input/output interface connected to each interface control unit, a microprogram address area having a plurality of address areas each having a one-to-one correspondence with each of the plurality of interface control units; a counter, a microprogram ψ address control unit that reads an address from an address area specified by the value of the time counter and sends the address to the microprogram area as a read address, an interface control unit that can be specified by the time counter, and the microprogram. and an interface selection unit for connecting with the processor, and if the received microinstruction is an execution & test instruction, the microprocessor executes the normal instruction part of the execution & test instruction by itself. At the same time, the branch instruction part of the execution & test instruction is passed to the branch execution unit, and the branch execution unit executes the received branch instruction part, and if the branch is taken, the branch destination address is written as l:. If the branch destination address is based on an execution & test instruction for the second input/output interface, the microprogram address area will send the branch destination address to the second input/output interface. It is characterized in that it is configured to write to an address area that corresponds one-to-one with the output interface.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention, and FIG. 4 is a block diagram of one embodiment of the present invention.
FIG. 5 is a diagram showing the format of the execution & test instruction used in the present invention and a conventional instruction sequence equivalent to this; FIG. 6 is a diagram showing the execution & test instruction format and FIG. 2 is a diagram showing the execution of a conventional instruction sequence equivalent to this.

In FIG. 3, 6 is a microprogram area, 7 is a microprocessor, 8 is a branch execution unit, 9 is a microprogram address control unit, 10 is a microprogram address area, 11 is an interface selection unit 12 is a time counter control unit are shown respectively. The microprogram area 6 is an area for storing microprograms.

The microinstructions read from the microprogram area 6 are passed to the microprocessor 7. The microprocessor 7 executes the passed microinstruction, and then passes this microinstruction to the branch execution unit 8. When the branch execution unit 8 receives a microinstruction, it checks whether or not this instruction is an execution & test instruction. If it is an execution & test instruction, it checks whether the branch condition is satisfied or not.
In the case of s, the branch destination address is sent to the microprogram address area 10, and if this instruction is a normal microinstruction or the branch condition is not satisfied, the microprogram sends the branch destination address to the microprogram address area 10. - Notify address area 10. The microprogram address area 10 has N address areas that correspond one-to-one with each of the 0th to N-1th I10 interfaces, and has N address areas that are sent from the branch execution unit 8. If the branch destination address is based on the execution & test instruction to execute the processing of the th I10 interface, write this branch destination address to the th address area and write the instruction crab of address + 1 to the th I10 of
If it is based on a microinstruction for executing interface processing, the contents of the 1st address area are incremented by 1. Introducing Time Calantum 1! 4^shi WT'
I'm in trouble.

When the value of the time counter reaches 0, the address is read from the second address area and the microprogram area 6 is read out.
sent to. When the microprogram area 6 receives this address, it reads the microinstruction in the memory location specified by this address and sends it to the microprocessor 7.
send to The interface selection section 11 connects the microprocessor 7 to the interface control section corresponding to the value of the above-mentioned time counter minus one in the next time Φ slot. Note that parts 6 to 11 constitute a common control section.

FIG. 4 is a diagram for explaining the operation of the embodiment of FIG. 3. In the example of FIG. 4, the I10 interface is l,
It is assumed that m and n exist. In this case, the above-mentioned timer/counter becomes a ternary counter, and when the value becomes 0, the address is read from the 0th address area, and when the value becomes 1, the address is read from the 1st address area, and the value When becomes 2, the address is read from the second address area. In the illustrated example, in the first time slot (when the time counter value is 1), the I
10 microinstructions l for processing the interface l. is executed, and in the second time slot, a microinstruction layer for processing the I10 interface m. is executed, in the third time slot the microinstruction rLo for processing the I10 interface is executed, and in the fourth time slot
A microinstruction l for processing the HI10 interface l is executed in the slot. Thereafter, similar processing is repeated.

FIG. 5 shows the format of the execution and test instruction of the present invention and a conventional instruction sequence equivalent thereto.

Figure 5 (b) shows the format of the execution & test instruction of the present invention, where C is the OP code indicating that it is an execution & test instruction, opx is the operand section, and ADR is the branch destination address section. . FIG. 5(a) shows a conventional instruction sequence equivalent to this. OP indicating that A is a normal execution instruction
Code B is an OP code indicating a branch instruction.

Figure 6 (a) shows channel N in the conventional collective channel.
5 shows how the instruction sequence in FIG. 5(a) is executed for First, a normal microinstruction A (microinstruction with OP code A) is executed to process channel N, and then a branch instruction (OP code B) is executed.
microinstruction) is executed and after completing the processing for channel N, in order to perform processing for channel M,
Microinstruction A is executed, followed by microinstruction B.

FIG. 6(B) shows a microinstruction C (FIG.
3 is a diagram illustrating the execution of the microinstruction (b)) and the execution of the microinstruction C for processing the channel M; FIG. First, in the first time slot Φ, the part corresponding to microinstruction A in microinstruction C for channel N is executed by the microprocessor 7, and in the second time slot, the part corresponding to microinstruction A in microinstruction C for channel N is executed by microprocessor 7. The part corresponding to microinstruction B in . . . is executed by the branch execution unit 8.

Furthermore, in the second time slot, the part corresponding to microinstruction A in microinstruction C for channel M is executed by the microprocessor 7, and in the third time slot, the part corresponding to microinstruction A in microinstruction C for channel M is executed by microprocessor 7. The part corresponding to microinstruction B in . . . is executed by the branch execution unit 8.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the microprogram area can be made smaller than in the conventional system, and the processing efficiency of the common control section can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional collective channel, FIG. 2 is a time chart for explaining its operation, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. A time chart to explain the operation of
Figure 6 shows the format of an instruction and a conventional instruction sequence equivalent to it. It is a diagram. 1-0 to 17N-1...interface control unit,
2... Priority circuit, 3... Micro program area,
4...Microprocessor, 5...Microprogram address control unit, 6...Microprogram area, 7...Microprocessor, 8...Branch execution unit, 9...Microprogram address control unit, 1゜...Microprogram address area, 11...
Interface selection section, 12... time counter control section. Patent Applicant: Fujitsu Limited Representative Patent Attorney Yotsube Kyotani

Claims (1)

[Claims] A microprogram area that stores microprograms including execution and test instructions and reads microinstructions specified by read addresses, a microprocessor that executes the read microinstructions, a branch execution unit, and interface control for multiple units. an input/output interface connected to each interface control unit, a microprogram address area having a plurality of address areas each having a one-to-one correspondence with each of the plurality of interface control units; a counter; a microprogram address control unit that reads an address from an address area specified by the value of the time counter and sends the address to the microprogram area as a read address; an interface control unit specified by the time counter; and an interface selection unit for connecting the microprocessor to the microprocessor, and the microprocessor automatically selects the normal instruction part of the execution and test instruction when the received microinstruction is an execution and test instruction. At the same time, the branch instruction part of the execution & test instruction is passed to the branch execution unit, which executes the received branch instruction part, and if the branch is taken, the branch destination address is is sent to the microprogram address area, and if the branch destination address is based on the execution & test instruction for the i-th input/output interface, the microprogram address area sends the branch destination address to the i-th address area. 1. A control method for a collective channel, characterized in that it is configured to write to an address area in one-to-one correspondence with an input/output interface.