JPH0738156B2 - Micro command controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for controlling a plurality of independent external buses by a single micro-instruction control mechanism, and particularly when performing the same processing on a plurality of external buses. The present invention relates to a microinstruction control device suitable for.

2. Description of the Related Art Although there is no document directly describing a device for controlling a plurality of independent external buses by a single microprogram control mechanism, a conventional microinstruction control device for controlling an external bus is described in, for example, National Technical Report. (National Technical Report), Vol.29, p.116 (198
3).

FIG. 3 is a block diagram of this conventional microinstruction control device, in which 1 is a control storage unit for storing a plurality of microinstructions including input / output instructions, and 2 is a microinstruction stored in the control storage unit 1. An address register for selecting one of the words, 3 is a data register for storing the selected microinstruction, 4 is a decoder for generating a control signal according to the microinstruction stored in the data register 3, and 5 is for the external bus 6. A bus controller that controls input and output (hereinafter BTC
7) is a start signal to the bus control device.

In the conventional microinstruction control device configured as described above, when the input / output instruction from the control storage unit 1 is stored in the data register 3, the decoder 4 sends a signal 7 to the BTC 5.
To occur. The BTC 5 controls the external bus 6 when the signal 7 is input.

However, in the above-described configuration, when controlling a plurality of independent external buses, the signal from the decoder 4 and the bus control device are directly connected, and therefore only the types of external buses differ. Since I / O micro-instructions must be prepared and the word length of one word of the micro-instructions becomes long, different I / O micro-programs are required for each external bus, and the amount of control memory is large. Had the problem that

The present invention has been made in view of the above problems of the prior art, and it is an object of the present invention to provide a microinstruction control device capable of coping with input / output control of a plurality of external buses with a small amount of hardware by sharing microprograms.

Means for Solving the Problems The present invention provides a first bus control device for controlling input / output with a first external bus, and a second bus control device for controlling input / output with a second external bus. A control storage unit for storing a plurality of microinstructions including an input / output instruction, a data register for storing an output from the control storage unit, and a microinstruction stored in the data register for decoding the input / output instruction. The mode register includes a decoder for generating a start signal to the first and second bus control devices, and a mode register for indicating which of the first and second bus control devices is the start signal. The decoder is connected to the output of the data register and generates a storage signal to the register when the microinstruction is a data storage instruction to the mode register. Is a micro command controller.

With the above-described configuration, the present invention sets information indicating whether the execution of the input / output instruction is for the first external bus or the second external bus in advance in the mode register. Since which of the two bus control devices is to be activated is decided at the time of executing the input / output instruction, it is possible to share the microprogram which can use the same microinstruction for the input / output operation for the first and second external buses. The control storage unit can be saved.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a microinstruction controller according to the first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a control storage unit for storing a plurality of microinstructions, and 12
Is an address register for selecting one of the microinstructions stored in the control storage unit 11, 13 is a data register for storing the selected microinstruction, and 14 is a data register 13
A decoder for generating a control signal in accordance with a microinstruction stored in a first bus controller (hereinafter referred to as a first BTC) 15 for controlling input / output with respect to a first external bus 16;
Is a start signal generated when the instruction stored in the data register 13 is an input / output instruction, and 18 is a second bus control device (hereinafter referred to as a second BTC) which controls input / output with respect to the second external bus 19.
, 20 is a mode register, 21 is a mode register 20.
To the data line, 22 is the signal stored in the mode register, 23,
24 is the first activation signal 25 for the first BTC 15 and the second BTC
An AND gate for generating a second activation signal 26 for each 18.

The operation of the microinstruction control device of the present embodiment configured as described above will be described below.

When the data setting instruction for the mode register 20 is stored in the data register 13, the decoder 14 generates a storage signal 22 in the mode register 20 and sets a desired value via the data line 21. When the input / output instruction is stored in the data register 13, the decoder 14 generates the activation signal 17 for the BTC.
The gate 23 generates the first activation signal 25 to the first BTC 15 when the activation signal 17 is activated when the state of the mode register is logic "1". The gate 24 generates the activation signal 26 to the first BTC 15 when the activation signal 17 is activated when the state of the mode register is logic "0".

As described above, according to the present embodiment, by providing the mode register indicating which external bus is used,
Input / output operations for two external buses can be controlled by a single microinstruction. In addition, by providing a storage instruction to the mode register in the micro instruction, the mode register can be set with a small amount of hardware.

FIG. 2 is a block diagram of a microinstruction controller according to the second embodiment of the present invention. In the figure, 11 is a control storage unit that stores a plurality of microinstructions, and 12 is a control storage unit 11
Address register for selecting one word of the microinstructions stored in, a data register for storing the selected microinstruction, and a first BTC for controlling input / output with respect to the first external bus 16. , 18 is a second BTC for controlling input / output with respect to the second external bus 19, 20 is a mode register, 21
Is a data line to the mode register 20, 22 is a storage signal to the mode register, and 23 and 24 are AND gates. The above is the same as the configuration of FIG. The difference from the configuration of FIG. 1 is that
AND 27 is a decoder that generates a signal 28 at the time of the first input / output instruction, a signal 29 at the time of the second input / output instruction, and a signal 17 at the time of the third input / output instruction. Gate 23
OR gate 30 which generates the first activation signal 25 for the first BTC 15 by taking the logical OR of the output of and the signal 28, and the second BTC 1 by taking the logical OR of the output of the AND gate 24 and the signal 29.
The point is that an OR gate 31 for generating the activation signal 26 for 8 is provided, and the second BTC 18 generates a signal 32 for waiting the execution of the microinstruction when activated.

The operation of the microinstruction control device of the second embodiment configured as described above will be described below.

When the first input / output instruction is stored in the data register 13, the decoder 27 generates the signal 28, and the first signal is output via the OR gate 30.
The start signal 25 is given to the BTC 15 to execute the input / output operation with the external bus 16. When the second input / output instruction is stored in the data register 13, the decoder 27 generates a signal 29, gives a start signal 26 to the second BTC 18 via the OR gate 31, and executes an input / output operation with the external bus 19. To do. When the third input / output instruction is stored in the data register 13, the decoder 27 generates the signal 17, and when the state of the mode register is logical "1", the start signal 25 is generated to the first BTC 15. When the state of the mode register is logical "0", the activation signal 26 is generated for the second BTC 18. When the activation signal 26 is input, the second BTC 18 generates a wait signal so that the microinstruction control mechanism does not shift to the execution of the next microinstruction until the input / output operation on the external bus 19 is completed.

As described above, according to the second embodiment, by providing a dedicated input / output instruction for each external bus, it is possible to execute the processing unique to the specific external bus without setting the mode register. Further, by waiting for the execution of the microinstruction as much as necessary by the waiting signal 32 from the second BTC 18, it is possible to easily control the external buses having different speeds.

In addition, in the first and second embodiments, the case of two sets of external buses is shown, but any number of sets may be used.

Effects of the Invention As described above, according to the present invention, it is possible to control input / output of a plurality of independent external buses with a small amount of hardware,
Its practical effect is great.

[Brief description of drawings]

1 is a block diagram of a microinstruction control device according to the first embodiment of the present invention, FIG. 2 is a block diagram of a microinstruction control device according to another embodiment of the present invention, and FIG. 3 is a conventional microinstruction control. It is a block diagram of an apparatus. 11 ... Control storage unit, 13 ... Data register, 14 ... Decoder,
15 ... First BTC, 17 ... BTC activation signal, 18 ... Second BTC, 20
… Mode register.

Claims (2)

[Claims] 1. A first for controlling input / output to / from a first external bus
Bus controller, a second bus controller for controlling input / output to / from the second external bus, a control storage unit for storing a plurality of microinstructions including input / output instructions, and an output from the control storage unit. A data register for storing the data, a decoder that decodes the microinstruction stored in the data register, and generates an activation signal to the first and second bus control devices in the case of an input / output instruction, and the activation signal is the first, A mode register for indicating to which of the second bus control devices the activation signal is sent, the mode register is connected to the output of the data register, and the decoder is a microinstruction for storing a data in the mode register. A microinstruction control device, characterized in that it is sometimes a decoder that generates a store signal for a register. 2. A microinstruction stored in a control storage unit includes first, second and third input / output instructions, and the first input / output instruction is an input / output instruction for the first bus controller. ,
The second input / output instruction is an input / output instruction for the second bus controller, and the third input / output instruction is an input / output instruction for either the first or second bus controller according to the contents of the mode register. The microinstruction control device according to claim 1, wherein the microinstruction control device is an output instruction.