JPH04346128A - Device and method for data processing - Google Patents

Abstract

PURPOSE:To shorten the decoding time of microinstructions which have plural instruction forms. CONSTITUTION:An F field for specifying the instruction form of a microinstruction to be executed next is provided in all microinstruction words stored in a control storage part 1. The address (A field) of the microinstruction to be executed next and the F field are set in a microaddress register 4 and the instruction word is set in a microinstruction register 2 according to the microinstruction form. Consequently, the form of the microinstruction to be executed next can be known in a microinstruction read cycle and the microinstruction decoding time in the interpreting and executing cycle of the microinstruction can be shortened to shorten the machine cycle of the processor.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is in the field of information processing, and relates, for example, to a data processing device using microprogram control and a processing method thereof.

0002

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional microprogram control system in a data processing device. 2F is a micro-F field that specifies the format of the micro-instruction word currently held in micro-instruction register 2; 2A is a micro-instruction register that holds the micro-instruction word read from control storage section 1; 2M is a micro-A field that specifies the address of the micro-instruction to be executed; 2M is a micro-M field in which the controlled object, the type of micro-operation, etc. change based on the specification of the micro-F field in the micro-instruction word currently held in the micro-instruction register; 3 is a selector that selects the address to access control storage unit 1 next, 4 is a micro address register that holds address information for accessing control storage unit 1, 5 and 6 are logical AND gates, and 7 and 8 are micro F fields. 9 is a micro decoder that performs decoding by changing the meaning of the micro M field based on the specification of the micro F field.
Micro M field 2M when field 2F is zero
10 is the controlled object Y specified by the micro M field 2M when the micro F field 2F is 1, 11 is the micro entry address register for specifying the start of processing in the micro program, 1
2 is a microinterrupt register for starting interrupt processing for the microprogram.

In general, in the horizontal microprogram control system, a microfield corresponding to each hardware function block to be controlled is provided independently to form a microinstruction word. By doing so, the microinstruction words can be decoded in units of independent microfields, and the decoding time is shortened compared to microinstructions in vertical microprograms. On the other hand, however, since each microfield is provided independently for each functional block to be controlled, it has a characteristic that when there are many functional blocks to be controlled, the number of bits constituting a microinstruction increases. An increase in the number of bits in a microinstruction increases the number of parts constituting the control storage section 1, which has a large impact on the floor plan, especially in the case of a one-chip LSI with severe area constraints. As a method to reduce the word width of a horizontal microprogram, micro-operations that are exclusively used in a micro-instruction are grouped and placed in the same position in the micro-instruction (for example, the micro-M field in Figure 2). ), it is well known to provide microinstruction format designating means (for example, the microF field in FIG. 2) for specifying which exclusive microoperation group the current microinstruction refers to.

Next, the operation will be explained based on the drawings. One microinstruction word read from the control storage section 1 using the address set in the microaddress register 4 is set in the microinstruction register 2 in the next cycle. The micro-instruction word set in the micro-instruction register 2 is specified by the micro-A field 2A to the address of the control storage unit 1 in which the next micro-instruction word to be executed is stored. That is, the value of the micro A field 2A is passed through the selector 3 and set in the micro address register 4. On the other hand, the micro F field 2F specifies the instruction format of the micro instruction word currently set in the micro instruction register 2. Specifically, Micro F field 2F
specifies the type of micro-operation in the micro-M field 2M. If the micro F field 2F is zero, the logical AND gate 5 is opened and the value of the micro M field 2M is input to the micro decoder 7. The micro-operations specified in the micro-M field 2M are decoded by the micro-decoder 7 and then transmitted to the controlled object X9 as individual control signals. At this time, the logical AND gate 6 is closed and zero is transmitted to the micro decoder 8 instead of the value of the micro M field 2M, so the micro decoder 8 outputs the initial value and the controlled object Y10
doesn't work. If the micro F field 2F is 1, the logic AND gate 6 is open;
is closed, the controlled object Y10 operates according to the value of the micro M field 2M, and the controlled object X9 does not operate.

When this data processing device starts microprogram control processing, the address information of the microinstruction to be executed in the first cycle is set from the microentry address register 11 to the microaddress register 4 through the selector 3. Ru. The subsequent operations are the same as described above.

Furthermore, when starting interrupt processing for a microprogram, a microvector address at which to start microinterrupt processing is set from the microinterrupt register 12 into the microaddress register 4 through the selector 3. The subsequent operations are the same as described above.

[0007]

[Problems to be Solved by the Invention] As mentioned above, the reading of microinstructions from the control storage unit and the interpretation and execution cycle of the microinstructions are usually processed in parallel as a pipeline, but in general, the reading of microinstructions is Compared to microinstructions, the interpretation and execution of microinstructions involves processing that takes longer, such as the transfer of arithmetic units and operation result data. In conventional microprogram control systems that have multiple formats of microinstructions, a means for specifying the microinstruction format is stored in the microinstruction word to be currently executed. The microinstruction format is known only after the Therefore, in the path from decoding the microinstruction word in the microinstruction register to determining the operation of the controlled hardware, decoding selection and activation/enablement are performed according to the microinstruction format.
This has the disadvantage that a circuit for performing an invalid operation is inserted, which slows down the control signal generation speed. Normally, microprograms control various arithmetic units that require high-speed operation, memory request issuing processing, etc., and this drawback is a critical path in recent data processing devices that are trying to shorten machine cycles to improve performance. There is a high possibility that it will be one of the

The present invention has been made to solve the above-mentioned problems, and eliminates the delay in the generation of control signals due to decoding operations for each microinstruction format even in a microprogram control system having multiple instruction formats. The purpose is to

[0009]

[Means for Solving the Problems] A data processing device according to a first aspect of the invention is provided with a field in an instruction word for specifying the instruction format of the instruction word to be executed next, and has the following elements. It is something. (a) A control storage unit that stores command words having the following elements (a1) Command information written in one of multiple types of command formats and executed to control the operation of the controlled object, (a2 ) Instruction format specification information that specifies the instruction format of the instruction information to be executed next, (
b) Execution means for executing the instruction information of the instruction word in the control storage unit based on the instruction format specified by the instruction format designation information of the previously executed instruction word.

[0010] Furthermore, the data processing device according to the second invention is capable of specifying the command format of the command word to be executed first even at the start of a predetermined process, and has the following elements. be. (a) A control storage unit that stores an instruction word written in one of a plurality of instruction formats; (b) A control storage unit that stores an instruction word written in one of a plurality of instruction formats; (b) Specifies the instruction word to be executed first for a predetermined process and the instruction format of that instruction word. (c) processing start specifying means for specifying a command word specified by the processing start specifying means;
Execution means that executes based on the instruction format of the instruction word specified by the processing start specification means.

Further, a data processing method according to a third aspect of the invention includes the following steps. (a) A control storage step for storing an instruction word having instruction information written in one of a plurality of instruction formats and instruction format designation information specifying the instruction format of the instruction information to be executed next. , (b) a setting step in which the address information of the next instruction to be executed and the instruction format designation information of the already executed instruction are set in a register; (c) the address information set in the setting step sets the next instruction to be executed. an execution step of selecting an instruction word to be used and executing the instruction information of the instruction word based on the instruction format designation information set in the setting step;

0012

[Operation] In the first invention, since the instruction format designation information specifies the instruction format of the next instruction to be executed, the instruction This means that the instruction format of is already known. Since the execution means can process the instruction word based on this already known instruction format, the delay of the instruction decoding section during the instruction execution cycle can be shortened.

Further, in the second invention, the processing start specifying means specifies the instruction format of the instruction word to be executed at the beginning of a predetermined process such as system startup processing when power is turned on or interrupt processing when an interrupt occurs. Therefore, the instruction format can be determined without delay even when switching to startup processing or interrupt processing, where processing sequence control is not directly performed by instruction words.

Furthermore, in the third invention, since the setting step sets the address information of the instruction word to be executed next and its instruction format in advance in the register, the execution step sets the instruction word based on the instruction format. Because the process is executed, the execution process becomes faster.

[0015]

[Example] Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a control storage unit 1 that stores microprograms having multiple instruction formats, and 1F is an F in a microinstruction word stored in the control storage unit 1.
field, 1A is the A field in the microinstruction word stored in the control storage unit 1, 1M is the M field in the microinstruction word stored in the control storage unit 1, 2
2F is a micro-instruction register that holds the micro-instruction word read from the control storage unit 1; 2F is a micro-F field that is included in the micro-instruction register 2 and specifies the instruction format of the micro-instruction word to be executed next; 2A is a micro-F field A micro-A that specifies the address of the micro-instruction word contained in the micro-instruction register 2 and to be read next from the control storage section 1;
field, 2M1 is a micro M1 field for controlling the operation of the controlled object
3 is a selector that selects the next address to access control storage unit 1, 4 is a micro address register that holds address information for accessing control storage unit 1, and 4F is a micro address. Next microinstruction format specification information included in register 4 and specifying the instruction format of the microinstruction word read from control storage unit 1; 5 and 6 are logical AND gates; 7 and 8 are microdecoders; 9 is microM1 field 2
Controlled object X, 10 whose operation is specified by the contents of M1
is a controlled object Y whose operation is specified by the contents of the micro M2 field 2M2, 11 is a micro entry address register for specifying the start of processing to the micro program, and 11F is a micro entry address register 11
micro-entry instruction format designation information that specifies the instruction format of the micro-instruction word that is included in the control storage unit 1 and is read out next from the control storage unit 1; 12 is a micro-interrupt register for activating a micro-interrupt for the micro program;
12F is microinterrupt entry instruction format designation information that is included in the microinterrupt register 12 and designates the instruction format of the first microinstruction word to be executed at the start of microinterrupt processing.

Further, 20 is an execution means for reading and executing a command word stored in the control storage unit 1; 21 is a process start specifying means for designating a command word for starting a predetermined process such as startup processing or interrupt processing; 30 is a setting step in which the address information and instruction format of the instruction word to be executed next are set in the microaddress register 4; 40 is a setting step in which the address information and instruction format of the instruction word to be executed next are set; This is the execution step of reading and executing the .

Next, the operation in an embodiment of the present invention is shown in FIG.
The explanation will be based on. The micro A field 2A in one microinstruction word set in the microinstruction register 2 in a certain cycle specifies the address of the microstep to be executed in the next cycle, and selector 3
The micro address register 4 is set through the micro address register 4. At the same time, the micro F field 2F in the micro instruction register 2 specifies the instruction format of the next micro instruction word to be executed, and similarly to the micro A field 2A, the next instruction in the micro address register 4 passes through the selector 3. Set in microinstruction format specification information 4F. Thereafter, one microinstruction word to be executed in the next cycle is read from the control storage section 1 according to the address indicated by the microA field 2A set in the microaddress register 4. The F field 1F and A field 1A in the micro instruction word read from the control storage section 1 are set in the micro F field 2F and micro A field 2A in the micro instruction register 2, respectively, in the next cycle. On the other hand, the M field 1M read from the control storage 1 becomes an input to the logical AND gates 5 and 6. now,
Assuming that the value of the next microinstruction format specification information 4F in the microaddress register 4 is zero, the logical AND gate 5 is opened and the logical AND gate 6 is closed. That is, the M field read from the control storage 1 is set in the micro M field 2M1 in the microinstruction register 2, and zero is set in the micro M2 field 2M2 in each subsequent cycle. On the other hand, the value of next microinstruction format specification information 4F in microaddress register 4 is 1.
When , the logical AND gate 5 is closed and the logical AND gate 6 is opened, so that in the next cycle, zero is set in the micro M1 field 2M1, and the value of the M field 1M is set in the micro M2 field 2M2. That is, the next microinstruction word to be executed is set in the microinstruction register 2 according to the instruction format designated by the microF field 2F in the microinstruction register 2 to be executed in the previous cycle. The micro decoder 7 that decodes the value of the micro M1 field 2M1, the controlled object X9, and the micro M
Since the microdecoder 8 that decodes the value of the second field 2M2 and the controlled object Y10 have the same functions as the same reference numerals in FIG. 3 showing the prior art, a description of their operations will be omitted here.

When this data processing device starts microprogram control processing, the address information of the microinstruction to be executed in the first cycle is set from the microentry address register 11 to the microaddress register 4 through the selector 3. Ru. At the same time, the micro-entry instruction format designation information 11F is also passed through the selector 3 and set to the next micro-instruction format designation information 4F in the micro-address register 4. The subsequent operations are the same as described above. Furthermore, when starting interrupt processing for a microprogram, a microvector address at which to start microinterrupt processing is set from the microinterrupt register 12 into the microaddress register 4 through the selector 3. At the same time, the microinterrupt entry instruction format designation information 12F is also passed through the selector 3 and set to the next microinstruction format designation information 4F in the microaddress register 4. The subsequent operations are the same as described above.

Next, a specific example will be explained using FIG. When this data processing device starts microprogram control processing, it refers to the address of the microinstruction to be executed = 0000 from the microentry address register 11 and the microentry instruction format information 11F = 0, and
Start execution from 000. At address 0000 of control storage unit 1, F field = 0 A field = 0001 M field = 00000 are stored, but micro entry instruction format information 1
Since 1F=0, M field=00000 is set in micro M1 field 2M1 and processed. Then, the next address to be executed is A field = 0001, so address = 0001 will be executed, but F field of address = 0000 =
0 indicates the format of the M field at address = 0001, so M field at address = 0001 = 1
1000 is processed in micro M1 field 2M1. Next executed address=0002 M field=
Since 11110 has address=0002 and F field=1, it is processed in micro M2 field 2M2.

Here, for example, as an interrupt process, I
Assuming that NT1 occurs, the address of control storage unit 1 = 1100 held in INT1 of microinterrupt register 12 and microinterrupt entry instruction format specification information 12F = 0
1100 will be executed. Address=1100
, F field = 1 A field = 1101 M field = 00111 are stored, and M field = 00111 is microinterrupt entry instruction format specification information 12F = 0
Therefore, it is processed in the micro M1 field 2M1. Also, M of the next execution address (A field = 1101)
Since field=10111 is F field=1 with address=1100, it is processed in micro M2 field 2M2.

As described above, in this embodiment, a microprogram consisting of microinstruction words of a plurality of formats, a control storage unit that stores the microprogram and reads out the microinstruction words in units of microinstruction words, and A data processing apparatus has been described which includes a field for specifying the instruction format of a microinstruction word to be executed next. Also,
Information that includes processing start designation means for starting predetermined processing such as startup processing and interrupt processing for the microprogram, and designates the instruction format of the microinstruction word that is executed first during the processing start designation means. A data processing device having the following has been described.

Example 2. In the above embodiment, an example was shown in which the definition of M field 1M is switched by F field 1F, but the definition of multiple microfields or all microfields except F field 1F may be switched, and in these cases. The same effects as in the above embodiment can also be achieved. Further, although the case where there are two instruction formats in which the F field is 0 or 1 has been shown, it is also possible to have three or more instruction formats.

Example 3. Furthermore, although the above embodiments have shown the case of micro-instructions, it is not limited to micro-instructions, and may be other programming languages or processing instructions.

[0024]

As described above, according to the first invention, since the instruction word is provided with a field for specifying the instruction format of the next instruction word to be executed, the instruction decoding during the instruction execution cycle during program execution is possible. This makes it possible to shorten the delay in the section regardless of the instruction format, which in turn makes it possible to shorten the machine cycle.

Further, according to the second invention, since the processing start designation means is provided with information that designates the command format of the command word to be executed first, it can be used in conjunction with the data processing device according to the first invention. This makes it possible to speed up the instruction execution cycle for all instruction words.

Furthermore, according to the third invention, since the instruction format of the instruction word is specified in advance in the setting step, the processing speed in the execution step can be increased.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a microprogram control method in a data processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing specific processing of the present invention.

FIG. 3 is a circuit diagram showing a microprogram control method in a data processing device by a conventional data processing device.

[Explanation of symbols]

1 Control storage unit 2F Micro F field (an example of instruction format designation information) 11F Micro entry instruction format designation information 12F
Microinterrupt entry instruction format specification information 20 Execution process 21 Processing start specification means 30 Set process 40 Execution process

Claims (3)

[Claims] Claim 1: A data processing device (
a) A control storage unit that stores command words having the following elements (a1) Command information written in one of multiple types of command formats and executed to control the operation of the controlled object, (a2) (b) instruction format specification information specifying the instruction format of the instruction information to be executed next; (b) the instruction format specified by the instruction format specification information of the previously executed instruction word; Execution means to be executed based on. Claim 2: A data processing device (
a) A control storage unit that stores an instruction word written in one of a plurality of instruction formats; (b) A control storage unit that specifies the instruction word to be executed first for a predetermined process and the instruction format of that instruction word. (c) execution means for executing the instruction word specified by the processing start specifying means based on the instruction format of the instruction word specified by the processing start specifying means; Claim 3: A data processing method comprising the following steps (
a) a control storage step of storing an instruction word having instruction information written in one of a plurality of instruction formats and instruction format designation information specifying the instruction format of the instruction information to be executed next; (b) a setting step of setting the address information of the next instruction to be executed and the instruction format designation information of the already executed instruction in a register; (c)
An execution step of selecting an instruction word to be executed next based on the address information set in the setting step, and executing the instruction information of the instruction word based on the instruction format designation information set in the setting step.