JPS56105543A - Microprogram controlling system - Google Patents
Microprogram controlling systemInfo
- Publication number
- JPS56105543A JPS56105543A JP782380A JP782380A JPS56105543A JP S56105543 A JPS56105543 A JP S56105543A JP 782380 A JP782380 A JP 782380A JP 782380 A JP782380 A JP 782380A JP S56105543 A JPS56105543 A JP S56105543A
- Authority
- JP
- Japan
- Prior art keywords
- mode
- time
- single mode
- mupg
- mff10
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To enable processing of multiplex mode and single mode to be easily executed by providing a mode of assigning whether time-division multiplex mode or single mode at a microprogram muPG level and setting the store area of data. CONSTITUTION:A bit for assigning whether time-division multiplex mode or single mode is provided in the contents of a control memory CM1 which stores muPG. The contents of the CM1 are read out to a control memory data register CMDR3, and at the time of the multiplex mode, an FFMFF10 is set and at the time of the single mode, an MFF10 is reset. When the mode assignment bit is 1, the MFF10 goes ON, and the output of a time slot counter TSC9 passes a gate G1, and stores the operation data corresponding to lower devices into the area corresponding to the devices of a register REG. When the mode assignment bit is zero, the MFF10 goes OFF, and stores the data as the single mode into the area of the REG based on the control information of the muPG via a gate G2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP782380A JPS56105543A (en) | 1980-01-28 | 1980-01-28 | Microprogram controlling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP782380A JPS56105543A (en) | 1980-01-28 | 1980-01-28 | Microprogram controlling system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56105543A true JPS56105543A (en) | 1981-08-22 |
Family
ID=11676310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP782380A Pending JPS56105543A (en) | 1980-01-28 | 1980-01-28 | Microprogram controlling system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56105543A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60181859A (en) * | 1984-02-28 | 1985-09-17 | Fujitsu Ltd | Control system of collected channel |
-
1980
- 1980-01-28 JP JP782380A patent/JPS56105543A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60181859A (en) * | 1984-02-28 | 1985-09-17 | Fujitsu Ltd | Control system of collected channel |
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