JPS5730170A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS5730170A
JPS5730170A JP10330380A JP10330380A JPS5730170A JP S5730170 A JPS5730170 A JP S5730170A JP 10330380 A JP10330380 A JP 10330380A JP 10330380 A JP10330380 A JP 10330380A JP S5730170 A JPS5730170 A JP S5730170A
Authority
JP
Japan
Prior art keywords
buffer memory
access
control
control system
memory control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10330380A
Other languages
Japanese (ja)
Inventor
Akihiko Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10330380A priority Critical patent/JPS5730170A/en
Publication of JPS5730170A publication Critical patent/JPS5730170A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To perform jobs efficiently by selectively controlling whethr a buffer memory is used or not for accessing to a storing means. CONSTITUTION:A buffer memory means 5 of controlling a buffer memory 4 and a register 6 for control are provided. For access to a storing means 2 on the basis of control information entered in the control register 6, a buffer memory controller 5 refers to a control table for information on whether the access destination is set in the buffer memory 4 or not. When it is not in the buffer memory 4, access to an access storage device DADS1 is attained to set it in the buffer memory 4 or to store it in the storage device 2 directly.
JP10330380A 1980-07-28 1980-07-28 Buffer memory control system Pending JPS5730170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10330380A JPS5730170A (en) 1980-07-28 1980-07-28 Buffer memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10330380A JPS5730170A (en) 1980-07-28 1980-07-28 Buffer memory control system

Publications (1)

Publication Number Publication Date
JPS5730170A true JPS5730170A (en) 1982-02-18

Family

ID=14350463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10330380A Pending JPS5730170A (en) 1980-07-28 1980-07-28 Buffer memory control system

Country Status (1)

Country Link
JP (1) JPS5730170A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6048553A (en) * 1983-08-25 1985-03-16 Fujitsu Ltd Performance evaluating system of disk cache
JPS6242247A (en) * 1985-08-20 1987-02-24 Fujitsu Ltd Cache memory control system
JPH0268639A (en) * 1988-09-02 1990-03-08 Hitachi Ltd Disk cache control system and information processing system
JPH0287242A (en) * 1988-09-26 1990-03-28 Hitachi Ltd Saving and recovering system for data base
JPH02191714A (en) * 1989-01-18 1990-07-27 Toray Ind Inc Anti-pilling fiber dyeable at normal pressure
JPH0460730A (en) * 1990-06-28 1992-02-26 Nec Corp Cache control system
EP1130590A2 (en) * 2000-03-03 2001-09-05 Hitachi, Ltd. High reliability storage drive and data write method
US8612685B2 (en) 2007-10-11 2013-12-17 Nec Corporation Processor, information processing device and cache control method of processor

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6048553A (en) * 1983-08-25 1985-03-16 Fujitsu Ltd Performance evaluating system of disk cache
JPS6242247A (en) * 1985-08-20 1987-02-24 Fujitsu Ltd Cache memory control system
JPH0268639A (en) * 1988-09-02 1990-03-08 Hitachi Ltd Disk cache control system and information processing system
JPH0287242A (en) * 1988-09-26 1990-03-28 Hitachi Ltd Saving and recovering system for data base
JPH02191714A (en) * 1989-01-18 1990-07-27 Toray Ind Inc Anti-pilling fiber dyeable at normal pressure
JPH0460730A (en) * 1990-06-28 1992-02-26 Nec Corp Cache control system
EP1130590A2 (en) * 2000-03-03 2001-09-05 Hitachi, Ltd. High reliability storage drive and data write method
EP1130590A3 (en) * 2000-03-03 2003-07-16 Hitachi, Ltd. High reliability storage drive and data write method
US7031092B2 (en) 2000-03-03 2006-04-18 Hitachi Global Storage Technologies Japan, Ltd. High reliability storage drive and data write method
US8612685B2 (en) 2007-10-11 2013-12-17 Nec Corporation Processor, information processing device and cache control method of processor

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