JPS60110036A - Method for obtaining maximum value of array element and number of maximum element - Google Patents

Abstract

PURPOSE:To decrease the number of steps of a program and to attain high-speed processing by obtaining the maximum value of the array element and the maximum element number with a single instruction. CONSTITUTION:This method contains three steps. In the 1st step, the array elements are read out of a main memory according to an instruction word containing an operation code field, an inter-element distance designation field and an element number designation field. In the 2nd step, the maximum value among the elements counted up to the i-th place of the read-out array elements is stored in the 1st holding means and the corresponding element number is stored in the 2nd holding means respectively. The contentes of the 1st holding means are compared with the (i+1)th element. When the latter is larger than the former, the latter value is stored in the 1st holding means together with the corresponding element number stored in the 2nd holding means. In the 3rd step, the contents of the 1st holding means are stored in the 1st register with the contents of the 2nd holding means stored in the 2nd register respectively when the procedure is through with the n-th element.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for calculating the maximum value of array elements and the element number of the maximum element for array data stored in the main memory of an information processing system.

Conventional technology In the past, array data was very often handled in scientific and technological calculations. In the system, this is achieved by looping a specific instruction sequence using repeated all branch instructions.

However, in this method, IElffi is not fast at execution because there is a delay due to waiting for the index register to be finalized, etc., and extra instructions such as branch instructions are required. One way to eliminate this is by using instructions that specialize in array data, so-called vector instructions.These vector instructions perform operations on one array in one instruction, and also include branch instructions for loop control, It is possible to perform Hama W at high speed because it takes a long time to wait for the index register to be confirmed1.
Among operations on array data, operations that calculate the maximum value of the elements of array data or the element number of the largest element are also often used. For example, when executing the problem "In two arrays A and B with the same number of elements, replace the element with the maximum value of the array user with the corresponding transene of array B", the element number of the maximum element is It is necessary to There are also cases where the maximum value of an array element itself is required. However, in conventional vector instructions, the maximum value of an array element and the element number of the maximum element cannot be determined at the same time, resulting in the following drawbacks. In other words, the above-mentioned "element replacement" operation cannot be performed with an instruction that only calculates the maximum value. Furthermore, since the maximum value itself is not fitted in an instruction to only read the element number of the largest element, if the maximum value itself is required, it is necessary to read the corresponding element from the main memory based on the fitted element number.

OBJECTS OF THE INVENTION In order to solve the above-mentioned drawbacks, an object of the present invention is to provide a flexible array data calculation method by calculating the maximum value of array elements and the element number of the maximum element in one instruction. .

Structure of the Invention The method of calculating the maximum value of an array element and the element number of the maximum element according to the present invention is as follows: An operation code field that specifies the type of speech, and an address specification field and element that specifies the address of the first element of the array. a first step of reading array elements from the main memory according to a command word having an inter-element distance specification field that specifies the distance between the elements and an element number specification field that specifies the number n of elements to be operated on; The first array element read in (
+"1, 2e..., n) is stored in the first holding means, the element number of the element having the maximum value is stored in the second holding means, and the Compare the contents of the first holding means and the (i+1)th element.
)th element has a larger value, a second step of storing that value in the first holding means and storing the element number of the (i+1)th element in the second holding means; and a third storing the contents of the first holding means in the first register when the comparison up to the n-th element is completed, and further storing the contents of the second holding means in the second register. From the step of 10,000.

Embodiment of the Invention Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, an information processing apparatus embodying the method of the present invention includes a main memory 1, a memory buffer unit 2, selectors 3 and 13, and registers 4*5.
It consists of *8, 9*11 and 13, a comparison circuit 6, a control unit 7, and an AND gate 10.

The main storage device 1 stores programs and data. Data is written into the main memory device through a signal line 101, and its contents are read out through a signal line 102. The memory buffer unit 2
is a unit that performs read access and write access to the main memory device l. The data read from the main storage device 1 is stored in a memory buffer unit 2.
In addition to being outputted to the signal line 103 via the selector 3 and transferred to the register 4, it is also transferred directly to the register 5 via the bar code line 103. The comparison circuit 6 compares the contents of the register 4 and the contents of the register 5, and outputs the result to the signal line 108. That is, the register 4
If the value stored in the register 5 is thicker than the value stored in the register 5, the signal line 108 becomes "1".

The control unit 7 is a unit for controlling each circuit shown in FIG. 1 by the method of the present invention.

-7° Referring to FIG. 4, the control unit includes an instruction prefetch control circuit 701. Instruction prefetch buffer 702, first instruction register 703, tm2 instruction register 704. Index register file 705° selectors 706 and 707. Effective address adder 7osJJ+address register 709. Base address register 710. Base address adder 711, virtual address register 712
．． Microaddress control circuit 713. Control memory 714.
Microinstruction register 715y'B prime number register 716
and a zero detection circuit 717.

Next, the operation of this control circuit 7 will be explained in detail.

When the instruction prefetch control circuit 701 outputs a request to read out the number of instruction words to the memory buffer unit 2 via the signal line 116, the instruction words are read out via the signal line 117 in response, and the instruction prefetch buffer 702. Instruction words to be processed are sequentially read from the instruction prefetch paner 702. If the read instruction is an instruction of the present invention, the first candy of the instruction is set in the first instruction register 703 and the second candy of the instruction is set in the second QJ instruction register 704. The effective address at the beginning of the array data is the value of the instruction word Kutsuild, there are a total of 8 registers, and the index register file 7
It is stored in 05. Further, the effective address generated by the effective address request or revocation address adder 708 is stored in the effective address staff 09.

The contents of the effective address register 709 are added to the contents of the base address register 710 by a base address adder 711 and stored in the virtual address register 712.

The contents of virtual address register 712 are sent to memory buffer unit 2 by signal line 118. In the memory buffer unit 2, the edges that have undergone address conversion are used as read addresses for array elements. Generation of read addresses for the second and subsequent elements is achieved by adding the ■□xtwield value of the instruction word to the address of the previous element. This addition is performed by an effective address adder 708, and switching of its input is performed by selectors 706 and 707.

On the other hand, it is sent to the OP command yield microaddress control circuit 713 of the IN command register 703.

The micro-address control circuit 713 generates the start address of the micro-instruction corresponding to the operation code, reads out the micro-instruction from the control memory 714, and sets it in the micro-instruction register 715. Subsequent reading of the microinstruction is performed based on the information in the branch control field of the microinstruction. Second instruction register 704
The number of elements of the array data is stored in the index register specified by the RN yield, and the number of elements register 716 is set to this value. Element number register 71
The value of 6 is counted down by 1 each time the processing of the first element is completed, and reaches zero when the processing of all the elements is completed. This is detected by the zero detection circuit 717, sent to the microaddress control circuit 713, and used as the microinstruction branch condition. The contents of the register 8 are incremented by lJ according to instructions from the control unit 7. The output of the register 8 is set to the register 9 according to instructions from the control unit 7. The contents of the register 4 are set to the register 11. The contents of the register 9 are set in the register 12.The contents of the registers 11 and 12 can be switched by the selector 13 and written to the main storage device 1 via the memory buffer unit 2. can.

The processing operations for determining the maximum value and maximum element of the array data stored in the main memory 1 according to the method of the present invention are shown in the flowchart of FIG. 2, and are performed in the following order. When a command word retrieval request is sent from the control unit 7 to the memory buffer unit 2 via the signal line 116, the command word of the command to be executed is read from the main memory device 1. The read command word is sent to the control unit 7 via the memory buffer unit 2 and the signal line 117. The control unit 7 decodes the instruction word taken out. Now, consider a case where the retrieved instruction word indicates an instruction to find the maximum value and maximum element of an array element using the method of the present invention. This instruction word has a length of 2 words (=72 bits) and has a format as shown in FIG. In FIG. 3, OF is an operation code field that specifies the type of operation. y is an address field for specifying the start address of an array element, the address modification specified by MP is applied to the value of y, and the resulting value represents the start address of the element. V specifies the difference in addresses between adjacent elements, that is, the distance between elements, and RN specifies the register in which the number of elements is stored. When this instruction is decoded by the control unit 7, the first The address of the element is calculated, and the first @element is read from the address of the calculation result. Reading of the leading element is performed in the main memory 1 in the same way as reading of the instruction word.
The read data is set in the registers 4 and 5 via the signal line 1o3r. At this time, the selector 3 is controlled via the signal line 105 to select the signal on the signal line 103. Since the element number starts from "0", register 8 is cleared to "0" when the first element is set in registers 4 and 5, and is incremented by "1" every time an element is read from then on. . The address of the second element (element number "1") is obtained by adding the inter-element distance to the address of the first element.

The second element is read from the address of the main memory 1 obtained in this way and set in the register 5. Control of this register 4 is performed as follows. That is, the comparison circuit 6 compares the contents of the register 4 and the register 5, and if the value of the data stored in the register 5 is greater, the value of the signal line 108 becomes "1". Further, the selector 3 is controlled to select the state of the signal line 104, that is, the contents of the register 5. When the second element is set in register 5, the contents of signal line 106 (register 5
set signal) becomes "1", but at this time, the signal line 10
The content of 7 is also "1". The contents of the signal line 107 and the contents of the signal line 108 are ANDed by the AND gate 10. If the content of the signal line 109, which is the AND result, is "1", the content of the register 5 is transferred to the register 4, and the content of the register 8 is transferred to the register 9. Similarly, the third to nth elements are read out in order, and the above-described process is repeated. In this way, the value finally stored in register 4 is the maximum value among the values of n elements, and is stored in register 9.
・The value is determined by the element number starting from "0" of the element with the maximum value.

The contents of register 4 are further transferred to register 11, the contents of register 9 are transferred to register 12, and the instruction ends. The contents of registers 11 and 12 are transferred to memory buffer unit 2 via signal line 115 and can be written to main memory 1 as well as used by other instructions.

The present invention has the advantage that since the maximum value of array elements and the element number of the maximum element can be determined with one instruction, the number of program steps can be reduced, and therefore processing can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the circuit shown in FIG. 1, and FIG. 3 shows the format of a command word for instructing the operation shown in FIG. and FIG. 4 are diagrams showing the detailed configuration of the control unit 7. 1. In FIGS. 1 to 4, 1. Main storage device, 2. Nofuhetufa unit, 3,13
...Selector, 4 t 5 t 8 = 9
* 11 t 12...Register, 6...
... Comparison circuit, 7 ... Control unit, 10.
......AND gate, 701...Instruction prefetch control circuit, 702...Instruction prefetch buffer,
703...First instruction register, 704...
...Second instruction register, 705...Index register file, 706゜707...SeV
effective address adder, 709
・・・・・・Effective address register, 71°・・・・・・
・Base address register, 711...Pace address adder, 712...Virtual address register, 713...Micro address control circuit,
714... Control memory, 715... Micro instruction register, 716... Element number register, 717... Zero detection circuit. Nol? 59.12.2G Showa year, month, day 1, case description 1982 Patent Application No. 19643
9 So 2, Title of the invention Maximum value of array elements and relationship of the maximum element to the incident Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent: 108 Shiba, Minato-ku, Tokyo? iT [No. 137 8-Sumitomo San [N Building Telephone East IIR (03) 456-311
1 (Major representative) 5 The entry "13" in column 6 of the detailed explanation of the invention in the specification subject to amendment, page 6, line 8 of the specification of the contents of the amendment, is corrected to "12".

Claims (1)

[Claims] A method of calculating the maximum value of an array element and the element number of the maximum element in which each element is assigned an element number, the method comprising: an operation code field specifying the type of operation; and the beginning of the array. Eleven column elements are retrieved from the main memory according to an instruction word that has an address designation field that designates the address of an element, an inter-element distance designation field that designates the distance between elements, and a number-of-elements designation field that designates the number n of elements to be operated on. A first step of reading, and storing the maximum value of the elements up to the first (i=1, 2*..., n) of the array elements read in this first step in the first holding means. store the element number of the element having the maximum value in the second holding means, and compare the contents of the first holding means with the (i+1)th element.
If the (i+1)-th element has a larger value, that value is stored in the first storage means and the (i+1)-th element has a larger value.
) A second step of storing the element number of the element number in the second holding means, and storing the contents of the first holding means in the first register when the comparison up to the nth element is completed. and further comprising the step of storing the contents of the second holding means in a second register.