JPS60122443A - Information processing unit - Google Patents

Abstract

PURPOSE:To decrease effectively an overall processing time by providing a backup resistor storing the past value of high-order l-bit of a memory address register and omitting a part of process of address converting processing only when the value of l-bit value is changed. CONSTITUTION:The past bit pattern of the high-order l-bit of a memory address register 1 is stored in the backup register 18. Then a comparator 19 compares the content of the register 18 with the content of the register 1. If the both are not coincident as the result, every time a real address register 3 is set, the register 18 is set. When the both are coincident, only when the high-order l-bit of the register 1 is unchanged, a part of the process of the address converting processing is omitted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an information processing device having a cache device, and particularly to address translation processing for accessing the cache device.

[Prior art]

A cache device is a high-speed buffer storage device that temporarily stores a portion of the contents of the main memory device.By providing a cache device, the access time to the main memory device can be substantially reduced. It is well known that the term can be shortened.

FIG. 1 is a block diagram showing an example of a conventional device of this type, in which (1) is a memory address register;
(2) is an address translation device, (3) is a real address register, (4) is a cache device, (5) is an index array in the cache device (4), and (6) is a data array in the cache device (4). , (7), and (8) are comparators (hereinafter abbreviated as COMP 1 and COMP 2), (9) is a control circuit, and ill') is a selector.

The logical address set in the memory address register (11) is converted into a real address and the main memory (not shown) is accessed using this real address. Then, reading from the data array (6) can be done faster than reading from the main memory, so first check whether the data exists in the data array (6). .

The lower m bits (m is a predetermined positive integer) of the address set in memory address register (11) remain unchanged in both the logical address and the real address.The logical address of the upper t bits excluding these m bits is The address translation device (2) converts the real address into the upper bits of the real address by processing such as table search, and sets it in the real address register (3).

As explained earlier, the lower bits of the real address are the lower m bits of the logical address.

Data stored in the data array (6) as a copy of a portion of the main memory is arranged using the lower m bits of the real address representing the storage location within the main memory. A plurality of pieces of data having the same lower m-bit address are stored in the data array (6), and these pieces of data are simultaneously read out using the m-bit address. In the example shown in FIG. 1, the number of data read simultaneously from the data array (6) by the same address is two, which are shown separated by dotted lines within the blocks of the data array (6).

The bit pattern of the upper bit of the real address of the data stored in the data array (6) is stored in the same address position as the address position in the data array (6) of the data in the index array (5). . When two pieces of data are stored in the data array for the same m-bit address, two indexes for the same address are stored in the index array (5) and read out at the same time.

Therefore, the index array (5) and the data array (6) are simultaneously read using the lower m bits of the contents of the memory address register (1), and all indexes read from the index array (5) (in the case of FIG. 1, 2 index of 3) to the real address register (3
), COMP 1 (7
), COMP 2 (8)) means that the requestable data is stored in the cache device (4) and is read out from the data array (6) in accordance with the matching index. This is the data that contains the data. If there is nothing that matches the contents of the index real address register (3) that are simultaneously read from the index array (5), the desired data does not exist in the cache device (4) and access to the main memory is disabled. means needing.

In the example shown in FIG. 1, if COMP 2 (8) outputs a signal indicating a match, the output from the right half of the data array (6) corresponding to the right half of the index array (5) is the data to be inserted. This means that the control circuit (9
), the data output from the right half of the data array (6) is outputted as the data via the selection circuit αO.

The operation described above is shown in a flowchart as shown in FIG. The steps (11) to αη in FIG. 2 are as described above.

The conventional device operates as shown in FIG.
]) each time a new logical address is set in the memory address register (1) by step α].

I was running α4,0υ. However, even if the numerical value set in the memory address register (1) changes, the change often occurs within the lower m bit range and the upper t pits do not change. If the upper t bits do not change, step o
'a, (11'(i-) There is no need to execute it, and the value already set in the real address register (3) can be used as it is, but in conventional devices, step Q2, (11), which has the disadvantage of reducing the overall processing speed of the information processing device.Especially when multiple cache devices share one address translation device, competition for the address translation device occurred, and the above-mentioned drawbacks became even more prominent.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and in this invention, a register (hereinafter referred to as a temporary backup register) that stores the past bit pattern of the upper t bits of the memory address register (1) is used. As long as the contents of this backup register and the upper t pit of the memory address register ill match, step Q9 in FIG.
g3 is omitted and the overall processing speed is improved.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figure indicate the same or equivalent parts, and <1119 is a memory address register (a backup register in which the past bit pattern of the upper l bits of 11 is stored;
19 is a comparator (hereinafter referred to as CO) that compares the contents of the backup register 08 and the contents of the memory address register (1).
(abbreviated as MP3).

FIG. 4 is a flowchart showing the operation of the device shown in FIG.
The same numerals as in FIG. 2 indicate the same steps, and (c) is CO.
MP3 (Comparison step in II, *a is step of setting backup register α1, (c).

Steps (c) are the same steps as α4 and α09 in FIG. 2, respectively.

The operation of the apparatus shown in FIG. 3 will be explained below with reference to FIG.

When a new logical address is set in the memory address register (1) in step (11), step Q]) is entered and the contents of the upper t bits of the memory address register (1) are compared with the contents of the backup register 0e. If they do not match (the comparison result is N).

) As in Figure 2, step (2), (to), α
4° αυ, αQ, αη are executed, and every time the real address register (3) is set in step a3, step (a) is executed to set the backup register 0→.

Also, if the comparison result in step 01) is YES, steps (2) and (to) are omitted and steps α◆ and (t) are performed.
Execute steps (c) and (c) that are the same as .

The time required for processing steps as, ni, α→, Q] is 1. 1. 1. If it is 1, then (1
1□12 13 14 21 ” tia )>t14, and the time required from the end of step αη to the start of step αFJ (or (c)) is T□ ”” t12 ” tia in the conventional device, In the device of this invention, T3=t2□+t14 or T'3=t21+t□2+
t16, but t2□ is t□2. This invention is effective for the purpose of shortening processing time because it is small compared to t□3, etc., and there are relatively few chances of reaching 73 as a result of No in step Q1). In other words, data is often retrieved while sequentially changing the value of the lower m bits without changing the upper t bits of the memory address register fil.
In this case, unless the upper t bits of memory address register (1) change, the determination result in step (c) is YE.
It becomes S.

In addition, in an information processing device having a cache device dedicated to instructions and a cache device dedicated to instruction operand data, if the present invention is applied to the cache device dedicated to instructions, (a) If the address translation device is shared, the address translation device Conflicts occur, and address translation is prioritized for the cache device dedicated to operand data, and the cache device dedicated to instructions is often forced to wait even if the use of the address translation device is requested.However, with this invention, the use of the address translation device is The frequency of requests can be significantly reduced.

(b) In the instruction-only cache device, since the instructions are read out sequentially, there is less opportunity for the upper t bits of the memory address register (1) to change, so there are advantages such as a significant reduction in processing time. .

The embodiment shown in FIG. 3 is for one cache device, and the cache device stores two blocks of data (
Although the case where two pieces of data that can be read at the same time at the same address of the lower m bits is stored has been described, the present invention can also be applied to an information processing apparatus having a plurality of cache devices. This method can be similarly applied regardless of the number of data blocks to be processed.

〔Effect of the invention〕

As described above, according to the present invention, a backup register is provided to store the past value of the upper t bits of the memory address register, and the address conversion process is omitted unless the value of the t bit changes. Overall processing time can be effectively shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional device, FIG. 2 is a flowchart showing the operation of the device shown in FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a flowchart showing the operation of the device. (1)...Memory address register, (2)...Address translation device, (3)...Real address register, (4)...Cache device, (5)...Index array, (6 )...Data array, 0 barrel...Backup register, 0 field...Comparator (COMP 3
). Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

[Scope of Claim] An information processing device having a buffer storage device that can be accessed at high speed and temporarily stores a copy of a part of the contents of a main storage device, comprising: a memory address register in which a logical address is set; An address conversion device that inputs a predetermined number of high-order bits to be converted into high-order bits of the real address among the contents of the memory address register and converts them into the high-order bits of the real address, and an output converted by this address conversion device is set. a real address register in which the input of the address translation device is set at the time when the output of the address translation device is set in the real address register; and a backup register in which the input of the address translation device is set to the real address register; means for comparing a value read from the index array of the buffer storage device using the lower bits excluding the upper bits as an address and the contents of the real address register; , a comparator that compares the predetermined number of upper bits of this memory address register with the contents of the backup register, and when this comparator outputs a signal indicating a comparison match, performs address conversion and real address register setting. An information processing device comprising means for comparing the contents of a real address register that has already been set with a value read from the index array.