JPS5812054A - Address controller - Google Patents

Abstract

PURPOSE:To improve the processing speed of a microprocessor, by executing increase/decrease of an address register for an operation instruction at the same time. CONSTITUTION:Operating data D0-D7 and C0-C7 changing addresses are set to shift registers (SRs)5 and 6. The SRs 5 and 6 shift by 1-bit circulatingly with an execution timing signal T of the operation instruction and output the data D0-D7 and C0-C7 to a decoder 4. The decoder 4 interpretes the data and gives a control signal of +1, -1 or 0 to incrementor/decrementor/through I/D/S2. The I/D/S2 converts the information of an address register 1 into +1 or -1, or transmits the information to an address buffer 3 without conversion. When this operation is continuously done according to the SRs 5 and 6 and a signal T, the address information of the register 1 is automatically converted according to the operation data D0-D7. When 0 is set to the SRs 5 and 6, the I/D/S2 always select ''through'' and the address information in the register 1 is transferred to the buffer 3 as it is.

Description

[Detailed description of the invention] This relates to the address control device K manufactured by Ij11.

As digital computer technology advances, increasing the speed of digital signal processing is often an issue.

Complex number calculations are essential in this digital signal processing. - For example, calculations such as the following are often used:

((x, +j x,)+(ye+i yo))x(wo
+iwt)i=,/':Complete
(1) For combinations that cannot perform complex number calculations, such as ``-YU'' and micro-combinations, ``-YU,'' the above equation is calculated by dividing into the real part and the imaginary part as shown below.

Imaginary part xOW1+xIW・+y@WI+yIW・It is assumed that the data used for this calculation is stored in memory. When jO, consider W.,W. Assume that Wl is stored in W,4)- on the memory. Said (2)
As you calculate the formula sequentially, the increase/decrease in the address value will be %W, assuming that the address is set at the beginning, +
1, -1, +1, O.

-1t+1*1.

When performing arithmetic operations while performing the above-mentioned address operations, conventional microprocessors must directly perform instructions to increase or decrease address registers, thus requiring the procedure of the flow graph shown in FIG. As is clear from FIG. 1, the number of instruction steps required for incrementing and decrementing the address value is K, which is one of the causes of a decrease in processing speed. The above is a major hindrance to digital signal processing, which requires high-speed processing.

The present invention aims to eliminate the cause of OJi, and! It is a microprocessor equipped with a function to improve processing speed.

In the present invention, the conventional microprocessor as shown in FIG.
For PliK, it is possible to simultaneously execute an operation instruction to increase or decrease an address register, so that the above-mentioned calculation can be realized by the operation procedure shown in FIG. Registers that control the above operation functions.

This was realized using a decoder etc. Set the conversion data for the address increase/decrease instructions required in the control register above.
Since it is possible to refer to this converted data in advance, the number of processes can be reduced.

The present invention will be explained using the drawings.

FIG. 3 shows an embodiment of the present invention. Conventionally, an address register 1, an incrementer/decrementer 2. and an address buffer 3. In the present invention, the shift register 5. and 6.
In addition, a decoder 4 is added. Further, the conventional incrementer/decrementer 2 is provided with a through function for transferring information in the address register 1 to the address buffer 3 until that time.

Next, the operation will be explained.

Shift register 5. and operation data De, Dx ---Dy (Do to D, are 101 or '1') for changing the address to 6, and C*, Ct ---Cy (C.

~C1 is set to @0@ or "11). The shift registers 5 and 6 circularly shift 1 bit according to the execution timing signal TK of the operation instruction, and at the same time, the 1 decoder 4
11 shown in Figure 4. Outputs I. (2) and I are assumed to be 4, taking the values of D, ~Dq, and q, ~C1. I
,,I, is decoded by the decoder 4, and the iris 4 figure 00. ,0. ，
0. +1. to incrementer/decrementer/through 2 using the control line. -1 or O control signal is sent. KoO
According to the control signal, the incrementer/decrementer/through two companies convert the address information in the address register 1 by +1 or -IK, or send this address information to the address buffer 3 without converting it. Shift register 5
．． and 6 are performed continuously using the operation instruction execution timing signal TK915, the address information in the address register 10 is automatically changed to the preset operation data D.
,,D,-1---D,. For example, the above-mentioned conversion operations +i, -i, -t
-t, o.

-1, +1. -1 by the above conversion operation, ,D,,---・
It is used in correspondence with D. However, D, is set to 0, and the order in which W,,W, are selected is,W,,
W,,W,,W,=wt,W,,W,,W.

Therefore, when calculating the above equation (2), the address register manipulation command only needs to set the address of Wo, which is the initial address data, and no other manipulation commands are required. First, if you do not need an address increase/decrease instruction, by setting the shift registers 5° and 6K"O', the incrementer/decrementer/through 2 will always select through. The address information will be transferred to the IT address buffer 3.The above function is useful when a large number of geographical calculations that use the same data over and over again are required, such as complex calculations such as digital signal processing. The number of operation instruction steps can be reduced, speeding up processing and simplifying programs.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart showing the operating procedure according to a conventional method, and FIG. 2 is a flowchart showing the operating procedure according to the present invention. FIG. 3 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a block diagram for explaining the operation of the present invention. l...address register, 2...incrementer/decrementer/through, 3...address buffer, 4---decoder, 5, 6...
...Shift register, T-...--Arithmetic instruction execution timing signal, ■. I, ----operation signal, 0. ．． 0. ．． 0.・・・－・・・
Control signal. Figure 1

Claims (1)

[Claims] An address control device comprising an address register, an address arithmetic circuit that converts the address data stored in the address register, and an address buffer that outputs the address data computed by the address arithmetic circuit to an address bus. A control circuit that includes a control circuit that generates a control signal that specifies an operation, and a shift register that stores control data of the control circuit, and that specifies the arithmetic function of the address arithmetic circuit by the shift register and the control circuit. An address control device characterized by: