JPS6145264B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address control device. With the advancement of digital computer technology,
Speeding up digital signal processing is often a topic of discussion. In this digital signal processing, calculation of prime numbers is essential. For example, the following calculations are often used:

{(x ₀ + ix ₁ ) + y ₀ + iy ₀ )}×(w ₀ +iw ₁ ) i=√−1 (1) On computers and microcomputers that cannot calculate complex numbers, the above equation can be calculated using real numbers as shown below. Calculations are performed separately for the part and imaginary part.

Real part x ₀ w ₀ −x ₁ w ₁ +y ₀ w ₀ −y ₁ w _1Imaginary part x ₀ w ₁ +x ₁ w ₀ +y ₀ w ₁ +y ₁ w ₀ (2) The data used for this calculation is stored in memory. Assume that it is stored. At this time, consider w ₀ and w ₁ . Suppose that w ₁ is stored next to w ₀ in memory. By sequentially performing the calculations of equation (2) above, we get
The increase/decrease in the address value is +1, -1, +1, 0, -1, + if the w ₀ address is set first.
It changes from 1 to -1.

When performing arithmetic operations while performing the above-mentioned address operations, conventional microprocessors require direct instruction to increase or decrease the address register, thus requiring the procedure of the flow graph shown in FIG. As is clear from FIG. 1, incrementing and decrementing address values requires a considerable number of instruction steps, which is one of the causes of a reduction in processing speed. The above is a major obstacle for digital signal processing, which requires high-speed processing.

The present invention aims to eliminate the above causes,
It is a microprocessor equipped with a function to improve processing speed.

In contrast to the conventional microprocessor procedure shown in FIG. 1, the present invention makes it possible to simultaneously execute an arithmetic instruction to increase or decrease the address register, thereby making it possible to realize the above calculation with the operating procedure shown in FIG. 2. This is what I did. Registers that control the above operation functions,
This was realized using a decoder etc. The conversion data for the address increase/decrease instructions required for the control register is set, and the output value of the address register can be converted while referring to this conversion data, which reduces the number of processes. be able to.

The present invention will be explained using the drawings.

FIG. 3 shows an embodiment of the present invention. Conventionally, it was composed of an address register 1, an incrementer/decrementer 2, and an address buffer 3. In the present invention, shift registers 5 and 6 and a decoder 4 are added to the above conventional configuration.
is added. Further, the conventional incrementer/decrementer 2 is provided with a through function for directly transferring information in the address register 1 to the address buffer 3.

Next, the operation will be explained.

Operation data D ₀ , D ₁ , ...D ₇ (D ₀ to _{D 7} are “0”) for changing addresses in shift registers 5 and 6
or “1”), and C ₀ , C ₁ , . . . C ₇ (C ₀ to _{C 7} are “0” or “1”). The shift registers 5 and 6 cyclically shift one bit by the execution timing signal T of the arithmetic instruction, and at the same time output I ₁ and I ₂ shown in FIG. 4 to the decoder 4. It is assumed that I ₁ and I ₂ take values of D ₀ to D ₇ and C ₁ to C ₇ . I ₁ and I ₂ are decoded by the decoder 4, and O _{1 and} I 2 in FIG.
Send a ₊₁ , -1 or 0 control signal to the incrementer/decrementer/through 2 using the O 2 and O ₃ control lines. According to this control signal, the incrementer/decrementer/through 2 converts the address information in the address register 1 to +1 or -1, or sends this address information to the address buffer 3 without converting it. The above operation is performed by shift register 5,
and 6 are performed continuously according to the operation instruction execution timing signal T, the address information in the address register 1 is automatically changed according to the preset operation data D ₀ , D ₁ , . . . D _{7 .} It will be converted. For example, the conversion operation +
1, -1, +1, 0, -1, +1, -1 are used in correspondence with the above conversion operations D ₁ , D ₂ , . . . D ₇ . However, D ₀ is set to 0, and W ₀ , W ₁ at this time
The order in which is chosen is W ₀ , W ₁ , W ₀ , W ₁ , W ₁ ,
W ₀ , W ₁ , W ₀ , and when calculating equation (2) above, the address register manipulation instruction only needs to set the address of W ₀ , which is the initial address data, and other manipulation instructions are not necessary. I don't. In addition, if address increase/decrement instructions are not required, by setting "0" in shift registers 5 and 6, incrementer/decrementer/through 2 will always select through, and address register 1 will always select through. Address information remains the same as address buffer 3
will be transferred to. With the above functions, when a large number of processing calculations that use the same data many times are required, such as complex calculations such as digital signal processing, the number of operation command steps can be greatly reduced, speeding up processing and program execution. Simplification can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the operating procedure according to the conventional method, and FIG. 2 is a flowchart showing the operating procedure according to the present invention. FIG. 3 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a block diagram for explaining the operation of the present invention. 1... Address register, 2... Incrementer/decrementer/through, 3... Address buffer, 4... Decoder, 5, 6... Shift register, T... Arithmetic instruction execution timing signal, I ₁ , I ₂
...operation signal, O ₁ , O ₂ , O ₃ ... control signal.

Claims (1)

[Claims] 1. In an address control device comprising an address register, an address calculation circuit that converts address data stored in the address register, and an address buffer that outputs the address data calculated by the address calculation circuit to an address bus, and a shift register that stores control data of the control circuit, and the arithmetic function of the address arithmetic circuit is specified by the shift register and the control circuit. An address control device characterized by: