JPS61175821A - Timer device for microcomputer - Google Patents

Abstract

PURPOSE:To prevent a hardware from being complicated, by placing an indirect address register and an address of a timer on the same space, so that the timer is operated as a data pointer, which is brought to an increment automatically at the time of a desired mode. CONSTITUTION:At the time of a mode in which a control signal from a control register 7 is '1', an address of a timer 4 is generated from a data pointer generating circuit 5 by a clock M2, and supplied to the timer 4 through buses 8, 9. Next, the contents of the timer 4 shown by its address are read out by a clock M3 and latched by a RAM address latching circuit 2. Also, by a clock M0, the contents of the circuit 2 are decoded by an address decoder 3 and supplied to a RAM1, and object data is fetched to the bus 8 side from the RAM1. This data is subjected to a necessary signal processing and its operation result is stored. In such a way, in this mode, the timer 4 is operated as an automatic increment data pointer.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to microcomputers, and in particular to a microcomputer that has a register (hereinafter referred to as a data pointer) that allows data access through indirect specification and a built-in timer function. Relating to a timer device.

(Prior Art) Generally, as a method for accessing target data in computer operations, there is a method of indirect addressing in which the contents of a register that has the address of the target data is read and then the target data is accessed. When reading or writing this target data from consecutive addresses, if a data pointer having the address of the target data is automatically incremented during execution of an operation, program steps can be shortened, resulting in a concise program.

[Problem that the invention seeks to solve]

However, providing the data pointer with the above-mentioned increment function has drawbacks such as the need for the data pointer to be in the form of a binary counter, which complicates the hardware. Furthermore, since such operations are not always performed on consecutive addresses, the efficiency of hardware usage is poor.

This invention was made in view of these points, and it is possible to add an auto-increment function of a data pointer without adding any hardware, and it is possible to flexibly change the internal system of a microcomputer according to the needs of the user. The present invention provides a timer device for a microcomputer that can perform the following steps.

[Means for solving problems]

The timer device for a microcomputer according to the present invention has the following features:
In a microcomputer that has a built-in indirect address register and a timer, the addresses of the indirect address register and timer (4) are placed in the same space, and when the instruction is in the indirect specified address mode and the indirect specified address is automatically set to 1.
In the increment mode, the timer (4) is configured to function as an indirect address register that automatically increments the timer (4).

[Effect]

The indirect address register included in RAM (11), that is, the data pointer and the timer (4) have the same address (7)
Placed in RAM address space. Then, the instruction becomes indirect specification mode, that is, the signal DPIR becomes "11",
In addition, the indirect specified address is automatically incremented by 1 (11!), that is, when the signal AUTD is set to 1'', the timer (4) is made to function as an indirect address register (data pointer) that automatically increments. The built-in timer can be changed to an automatic increment data pointer.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail based on FIGS. 1 to 4.

Figure 1 shows the overall configuration of this embodiment. In the figure, (1) is an RA that has a data pointer in a part
M, (21 is a RAM address latch circuit, (3) is an address decoder, (4) is a timer, (5) is a data pointer address generation circuit, and (6) is a ROM (not shown) instruction The signal DPIR output from the instruction decoder (6) becomes valid when an instruction with indirect addressing mode is executed.In other words, when the instruction is in indirect addressing mode, for example @1 ``'', otherwise it becomes ``0''. (7) is a control register, and the signal AIJTD output from this control register (7) programmably sets and resets the bit to control normal mode and automatic increment data. This is a control signal for selecting pointer mode.

For example, when the control signal AUTD is “0”, the normal mode is “
When it is "l", it becomes automatic increment data pointer mode.

Next, the operation shown in FIG. 1 will be explained with reference to FIG. 2.

In the normal mode where the control signal from the control register (7) is "0" while the signal DPIR from the instruction decoder (6) is "1" and the instruction is in the indirect address mode, the period of clock M2 A data pointer (DP) address indicating the normal mode is generated from the data pointer address generation circuit (5) at the bus (8), (9
), the contents of the data pointer indicated by the address are read out during the period of clock M3 and latched into the RAM address latch circuit (2).

Then, the RAM address latch circuit (2
) is decoded by the address decoder (3) and sent to R.
A M (11), and the target data is taken out from this RAM (1) to the bus (8) side.The taken out target data then undergoes the necessary signal processing and is clocked by the clock Ml depending on the instruction. For example, the result of the calculation is stored.In this normal mode, the timer (4) works as an ordinary timer.

On the other hand, in the automatic increment data pointer mode in which the control signal from the control register (7) is "11", a data pointer address representing the automatic increment data pointer mode is generated by the data pointer address generation circuit (5) during the period of clock M2. , that is, the address of timer (41) is generated and supplied to timer (41) via bus +8, (9).

Then, using clock M3, the timer (
4) is read out and the RAM address latch circuit (
2) is latched.

Furthermore, the RAM address latch circuit (2) is clocked by the clock MO.
The contents of are decoded by address decoder (3) and sent to RA.
M (1), and at this time the timer content is 1
The target data is taken out from this RAM (1) to the bus (8) side. The retrieved target data is subjected to necessary signal processing, and depending on the instruction, for example, the calculation result is stored at clock M1. In this automatic increment data pointer mode, timer (4) works as an automatic increment data pointer because the contents of timer (4) are automatically incremented by one in MO after being retrieved in M3.

FIG. 3 shows an example of a specific circuit of the data pointer address generation circuit (5).
~P7 is provided, which corresponds to bus (8). Field effect transistors (hereinafter referred to as FETs) are connected in series between the line PO and ground (GND) (10), (11)
is connected, and similarly FET (1
2), (13), FET between line and ground
(14), (15), F between line P7 and ground
ET (16) and (17) are connected. FET
(10), (12), (14), (
Each gate terminal of the inverter (16) is commonly connected to the inverter (1
8), and the input side of this inverter (18) is connected to the output end of the NAND circuit (19). One input end of the NAND circuit (19) is connected to a terminal (20), to which the signal DPIR from the instruction decoder (6) (Fig. 1) is supplied, and to the local input end. Clock M2 is supplied.

In addition, the control signal AI is sent from the control register (7) (Fig. 1).
The terminal (21) to which ITD is supplied is the inverter (22)
is connected to the gate terminal of FET (11) through FET (13), (15), (1
7) is connected to the gate terminal.

Currently, the levels of lines P1 to P4 are precharged to "1", and the levels of lines PO and P5 to P7 are also normally precharged to "1". In the normal mode when the control signal AUTO from the terminal (21) is "01", the output of the inverter (22) becomes 1'' and the FET (11) turns on, while the FET=(13),
(15) and (17) are turned off. In the indirect address mode in which the signal DPIR supplied to the terminal (20) is 11'', the output of the NAND circuit (19) becomes "O" when the clock M2 is supplied, and the output of the inverter (18) becomes "O". This "l" signal whose output becomes "1" is FB'r (10).

It is supplied to the gate terminals of (12), (14), and (16). As a result, the level of the line PO connected to the FET (10) connected to the FET (11) that is on becomes 01, and the levels of the remaining lines PI to P7 are 1''. Considering this in terms of positive logic, The level of line PO becomes “1” and the level of lines P1 to P7 becomes @θ
''.If we consider this in hexadecimal notation (P7
Pa P5 P4 ) −(0000).

(Pa P2 PI PO) → (0001) [O1
].

In other words, in normal mode, the data pointer address is set to [0
1], the data pointer address generation circuit (5)
Thus, data pointer address [01] is generated.

Next, when the control signal ^υTD from the terminal (21) is "1" in automatic increment data pointer mode, FET:T (11) is turned off, and FET (13)
, (15) and (17) are turned on. Then, when the clock M2 is supplied in the indirect designation address mode in which the signal 0PIR supplied to the terminal (20) is "1", the FETs (10), (12), (14
), a signal of "1" is supplied to the gate terminals of (16). As a result, the ON FET (13),
(15), (17) are connected to FET (
The levels of lines P5 to P7 connected to 12), (14), and (16) are "0", and the levels of the remaining lines PO to P4 are "1".

If we consider this in positive logic as above, the level of lines P5-P7 will be ``1'', and the level of lines PO-P4 will be @0'', and if we consider this in hexadecimal notation (P
7 Pa P5 P4 ) → (1110), (P3P2
PI PO)→(0000) becomes (EO).

That is, in the automatic increment data pointer mode, if the data pointer address is CEO), the data pointer address [EO] is generated by the data pointer address generation circuit (5).

FIG. 4 shows an example of a specific circuit of a timer (4) and its peripheral control circuit.
1 and (32) are terminals to which the signals DPIR and AUTD are respectively supplied, which are connected to each input terminal of an AND circuit (33), and the remaining input terminals of this AND circuit (33) are supplied with a clock MO. is supplied. In addition, the terminal (32) is connected to one input terminal of the AND circuit (35) via the inverter (34), and the clock M2 and the other input terminals of the AND circuit (35) are connected to each other when operating as a normal timer. If necessary, a lock control signal C1 is supplied. Each output terminal of the AND circuits (33) and (35) is connected to a NOR circuit (36).
), and the output terminal of the NOR circuit (36) is connected to the clock terminal of the timer (4) via an inverter (37).

In addition, the terminals (31) and (32) are connected to the AND circuit (3
8), and a clock M3 and an address decoder (3) are connected to each of the remaining input terminals of the AND circuit (38).
A signal TAD (signal obtained by decoding data pointer address [EO]) from (FIG. 1) is supplied. Also,
An AND circuit (39) is provided, and each input terminal has a readout signal C3 and a clock M when operating as a normal timer.
O and signal TAD are supplied. And the AND circuit (
3B), each output terminal of (39) is a NOR circuit (40)
The output terminal of the NOR circuit (40) is connected to the read terminal of the timer (4) via an inverter (41).

Further, a NAND circuit (42) is provided, and each input terminal is supplied with a signal TAD and a write signal C2 necessary when operating as a normal timer. The output terminal of the NAND circuit (42) is connected to the write terminal of the timer (41) via an inverter (43).

Now, when the signal ports PIR and ALITD supplied to the terminals (31) and (32) are both "1", that is, when the indirect address mode and the automatic increment data pointer mode are set, the gate of the AND circuit (38) is When the decoded signal TAD of the data pointer address (80) is supplied from the address decoder (3) (FIG. 1) at the time when the clock M3 is applied,
The output “l” from the AND circuit (38) is
) and is inverted by the inverter (41) to become a 1° signal, which is supplied to the read terminal of the timer (4).

Then, the contents of the position corresponding to the data pointer address CBO) are read out.

Furthermore, when both the signals DPIR and AUT ports are "1", the gate of the AND circuit (33) opens, and when the clock MO is applied, the output "1" of the AND circuit (33) connects the NOR circuit (36). It is inverted by the inverter (37) and becomes “1”.
'' signal is supplied to the clock terminal of the timer (41), thereby incrementing the timer (4) once.

On the other hand, when the signal AUTO is 0'', that is, in the normal mode, the AND circuit (35) opens the gate by the @1'' signal passed through the inverter (34), and the clock M2. When the clock control signal C1 is applied, the AND circuit (35
) becomes 'l'', which is supplied to the clock terminal of the timer (4) via the NOR circuit (36) and the inverter (37), and the timer (41) is incremented.

Further, when the AND circuit (39) is supplied with the read signal C3° clock MO and the signal TAD, the AND circuit (39)
) becomes 61'', which is supplied to the read terminal of the timer (4) via the NOR circuit (40) and the inverter (41), and the contents of the timer (4) are read out.

In addition, the write signal C2° signal T is input to the NAND circuit (42).
When AD is supplied, the output of the NAND circuit (39) becomes “0”.
''' is inverted by the inverter (43) and the timer (
The brown write terminal can be supplied to load the first data pointer value into position.

〔Effect of the invention〕

As described above, according to the present invention, the indirect address register (
The addresses of the data pointer) and timer (timer register) are placed in the same space, and when an instruction is executed, the data pointer address generation circuit is controlled to select either address, and when the timer is selected, one indirect address is Increment the timer once when executing an instruction in the specified mode,
The indirect address becomes the contents of the timer register, and the contents of the address indicated by it become the object of the operation. Therefore, by providing a control register to control the data pointer address generation circuit and programmably selecting between a normal data pointer and an automatic increment data pointer (in this case, the timer register is the data pointer), the optimal format can be selected depending on the calculation content. Become. The original hardware of the data pointer need not be in the form of a binary counter as in the past, but may be a register. In other words, the auto-increment function of the data pointer can be added without adding any hardware. Also,
It can be flexibly changed according to the needs of the internal system of the microcomputer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a line diagram for explaining the operation of FIG. 1, and FIGS. 3 and 4 each show an example of the main part of the invention. FIG. 3 is a circuit configuration diagram. (1) is RAM, (2) is RAM address latch circuit,
(3) is an address decoder, (4) is a timer, (5) is a data pointer address generation circuit, (6) is an instruction decoder, (and is a control register. Ribbon data Shitu - Fruit - L. Figure 3 P71 - Fu - Upper one

Claims (1)

[Claims] In a microcomputer that has a built-in indirect address register and a timer, a mode in which the addresses of the indirect address register and timer are placed in the same space, the instruction is in the indirect specification address mode, and the indirect specification address is automatically increased by one. A timer device for a microcomputer, characterized in that it functions as an indirect address register that automatically increments the timer.