JPS63261439A - Data storage device - Google Patents

Abstract

PURPOSE:To reduce overhead at the time of reading out data set such as array data by reading out a required element from the data set without executing the specific address calculation of addresses storing elements in the data set. CONSTITUTION:A data packet for executing memory access holds the set name of a required data set and the set name is loaded to a counter in pointer address memory (pam). Then, the memory (pam) is read out by using the output of the counter as an address and a pointer address is latched to a register (r) in a pointer memory (pm). The contents of the memory (pm) are read out by using the contents of the register (r) as an address. The read pointer is latched to an address register (ar) in a data memory (dm) and the contents of the memory (dm) are read out by using the latched pointer as an address. Thus, overhead can be reduced at the time of reading out a data set such as array data.

Description

[Detailed Description of the Invention] (a) Industrial Application Field This invention relates to a data storage device used in computer systems, etc., and in particular to a data storage device for efficiently storing and referencing data sets such as array data. It is related to storage devices.

(b) Conventional technology In general, a computer system is composed of a data processing device, a data storage device, etc., and the data processing device reads data from the data storage device, performs some processing, and writes the data to the data storage device. Processing proceeds by repeating this cycle.The problem of overhead (processing waiting time) in a data processing device for referring to a data storage device is common to various computer systems.

For example, even in data-driven (data flow) computer systems, systems that connect data processing devices and data storage devices have been proposed and realized (this -
Examples are disclosed in pages 205 to 209 of Nikkei Electronics, published April 9, 1982), and in the data storage device of such a system, large amounts of data are continuously read out. In some cases, the processing device had to give an address to the storage device each time a piece of data was read. Furthermore, when referring to a specific element of a data set such as array data, the processing device must calculate and generate an address where the desired element is stored.

(Han) Problems to be Solved by the Invention In conventional data storage devices, when data is read out continuously, the address of each data must be given from the processing device each time. When reading a particular element of a data set, either one or successively, the processing unit had to perform address calculations each time to obtain the address where each element of the array was stored. For the reasons mentioned above, there has been a disadvantage that the processing time required by the processing device to refer to the storage device becomes very long.Therefore, the main purpose of the present invention is to read data sets such as array data. An object of the present invention is to provide a storage device that reduces overhead when storing rice.

(d) Means for solving the problem The first invention is as shown in FIG.
A pointer memory (pm) that stores a pointer that is an address where an element of a data set is stored in m), and a pointer address memory that can refer to a pointer address that is an address in the pointer memory (pm) by the set name of the data set. (pam>) is a data storage device that allows a specific element in a data set to be read without requiring special address calculations.

As shown in FIG. 6, the second invention provides a set name changing means (fn
By providing c), the data storage device is capable of continuously obtaining addresses of a plurality of desired elements with a single reference, and successively reading out specific elements of each of a plurality of data sets. .

(e) Operation According to the data storage device of the present invention, a data packet for memory access holds a set name of a desired data set, and first, this set name is stored in the pointer address memory (pam). The first time the counter is loaded, the output of this counter is used as an address to read out the memory (pam) in which the pointer address is stored.The read pointer address is stored in the register (r) of the pointer memory (pm). Latched. The pointer memory (pm) is read using the contents of this register as an address.

The pointer that has been read out can be latched into the address register (ar) of the data memory (dm). The data memory (dm) is accessed using this address.

Furthermore, if the ipitam identifier included in the pointer address memory (pam) or provided separately from it instructs continuation, the counter is incremented and the same operation is performed. I! Repeat until the identifier no longer indicates continuation.

(F) Embodiment FIG. 2 shows an outline of a data flow computer system as an example of a system using the data storage device of the present invention. In the system shown in the figure, data packets are input into a ring network (RN), which is a ring-shaped transfer mechanism that transfers data packets (a combination of original data and control information), which is the basic unit of data, within the system. Control output to 0! Network interface (N I ) (N I )
(N I ) via data storage! (DM), a data flow computing device (DFC), and a host interface (HI), and this host interface (HI) is further connected to a host computer (HC).

The data storage device of such a system stores data (for example, image data, array data)
is stored, and in the process in which the data flow computation device (DFC) executes a data-driven program, the data storage device receives execution processing of write commands and read commands according to the control information of the data packet. It is designed to hold.

FIG. 1 shows the configuration of the data storage device of the present invention. In the device shown in the same figure, (1) is an input queue, (2) is a register that holds the first word (header) of an input packet, and (2) is a register that holds the first word (header) of an input packet. 3)
is the register that holds the second word (data) of the input packet, (4) is the environment number, (5) is the processing instruction code, (6)
is the data held by the input packet, and (7) is the judgment/
Control circuit, (8) is a control signal, (9) is a pointer address memory, (10) is a register that holds an environment number and a voice address, (11) is a differential memory, (12) is a pointer memory, (13) is a Difference register, (14> is pointer update means (adder), (15) is difference value, (16
) is a pointer register, (17) is a pointer value, (18
) is the data memory, (19) is the output packet data register, (20) is the return code memory, (21)
) is the header register of the output packet, (22) is the return food, (23) is the unchanged information, (24) is the output queue, (25) is the load (dump) address, (26) is the collection name, (27) indicates the means for changing the set name.

Next, the processing operation of the device of the present invention will be explained in detail for each input packet. The structure of the input packet is a two-word data packet as shown in FIGS. 3 and 4 (a), and the processing is performed using a processing instruction code (processing instruction code, module number, etc.), which is one of the control information (processing instruction code, module number, etc.). 5).

■ The 35th A data packet, which indicates the loading of the pointer address memory and return code memory (5> is 5 bits, for example, C51, St,
Ss, S4. Se3-[0,1,O,0.

0] arrives at the input end, the load packet 2 passes through the input queue (1) and is stored in the register (2) (hereinafter referred to as the second register) that holds the header in which the first word of the packet is the first word of the packet. The words are each latched into a register (3) (hereinafter referred to as a second register) that holds the second word (data) of the packet. Among the contents latched in the register (2), the processing instruction hood (5) has been successfully determined by the determination/control circuit (7), and the control signal (8) that controls the loading operation of the following pointer address memory and return hood memory ) is output. Of the contents latched in the register (2), the data (6) held by the input packet is transferred to the pointer address memory (9) and the return food memory (2) using the load (dump) address (25) as the address.
0), there is no output packet.

■ Processing instruction code (5) indicating loading of differential memory (11) For example, when a load packet of [0, 1, 1, O, O] arrives, the first word passes through the input queue (1) and is transferred to the first word register ( 2), 211! The second register (3) is latched into the second register (3). Among the contents latched in this register (2), the processing instruction hood (5) has been successfully determined by the determination/control circuit (7), and the control signal (8) that controls the loading operation of the differential memory (11) is output. Among the contents latched in the register (2), the data (6) held by the input packet is written to the differential memory (11) using the load (dump) address (25) as the address.
There are no output packets.

■ When a load packet whose processing instruction code (5) indicating a load in the pointer memory (12) is, for example, [0, 1, 0, 1, 0] arrives, the first word passes through the input queue (1) and the first word is in the register. (2), the second word is in the second register (3)
are latched respectively. Among the contents latched in the register (2), the processing instruction code (5) is the judgment/control circuit (
7>, and a control signal (8) for controlling the loading operation of the pointer memory (12) is output. Also, among the contents latched in the register (2), the data (6) held by the input packet is transferred to the pointer memory (12) using the load (dump) address (25) as the address.
There are no output packets.

■ When a load packet whose processing instruction code (5) indicating loading of the data memory (18) is, for example, [0, 1, O, 0, 1] arrives, the first word is The second word is in the register (2), and the second word is in the second register (3).
You can trace the respective latches. Among the contents latched in the first register (2), the processing instruction hood (5) is determined by the judgment/control circuit (
7), and a control signal (8) for controlling the following data memory loading operation is output. No. Rujistha (
2) Among the contents latched, the data (6) held by the input packet is written to the data memory (18) using the load (dump) address (25) as the address.
There are no output packets.

■ A data packet as shown in FIG.
I, St, Ss, S-, 5sl-[1, X, 0,
When an operand packet of 1°0 arrives, the first word is latched into the first register (2) and the second word is latched into the second register (3) via the input queue (1). Among the contents latched in the register (2), the processing instruction code (
5) is determined by the determination/control circuit (7), and a control signal (8) for controlling the following pointer settings is output.

Among the contents latched in the register (2), the set name has not been loaded into the set name updating means (27).1. The pointer address memory (9) is read using this as an address. Among this output of the pointer address memory (9) and the contents of the register <2>, the environment number (4) is the environment number.
It is latched into the pointer address holding register (10). This environment number/pointer address holding register (10
) is used as an address to write the data (6) held by the input packet into the pointer memory (12).

On the other hand, the return food memory (20) is read using the contents of the set name updating means (27) as an address, and the return food (22) and unchanged information (23) are latched into the header register (21). An acknowledge packet whose first word is the contents of the header register (21) is shown in Figure 4 (b).
) is output via the output queue (24).

■ For example, the processing instruction hood (5) indicating the difference settings is
1,X,1. When an operand packet of O, O arrives, the first word passes through the input queue (1) and is transferred to the first word register (
2), the 28i-th data is latched in the second register (3). Among the contents latched in the register (2), the processing instruction hood (5) is determined by the determination/control circuit (7), and the control signal (8°
) is output.

Among the contents latched in the register 2), the set name is loaded into the set name update means (27), and the pointer address memory (9) is read out using this as an address. No. Rujistha (
Among the contents of 2), the environment number (4) is latched into the environment number/pointer address holding register (10). The data (6) held in the input packet is written into the differential memory (11) using the contents of the environment number/pointer address holding register (10) as an address.

On the other hand, the return code memory (20) is read using the set name updating means (27) as an address, and the return code (
22), and unchanged information (23) Kahe/Yda register (
21). An acknowledge packet whose first word is the contents of the header register (21) is sent to the output queue (2
4) and then output.

■ When an operand packet arrives whose processing instruction code (5) indicating a write that outputs an acknowledge packet is, for example, [1,X,1°1.0, the input queue (1
), the first word is latched into the first register (2), and the second word is latched into the second register (3). No. Rujistha (2)
Among the contents latched, the processing instruction code (5) is determined by the determination/control circuit (7), and the control tube controls the writing to output the following acknowledge packet! (8
) is output. Among the contents latched in the register (2), the set name is loaded into the set name new means (27), and this is used as an address in the pointer address memory (9).
This output of the pointer address memory (9), and the contents of the first register (2), the environment number (4) is read out.
is latched into the environment number/pointer address holding register (<10). The contents of the environment number/pointer address holding register (10) are used as an address to read out the pointer memory (12) and the differential memory (11).The output of the differential memory (11) is stored in the differential register (13) and ) are respectively latched in the pointer registers (16), and *(1
The contents of the difference register (13) and pointer register (16) are written to the data memory (18) using the address 7) as the data (6) held by the input packet. 14) and write it to the read address of the pointer memory (12), while reading the return code memory (20) using the collective famous new means (27) as the address,
Return food <22) and unchanged information (23) are latched into the header register (21). An acknowledge packet whose first word is the contents of the header register (21) is output via the output queue (24).

■ The processing instruction code (5) indicating a write without outputting an acknowledge packet is, for example, [1,X.

1, 1, 1], the first word is sent to the input queue (1) and the first word is sent to the first word register (2).
Then, the second word is latched into the second register (3), respectively.

Among the contents latched in the register (2), the processing instruction seed (5) is determined by the determination/control circuit (7),
A control signal (8) for controlling writing without outputting the following acknowledge packet is output. No. 1 Rujistha (2)
), the set name is loaded into the set name new means (27), and the pointer address memory (9) is read out using this as an address. Among the contents of 2), the environment number (4) is latched into the environment number/pointer address holding register (10). And environment number・
The contents of the pointer address holding register (10) are used as an address to store the pointer memory (12) and the differential memory (1
1), the output of the differential memory (11) is latched to the differential register (13), the output of the pointer memory (12) is latched to the pointer register (16), and the contents (17) of the pointer register (16>) are latched. The data (6) held by the input packet is used as the address in the data memory (1).
There are no output packets to write to B).

■ For example, if the processing instruction code (5) indicating reading is [1
, X, 0, 1.1], Ig! The i-th word is latched in the register (2), and the second word is latched in the second register (3). Among the contents latched in the register (2), the processing instruction code (5) can be determined by the determination/control circuit (7), and the control statement (8) for controlling the following readout can be output. Among the contents latched in the first register (2),
The set name is loaded into the set name new means (27), and the pointer address memory (9) is read out using this as an address. This output of the pointer address memory (9) and the environment number of the contents of the register (2) are (4) is latched into the environment number/pointer address holding register (10). This environment number/pointer address holding register (1
Pointer memory (12) with the contents of 0) as the address,
and a pointer memory (11) that reads the differential memory (11).
The output of 12) is latched to the pointer register (16), the output of the differential memory (11) is latched to the differential register (13), and the data memory (18) is read using the contents (17) of the pointer register (16) as an address. The contents of the differential register (13) and the pointer register (16) whose contents can be latched into the data register (19) are added by the pointer updating means (14) and written to the read address of the pointer memory (12).

On the other hand, the return code memory (20) is read using the set name updating means (27) as an address, and the return code (
22), and the unchanged information (23) is stored in the header register (2
1) and sets the contents of the header register (21) to 1.
A data packet with the contents of the data register (19) as the second word is output via the output queue (24>).

Now, if the continuation identifier consisting of a 1-bit flag of data included in the pointer address memory (9) or return code memory (20) or provided independently is "1" and indicates continuation, then the set Name update means (2
7) increments the content, stops the output of the input queue (1), and causes the first register (2>) to hold the content.The updated content of the set name updating means (27) is used as the pointer address. Out of this output of the pointer address memory (9) and the contents of the register (2) that reads the memory (9), the environment number (4) is latched into the environment number/pointer address holding register (10). Environment number/pointer address holding register (
10) as the address and pointer memory (12L
and read out the differential memory (11). Pointer memory (
The output of 12) is latched to the pointer register (16), the output of the differential memory (11) is latched to the differential register (13), and the data memory (18) is read using the contents (17) of the pointer register (16) as an address. , its contents are latched into the data register (19). The contents of the difference register (13) and pointer register (16) are added by the pointer updating means (14) and written to the read address of the pointer memory (12).

On the other hand, the return code memory (20) is read using the set name updating means (27) as an address, and the return code (
22), and the information in the register (2>) excluding the return food is latched into the header register (21). A data packet having the second word is output via the output queue (24). This is repeated until the continuation identifier no longer instructs continuation (for example, 0'').

■ In the data packet of FIG. 3, the processing instruction code (5) indicating dumping of the pointer address memory and return code memory is, for example, [s+, sm.

S, , S, , 51] oppression [o, o, o
, o , o When the dump packets arrive,
The first word passes through the input queue (1) and enters the first word (2).
The second word can be latched into the second register (3). Among the contents latted to the No. 1 register (2), the processing instruction hood (5) is determined by the determination/control circuit (7), and the control signal (8) that controls the dump operation of the pointer address memory and return hood memory below ) is output.

Of the contents latched in the first register (2), the load <
dump) address (25) as the address, pointer address memory (9), and return food memory (20
), these contents are stored in the data register (19)
It can be latched to. A data packet whose second word is the contents of this data register (19) is outputted to the host interface via the output queue (24).

■ When a dump packet whose processing instruction code (5) indicating a dump in the pointer memory (12) is, for example, [0, 0, 0, 1, 0] arrives, it passes through the input queue (1) and the first word is the first word. The second word is in the register (2), and the second word is in the second register (3).
are latched respectively. Among the contents latched in the register (2), the processing instruction hood (5) is determined by the determination/control circuit (7), and a control signal (8) for controlling the dump operation of the pointer memory below is output. . Load (dump) the contents latched in the 2nd register
Pointer memory (1) with address (25) as address
2), this content is latched into the data register (19). The contents of this data register (19) are
The data packet is outputted to the host interface via the output queue (24).

@ When a dump packet whose processing instruction hood (5) indicating a dump of the difference memory (11) is, for example, [0, 0, 1, 0, 0] arrives, it passes through the input packet (1) and becomes 1! ! !
The first word is in the second register (2), the second word is in the second register (3)
They can be latched separately. Among the contents latched in the register (2), the processing instruction code (5) is the judgment/control circuit (
7), and a control signal (8) for controlling the following differential memory dump operation is output. No. 1 Rujistha (2)
), the differential memory (11) is read out using the load (dump) address (25) as an address, and this content is latched into the data register (19). A data packet whose second word is the contents of this data register (19) is outputted to the host interface via the output queue (24).

[Phase] Processing instruction code indicating data memory dump
When a dump packet whose value 5) is, for example, [0, O, O, 0, 1] arrives, the first word is stored in the input queue (1), and the first word is stored in the second register (2), and the second word is stored in the second register (2). Of the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7), and the following control is performed to control the dump operation of the data memory. Signal (8>) is output. Load (dump) address (2) of the contents latched in the register (2)
5) is used as the address to read the data memory (18), and its contents are latched into the data register (19).

A data packet whose second word is the contents of this data register (19) is outputted to the host interface via the output queue (24).

(G) Effects of the Invention According to the present invention, the address where the element of the data set is stored can be automatically obtained from the set name included in the data packet. Therefore, a desired element in the data set can be read without requiring special address calculations. Furthermore, multiple elements spanning multiple data sets can be read out consecutively by simply giving a single set name. Furthermore, since the reference operations to the three memories, namely the pointer address memory, pointer memory, and data memory, can be performed in parallel in a vibe-line manner, the time required for reading data - times is very short, such as 0 or more. Due to these characteristics, the present invention provides the following advantages:
The overhead for storage device references can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of the data storage device of the present invention, FIG. 2 is a block diagram of a system using the data storage device of the present invention, and FIGS. 3 and 4 are diagrams of data packets used in the present invention. FIG. 5 is a block diagram showing an overview of the present invention, and FIG. 6 is another block diagram showing an overview of the present invention. (1)...Input queue, (2)...Lujistar, (
3)...Second register, (7)...Judgment/control circuit, (9)...Pointer address memory, (11)...
・Differential memory, (12)... Pointer memory, (13
)...Difference register, (14)...Pointer update means, (16)...Pointer register, (18)...
Data memory, (19)...Data register, (2
0)... Return code memory, (21)... Header register, (24 N... Output queue.

Claims (4)

[Claims] (1) A data memory in which one or more data sets are stored, a pointer memory that stores address information of the data memory in which elements of the data set are stored, and elements of the data set in the pointer memory are stored. The data element comprises a pointer address memory that stores an address in which address information is stored, and the data element in the data memory is read by referring to the pointer address memory by a set name of the data set. Eggplant data storage device. (2) the pointer address memory, pointer memory;
2. The data storage device according to claim 1, wherein reference operations to each of the data memory and the data memory are performed in parallel. (3) A data memory in which a plurality of data sets are stored, a pointer memory that stores address information of the data memory in which elements of the data set are stored, and a pointer memory in which the elements of the data set in the pointer memory are stored. A continuation identifier that stores a pointer address memory that stores an address in which address information is stored, and a continuation identifier that is provided in or in parallel with the pointer address memory and indicates whether or not reference to the data memory is continued. a memory, and a set name update means for updating a set name using the continuation identifier; the data memory is referenced by referring to the pointer address memory by the set name of the data set; By updating the set name according to the continuation identifier using the name update means and repeating the operation of referring to the pointer address memory again using the updated set name, specific data sets of a plurality of data sets in the data memory can be identified. A data storage device characterized in that data elements of element numbers can be successively read. (4) the pointer address memory, pointer memory;
4. The data storage device according to claim 3, wherein reference operations to each of the data memory and the data memory are performed in parallel.