JPS63262738A - Data storage device - Google Patents

Abstract

PURPOSE:To dynamically change a pointer corresponding to an address in which the element of a data aggregate has been stored, by giving an aggregate name to a data aggregate by using a pointer updating data packet. CONSTITUTION:A load packet which has reached an input terminal is held by a register 2 for holding a first word (header) of the packet, and a register 3 for holding a second word (data), respectively. In the contents of the register 2, a processing instruction code 5 is decided by a deciding/control circuit 7, and a control signal 8 for controlling a loading operation of the subsequent point address memory and return code memory is outputted. In the contents of the register 2, data 6 which an input packet has held by using a load address 25 as an address is written in a pointer address memory 9 and a return code memory 20.

Description

[Detailed Description of the Invention] (a) Industrial Application Field This invention relates to a data storage device used in computer systems, etc., and in particular to a data storage device for efficiently storing and referencing data sets such as array data. It is related to storage devices.

(b) Conventional technology In general, a computer system is composed of a data processing device, a data storage device, etc., and the data processing device reads data from the data storage device, performs some processing, and writes the data to the data storage device. The process progresses by repeating this cycle. This problem of overhead (processing waiting time) in a data processing device for referencing a data storage device is common to various computer systems.

For example, in the case of data-driven (data flow) computer systems, an example of a system that connects a data processing device and a data storage device has been proposed, and one example of how it could be realized was published on April 9, 1980. (as disclosed in Nikkei Electronics, pages 205 to 209), and in the data storage device of such a system, when reading a large amount of data continuously, the processing device had to give an address to the storage device from Furthermore, when referring to a specific element of a data set such as array data, the processing device must calculate and generate an address where the desired element is stored.

In contrast, the present applicant proposed a storage device that generates the address where the elements of the data set are stored when the set name of the data set is given, and a storage device that generates the address where the elements of the data set are stored, and multiple elements that span multiple data sets by just giving a single set name. We have succeeded in developing a storage device that can read data continuously, and a storage device that automatically sets the address of the next element to be read within a data set.

(c) Problems to be Solved by the Invention However, in the above-mentioned storage device, the capacity of the pointer memory is limited, so when handling multiple data sets, the number of sets that can be handled is limited. Therefore, if the number of data sets exceeds this number, there is a drawback that memory access cannot be performed.

Therefore, the main object of the present invention is to provide a storage device as described above that can handle an unlimited number of data sets.

(d) Means for Solving the Problems The data storage device of the present invention, as shown in FIGS.
By providing a judgment control circuit (jc) that judges and controls the processing according to the processing instruction code (5), the pointer memory (pm) storing the address where the element of the data set is stored. The contents of the set name (26
) and a processing instruction code (5) indicating a pointer change to an infinite number by dynamically changing the address of an element of another data set (new pointer value) in response to the arrival of a data claw type. This is a storage device that can handle data sets.

(E) Effect According to the present invention (see prisoner 5), a pointer change data packet for changing a pointer includes a processing instruction code (5) indicating a pointer change, a set name (26) of a desired data set, , and a new pointer value (17) which is the address of the data memory where the data elements of the new set corresponding to the set name are stored.When the pointer change data packet arrives, the judgment control circuit (j c )
The processing instruction code (5) is identified, and the following pointer change processing is performed. First, the pointer address memory (pam) is read using the set name (26) as an address.The read pointer address is stored in the register (r).
latched to. Use this as an address to create a new pointer (a
(17) is written to the pointer memory (pm).

A read data packet for reading a data element contains a processing instruction code (
5), and the set name of the desired data set.

When a read data packet arrives, the pointer address memory <pam) is read using the set name as the address.The read pointer address is stored in the register (r).
latched to. The pointer memory (pm) is read out using the contents of this L-sister as an address, and the read pointer is latched into the address register (ar). The data memory (dm) is accessed using this as an address. In the second invention (see Fig. 6), the pointer and the difference are added by the pointer updating means, and this value is written into the pointer memory (p m). If the continuation identifier in the memory specified indicates continuation, the counter is incremented and the same operation is performed, and this is repeated until the continuation identifier no longer instructs continuation. When packets arrive successively, the above operations are performed successively.

(v) Embodiment Fig. 2 shows an outline of a data flow computer system as an example of a system using the data storage device of the present invention. A network interface (N I ) (N I )(
A data storage device f (DM), a data flow calculation device (DFC) and an eight-hohet interface (H
I) is coupled to this host interface (H
I) is further connected to a host computer (HC).

The data storage device of such a system stores data (for example, array data such as image data) that is used when the data flow calculation device (DFC) executes a data-driven (data claw) program including write commands and read commands. )
is memorized and the data flow calculation system! During the process in which the DFC (DFC) executes a data-driven program, the data storage device is responsible for executing write commands and read commands according to control information of data packets.

FIG. 1 shows the configuration of the data storage device of the present invention. In the device shown in the figure, (1) is an input queue; 3)
is the register that holds the second word (data) of the input packet, (4) is the environment number, (5) is the processing instruction code, (6)
is the data held by the input packet, and (7) is the judgment/
Control circuit, (8) is a control signal, (9) is a pointer address memo IJ, (10) is a register that holds an environment number and a voice address, (11) is a differential memory, (12) is a pointer memory, ( 13) is a difference register, (14) is a pointer update means (adder), (15) is a difference value, (1
6) is a pointer register, (17) is a pointer value, <1
8) is data memory, (19) is output packet data register, (20) is return code memory, (21)
is the output packet header register, (22) is the return code, (23) is the unchanged information, (24) is the output queue, <25) is the load/dump) address, (26) is the collection name, and (27) is It shows a means for changing the set name.

Next, the processing operation of the device of the present invention will be explained in detail for each input packet. The structure of the input packet is 2w! as shown in FIGS. 3 and 4 (a). The processing is determined by the processing instruction code (5), which is one of the control information (processing instruction code, module number, etc.).

■ 3rd r: I! J data packet, the processing instruction code <5) indicating loading of the pointer address memory and return code memory is 5 pits, for example [S+,
St, S-, S-, Sa]-[0,1,0,0.

0] arrives at the input end, the first word is transferred to the register (2) (hereinafter referred to as the second register) that holds the first word (header) of the packet after passing through the large queue (1). The second word is latched in a register (3) (hereinafter referred to as a second register) that holds the second word (data) of the packet. Among the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7), and the control signal (8) that controls the loading operation of the following pointer address memory and return code memory is determined by the determination/control circuit (7). )
is output. Among the contents latched in the register (2), the data (6) held by the input packet is transferred to the pointer address memory (9) and the return code memory using the load (dump) address (25) as the address.
20), there is no output packet.

■ Processing instruction code (5) indicating loading of differential memory (11) For example, when a load packet of [0, 1, 1, O, O] arrives, the first word passes through the large queue (1) and is transferred to the first word ( 2), the second word is latched into the second register (3). Among the contents latched in this register (2), the processing instruction code (5) is the judgment/control circuit (7).
), and a control signal <8) for controlling the loading operation of the differential memory 11) is output. Runo Star (2)
), there is no output packet that writes the data (6) held by the input packet to the differential memory (11>) using the load (dump) address (25) as the address.

■ When a load packet whose processing instruction code (5) indicating loading of the pointer memory (12) is, for example, [0, 1, Q, 1, O] arrives, the first word passes through the input queue (1) and is placed in the In (2), the 21st bits are respectively latched in the second register (3). Among the contents latched in the register (2), the processing instruction code (5) has been successfully determined by the determination/control circuit (7), and the pointer memory (12
) is output. Also, among the contents wrapped in the register (2), there is no output packet that writes the data (6) held by the input packet to the pointer memory (12) using the load (dump) address (25) as the address.

■ When a load packet whose processing instruction code 5) indicating loading of the data memory (18) is, for example, [0, 1, 0, 0, 1] arrives, the first word passes through the input queue (1). Lujista (2>, the second word is in the second register 3)
are latched respectively. Among the contents latched in the register (2), the processing instruction code (5) is the judgment/control circuit (
7), and a control signal (8) for controlling the following data memory loading operation is output. No. Rujistha (
2) Among the contents latched, the data (6) held by the input packet is written to the data memory (18) using the load (dump) address (25) as the address.
There are no output packets.

■ In a data packet as shown in FIG. 4(a), the processing instruction code (5) indicating pointer setting is, for example, [5,
,S, ,S, ,S, ,S,Ko[ヱ,X,
When an operand packet of O', 1°0 arrives, the first word is latched in the first register (2) and the second word is latched in the second register (3) after passing through the input queue (1). Among the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7), and a control signal (8) for controlling the following pointer settings is output. Among the contents entered in the second register, the set name is loaded into the set name updating means (27), and the pointer address memory (9) is read out using this as an address. Of this output of the pointer address memory (9) and the contents of the register (2), the environment number (4) is latched into the environment number/pointer address holding register (10). This environment number/pointer address holding register (
The data (6) held by the input packet is written into the pointer memory (12) using the contents of 10) as an address.

On the other hand, the return code memory (20) is read using the contents of the set name update means (27) as an address, and the return code (22) and unchanged information (23) are latched into the header register (21). The acknowledge packet whose first word is the content of 21) is shown in Figure 4 (
b) 4 are outputted via the output queue (24) with the configuration shown.

■ For example, if the processing instruction code (5) indicating the difference setting is [
1,X,1. O, O], when an operand packet arrives, it passes through the input queue (1) and the first word is placed in the first word register (
2), the second word is latched in the second register (3). Among the contents latched in the register (2),
The processing instruction code (5) is determined by the determination/control circuit (7), and a control signal (8) for controlling the following difference settings is output.

Among the contents latched in the register (2), the set name is loaded into the set name updating means (27), and the pointer address memory (9) is read out using this as an address.This output of the pointer address memory (9); Among the contents of register (2), environment number (4) is latched into environment number/pointer address holding register (10). The data (6) held in the input packet is written into the differential memory (11) using the contents of the environment number/pointer address holding register (10) as an address.

On the other hand, the return code memory (20) is read using the set name updating means (27) as an address, and the return code (
22), and the unchanged information (23) is stored in the header register (2
1). An acknowledge packet whose first word is the contents of the header register (21) is sent to the output queue (
24).

■ For example, the processing instruction code (5) indicating a write that outputs an acknowledgement,
] When an operand packet arrives, the first word is transferred to the second register (2) via the input queue (1), and the second word
Each is latched in register (3). No. Rujistha (
Among the contents latched in 2), the processing instruction code (5)
is determined by the determination/control circuit (7), and a control signal (8) for controlling writing that outputs the following acknowledge packet is output. Among the contents latched in the register (2), the set name is loaded into the set name updating means (27), and the pointer address memory (9) is read out using this as an address. Of this output of the pointer address memory (9) and the contents of the register (2), the environment number (4) is the environment number/pointer address holding register (1).
0). The content of this environment number/pointer address holding register (10) is used as an address to read out the pointer memory (12) and differential memory (11).
The output of the differential memory (11) is sent to the differential register (13),
The output of pointer memory (12) is the pointer register (1
6), and write the data (6) held by the input packet into the data memory (18) using the contents (17) of the pointer register (16) as an address. The contents of the difference register (13) and pointer register (16) are updated by pointer updating means (14) consisting of an adder.
and is written to the read address in the pointer memory (12). On the other hand, collective name updating means (27)
Read the return code memory (20) using the address as the return code (22) and the unchanged information (23).
) can be latched into the header register (21). An acknowledge packet containing the contents of the header register (21) as one word is output via the output queue (24).

■ For example, the processing instruction code (5) indicating a write without outputting an acknowledge packet is [1,X.

1, 1, 1], the first word is sent to the input queue (1) and the first word is sent to the first word register (2).
Then, the second word is latched into the second register (3), respectively.

Among the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7),
A control signal (8) for controlling writing without outputting the following acknowledge packet is output. No. Rujistha (2)
Among the contents latched to the set name, the set name is updated by the set name update means (
27), and read out the pointer address memory (9) using this as an address. Among this output of the pointer address memory (9) and the contents of the register (2), the environment number (4) is the environment number/pointer. It is latched into the address holding register (10). Then, the content of the environment number/pointer address holding register (10) is used as an address to be stored in the pointer memory (12) and the differential memory (11).
) is read out. The output of the differential memory (11) is latched in the differential register (13), and the output of the pointer memory 12 is latched in the pointer register (16), and a λ packet is held using the contents (17) of the pointer register (16) as an address. The data (6) that was in the data memory (18)
There are no output packets.

■ For example, if the processing instruction code (5) indicating reading is [1
,
), the second word is latched into the second register (3), respectively. Among the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7), and a control signal (8) for controlling the following reading is output. Among the contents latched in the register (2), the set name is loaded into the set name update means (27), and the pointer address memory (9) is read out using this as an address.
Of this output of the address memory (9) and the contents of the address register (2), the environment number (4) is the environment number.
It is latched into the pointer address holding register (10). This environment number/pointer address holding register (10
) is used as an address to read out the pointer memory (12) and the differential memory (11). Pointer memory (1
2), the output is latched to the pointer register (16), and the output of the differential memory (11) is latched to the differential register (13), respectively, and the data memory (18) is loaded using the contents (17) of the pointer register (16) as an address. The read contents are latched into the data register (19). The contents of the difference register (13) and pointer register (16) are added up by the pointer updating means (14) and written to the read address of the pointer memory (12).

On the other hand, the return code memory (20) is read using the set name updating means (27) as an address, and the return code (
22), and the unchanged information (23) is stored in the header register (2
1) and sets the contents of the header register (21) to 1.
The contents of the data register (19) are 2F! The first data packet is output via an output queue (24).

Now, if the continuation identifier consisting of a 1-bit flag of data included in the pointer address memory (9) or return code memory (20) or provided independently is "1" indicating am, then the set Name update means (2
7) increments the contents, stops the output of the input queue (1), and causes the register (2) to hold its contents. The pointer address memory (9) is read out using the updated set name update means (27) as an address. Among the output of the pointer address memory (9) and the contents of the register (2), the environment number (4) is read out. ) is latched into the environment number/pointer address holding register (10). This environment number/pointer address holding register (
Pointer memory (12) with the contents of 10) as the address
, and read the differential memory (11). The output of the pointer memory (12) is latched to the pointer register (16), the output of the differential memory (11) is latched to the differential register (13), and the contents of the pointer register (16) are latched. The data memory (18) is read using (17) as the address, and its contents are latched into the data register (19). The contents of the difference register (13) and pointer register (16) are added up by the pointer updating means (14) and written to the read address of the pointer memory (12).

On the other hand, the return code memory (20) is read using the set name updating means (27) as an address, and the return code (
22) and the contents of the register (2>), except for the return code, are latched into the header register (21). A data packet is output via the output queue (24), with the contents of the header register (21) as the first word and the contents of the data register (19) as the second word. This is repeated until the continuation identifier no longer indicates m continuations (for example, "θ").

■ In the data packet of FIG. 3, the processing instruction code (5) indicating dumping of the pointer address memory and return code memory is, for example, C5+, S*.

S, , S, , S@ko [0, 0, 0, 0, O] When a dump packet arrives, the input queue (1)
After that, the first word is latched into the first register (2), and the second word is latched into the second register (3). Among the contents latched in the register (2), the processing instruction code (5) is determined.
The control circuit (7) makes a determination and outputs a control signal (8) that controls the following dump operations of the pointer address memory and return code memory.

Of the contents latched in the register (2), the load (
Pointer address memory (9) and return code memory (20
) is read out. These contents are data register (19)
It can be latched to. A data packet containing the contents of this data register (19) as the second word is outputted to the host interface via the output queue (24).

■ When a dump packet whose processing instruction code (5) indicating a dump in the pointer memory (12) is, for example, [0, 0, 0, 1, (2), the second word is in the second register (3)
are latched respectively. Among the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7), and a control signal (8) for controlling the dump operation of the pointer memory described below is output. Load (dump) the contents latched in the register (2)
Pointer memory (1) with address (25) as address
2) is read, and its contents are latched into the data register (19). The contents of this data register (19) are
Each data packet is outputted to the host interface via an output queue (24).

O difference memory (11> processing instruction code (11) indicating dump)
When a dump packet whose value 5) is, for example, [0, 0, 1, 0, 0] arrives, it passes through the input queue (1), and the first word is stored in the register register (2), and the second word is stored in the second register (2). 3) respectively. Among the contents latched in the register (2), the processing instruction code (5) is sent to the judgment/control circuit (7).
The control signal 8) for controlling the dump operation of the differential memory described below is output. Load (dump) address (2) of the contents latched in the register (2)
5) Read the differential memory (11) using the address,
This content is latched into the data register (19). A data packet containing the contents of this data register (19) as the second word is outputted to the host interface via the output queue (24).

◎ Processing instruction code (5) indicating data memory dump
For example, when a dump packet arrives with [0, 0, 0, 0, 1], the first word is transferred to the first register (2) and the second word is transferred to the second register (3) via the input queue (1). Each is latched. Among the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7), and a control signal (8) for controlling the following data memory dump operation is output. Load (dump) address (25) of the contents wrapped in the first register (2)
The data memory (18) is read out using the address , and its contents are latched into the data register (19). A data packet containing the contents of this data register (19) as the second word is outputted to the host interface via the output queue (24).

(G) Effects of the Invention According to this invention, by giving the set name of a data set using a pointer update data packet, it is possible to dynamically change the pointer that is the address where the element of the data set is stored. . This corresponds to using the set name as a set name for another data set. In this way, by using the set name of a data set that is no longer needed as the set name of another set, it is possible to handle an infinite number of data sets, such as 0 or more, so the present invention can handle them. The number of data sets can be infinite.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of the data storage device of the present invention, FIG. 2 is a block diagram of a system using the data storage device of the present invention, and FIGS. 3 and 4 are diagrams of data packets used in the present invention. FIG. 5 is a block diagram showing an overview of the present invention, and FIG. 6 is another block diagram showing an overview of the present invention. (1)...Dairiki cue, (2)...Second register,
(3)...Second register, (7)...Judgment/control circuit, (9)...Pointer address memory, (11)...
... Differential memory, (12) ... Pointer memory, (1
3)...Difference register, (14)...Pointer update means, (16)...Pointer register, (18)...
・Data memory, (19)...Data register, (2
0)...Return code memory, (21)...Header register, <24)...Output queue.

Claims (6)

[Claims] (1) A data memory in which one or more data sets are stored, a pointer memory that stores address information where the elements of the data set are stored, and a pointer memory in which the elements of the data set are stored in the pointer memory. It consists of a pointer address memory that stores the address where address information is stored, and a determination control circuit that determines and controls processing based on a processing instruction code that indicates the type of processing included in the data packet. A data storage device characterized in that the data element is read out or the contents of the pointer memory are changed under the control of the determination control circuit in accordance with the arrival of the data element. (2) In response to the arrival of a pointer change data packet holding the processing instruction code indicating a change in pointer value, the set name, and a new pointer value, the contents of the pointer memory corresponding to the data set are changed to the new pointer value. and referring to the pointer address memory by the set name of the data set in response to the arrival of a read data packet holding the processing instruction code indicating reading of a data element and the set name of the data set. A data storage device according to claim 1, characterized in that data elements in a data memory are read out. (3) A data memory in which one or more data sets are stored, a pointer memory that stores address information in which the elements of the data set are stored, and a pointer memory in which the elements of the data set are stored in the pointer memory. a pointer address memory that stores an address where address information is stored; a difference memory that stores a difference between addresses in the data memory of two data elements to be referenced consecutively in the same data set; It consists of a pointer update means that generates a new pointer value from the contents of the pointer memory and the contents of the differential memory, and a determination control circuit that determines and controls the process based on a process instruction code indicating the type of process included in the data packet, A data storage device, wherein a data element is read out or the contents of the pointer memory are changed under the control of the determination control circuit in response to the arrival of a packet containing a code. (4) rewriting the contents of the pointer memory of the data set to the new pointer value in response to the arrival of a pointer change data packet holding the processing instruction code indicating a pointer change, the set name, and a new pointer value; In response to the arrival of a plurality of read data packets holding the processing instruction code indicating reading of a data element and the set name of the data set, successively referring to the pointer address memory by the set name of the data set, The data storage device according to claim 3, characterized in that a plurality of data elements within the same data set in the data memory are successively read by continuously updating a pointer by a pointer updating means. . (5) A set name updating means is provided for updating a set name in accordance with a continuation identifier indicating whether or not reference to the data memory is continued, and further, the pointer address memory stores the continuation identifier and each time the data memory is read. Then, in response to the arrival of one of the data packets, the set name is updated by the set name update means according to the continuation identifier, and the operation of referring to the pointer address memory again using the updated set name is repeated. 5. The data storage device according to claim 4, wherein data elements spanning a plurality of data sets in the data memory are read out continuously. (6) the pointer address memory, pointer memory;
6. The data storage device according to claim 5, wherein reference operations to each of the data memory and the data memory are performed in parallel.