JPS63261443A - Data storage device - Google Patents

Abstract

PURPOSE:To continuously and independently read out elements in a data set by dividing a pointer memory and a difference memory into plural blocks and allocating these blocks to respective programs. CONSTITUTION:A data packet holds a set name and an environment number and loads the set name to a counter in a pointer address memory (pam). The contents of the memory (pam) are read out by using the output of the counter as an address, the environment number is added to the read contents and the added result is latched to registers r1, r2. The contents of the pointer memories pm1, pm2 and the differential memories dim1, dim2 are read out by using the contents of the registers r1, r2 as addresses and latched to an address register (ar) of a data memory (dm). The contents of the memory (dm) are read out by using the contents of the register (ar) as an address. Pointers and differences are added by a pointer updating means (pc) and the added result is written in the memory (pm). Thus, the elements in the data set can be continuously read out.

Description

[Detailed Description of the Invention] (a) Industrial Application Field This invention relates to a data storage device used in computer systems, etc., and in particular to a data storage device for efficiently storing and referencing data sets such as array data. It is related to storage devices.

(B) Conventional technology In general, a computer system is composed of a data processing device, a data storage device, etc., and the data processing device reads data from the data storage device, performs some processing, and writes the data to the data storage device. Processing proceeds by repeating this cycle.The problem of overhead (processing waiting time) in a data processing device for referring to a data storage device is common to various computer systems.

For example, even in data-driven (data flow) computer systems, systems that connect data processing devices and data storage devices have been proposed and realized (this -
An example is disclosed in pages 205 to 209 of Nikkei Electronics, published on April 9, 1981), and in the data storage device of such a system, large amounts of data are continuously stored. When reading data, the processing device had to give an address to the storage device each time one piece of data was read. Furthermore, when referring to a specific element of a data set such as array data, the processing device must calculate and generate an address where the desired element is stored.

In contrast, the present applicant proposed a storage device that generates an address where an element of a data set is stored when a set name of a data set is given, and a storage device that generates an address where an element of a data set is stored simply by giving a single set name. We have successfully developed a storage device that can read data continuously, and a storage device that automatically sets the address of the next data element to be read in the data set after it has been read in the manner described above.

(c) Problems to be solved by the invention However, in the conventional storage device as described above, the address (pointer) where an element of a data set is stored and the difference between the addresses of two elements in the data set Since the method can only have one storage location for each set name, it cannot handle cases where multiple users read a single storage device independently and with the same set name.Therefore, this invention The main purpose of this is that even if multiple users run the same program independently, if each user successively gives the set name of the data set, the desired data elements for each user can be successively delivered. To provide a storage device that can read data from multiple data sets, and a storage device that allows each user to continuously read a plurality of data elements spanning a plurality of data sets by sequentially giving one set name to each user. That's true.

(D) Means for Solving the Problems As shown in FIG. 5 and FIG. The differential memory (d i m) that can store the difference between both addresses where one element is stored is stored in multiple pro//
(p m 1 ), (p m 2 ), ..., (d
By dividing the data into (ml), (dim2), etc. and allocating these blocks to each program executed by each user, each user can independently read the elements in the data set continuously. It is a data storage device that can

(E) Function According to the data storage device of the present invention (see FIG. 5), data packets for reading from the memory are assigned to the set name of the desired data set and to each program executed by each user. The environment number (4) shown in FIG. 4 is held. When a data packet to be read from the memory arrives, the set name is first stored in the pointer address memory (PAN), for example, by the counter (C in the case of the invention shown in FIG. 6, the set name update means (f'nc)). ))
Next, the pointer address memory (pam) is read using the output of this counter as an address. The environment number (4〉) in the data packet is added to the read pointer address by f1, and the register (rl) (
r2) and latched. This register (rl)
Pointer memory (p m 1 ) divided into blocks with the contents of (r2) as address 7, (p m 2 >・
..., and differential memory (di ml), (dirn2
), . . . The read pointer is latched to the address register (ar) of the data memory (dm). The data memory (dm) is accessed using this as an address. Pointers and differences are pointer update means (
pc), and this value is added to the pointer memory (p
m). Furthermore, according to the second invention (see FIG. 6), mum included in the pointer address memory
If Besshi instructs continuation, the counter (C) is incremented and the same operation is performed. This is repeated until the J1m identifier no longer instructs continuation. Furthermore, multiple packets holding the same set name When , the above operations are performed successively.

Embodiment Figure 2 shows an overview of a data flow computer system as an example of a system using the data storage device of the present invention. A network interface (N I ) (N I ) (N
I), Data Storage Device (DM), Data Flow Computing Device (DFC), Host Interface ()
II) has been connected, and a host computer (HC) is connected to this host interface (HI).

The data storage device of such a system stores data (such as image data, etc.) used by the data flow calculation device (DFC) when executing a data-driven (data blow) program including write commands and read commands. array data) is stored, and the data blow calculation system WL (DF
In the process of C) executing a data-driven program, the data storage device is responsible for executing write commands and read commands according to control information of data packets.

FIG. 1 shows the configuration of the data storage device of the present invention. In the device shown in the same figure, (1) is an input queue, (2) is a register that holds the first word (header) of an input packet, and (2) is a register that holds the first word (header) of an input packet. 3)
is the register that holds the second word (data) of the input packet, (4) is the environment number, (5) is the processing instruction hood, (6)
is the data held by the input packet, and (7) is the judgment/
Control circuit, (8) is a control signal, (9) is a pointer address memory, (10) is a register that holds the environment number and Voitor address, (11) is a differential memory, (12) is a pointer memory, (13) is a difference register, (14) is pointer update means (adder), <15) is difference value, (16
) is a pointer register, (17) is a pointer value, (1
g) is the data memory, (19) is the output packet data register, (20) is the return food memory, (21)
) is the header register of the output packet, (22) is the return food, (23) is the unchanged information, (24) is the output queue, (25) is the load (dump) address, <26) is the collection name, (27) indicates the means for changing the set name.

Next, the processing operation of the device of the present invention will be explained in detail for each input packet. The structure of the input packet is a two-word data packet as shown in FIGS. 3 and 4 (a), and the processing is performed using the processing instruction hood (processing instruction hood, module number, etc.), which is one of the control information (processing instruction hood, module number, etc.). 5).

■ In the data packet shown in FIG. 3, the processing instruction code (5) indicating loading of the pointer address memory and return food memory is 5 bits, for example [S+, Ss
, Ss, 54, S feeling]■[0,1,0,0゜0
] When a load packet arrives at the input end, it passes through the input queue (1) and the first word of the packet is the first word (header).
Register (2) that holds (hereinafter referred to as the second register)
Then, the second word is latched into a register (3) (hereinafter referred to as the second register) that holds the second word data of the packet. Among the contents latched in the first register (2),
The processing instruction code (5) is determined by the determination/control circuit (7), and a control signal (8) for controlling the following loading operations of the pointer address memory and return code memory is output. Among the contents latched in the register (2), the data (6) held by the input packet using the load (dump) address (25) as the address is transferred to the pointer address memory (9) and the return code memory (20).
), there are no output packets.

■ When a load packet with a processing instruction code (5) indicating loading of the differential memory (11), for example [0, 1, 1, 0, 0] arrives, the 11th one is sent through the input queue (1) to the 2), the second word is latched into the second register (3), respectively. Among the contents latched in this register (2), the processing instruction code (5) is the judgment/control circuit (
7), and a control signal (8) for controlling the loading operation of the differential memory (11) is output. Among the contents wrapped in the register 2), there is no output packet that writes the data (6) held by the input packet to the differential memory (11) using the load (dump) address 25) as an address.

■ When a load packet whose processing instruction hood (5) indicating loading of pointer memory (12) is, for example, [0, 1, 0, 1, 0] arrives, it passes through the input queue (1) and
The gth word is in the register (2), the second word is in the second register (3), and the second word is in the second register (3).
) are respectively latched. Among the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7), and the control signal (8) that controls the loading operation of the pointer memory (12) is Output. Also, among the contents latched in the second register (2), the load (
The data (6) held by the input packet is transferred to the pointer memory (12) using the dump) address (25) as the address.
), there are no output packets.

■ When a load packet whose processing instruction code (5) indicating loading of the data memory (18) is, for example, [0, 1, 0, 0, 1] arrives, the first word passes through the input queue (1). The second word is in the register (2), and the second word is in the second register (3).
are wrapped respectively. Among the contents latched in the register (2), the processing instruction code (5) is the judgment/control circuit (
7), and a control signal (8) for controlling the following data memory loading operation is output. No. Rujistha (
2) Among the contents latched, the data (6) held by the input packet is written to the data memory (18) using the load (dump) address (25) as the address.
There are no output packets.

■ It is a data packet as shown in FIG. 4(a), and the processing instruction hood (5) indicating pointer setting is
, St, Ss, S-, Sg Coco-1, X, 0
, 1゜0], the first word passes through the input queue (1〉) and is transferred to the second word register (2).
Each word is latched into the second register (3). Among the contents latched in the register (2), the processing instruction hood (5) is determined by the determination/control circuit (7), and a control signal (8) for controlling the following boiling settings is output. Among the contents latched in the register (2), the set name is loaded into the set name update means (27), and the pointer address memory (9) is read out using this as an address.This output of the pointer address memory (9) , and of the contents of the first Rujista (2), the environment number (4) is
It is latched into the pointer address holding register (10). This environment number/pointer address holding register (10
) is used as an address to write the data (6) held by the input packet into the pointer memory (12).

On the other hand, 20) is read out in the return code memory using the contents of the set name updating means (27) as an address, and the return hood (22) and unchanged information (23) are latched into the header register (21). An acknowledge packet whose first word is the contents of the header register (21) is shown in Figure 4 (b).
) is output via an output queue (24).

■ For example, if the processing instruction code (5) indicating the difference setting is [
1, .Among the contents latched in the register (2), the processing instruction code (5) has been successfully determined by the determination/control circuit (7), and the control signal (8) that controls the setting of the following differences
is output.

Out of the contents latched in the register (2), the set name is loaded into the set name update means (27), and the pointer address memory (9) is read out using this as an address. No. Rujistha (
Among the contents of 2), the environment number (4) is latched into the environment number/pointer address holding register (10). The data (6) held in the input packet is written into the differential memory (11) using the contents of the environment number/pointer address holding register (10) as an address.

On the other hand, the return code memory (20) is read using the set name update means (27) as an address, and the return code (22) and unchanged information (23) are stored in the header register (
21). An acknowledge packet whose first word is the contents of the header register (21) is sent to the output queue (2
4) and then output.

■ When an operand packet arrives whose processing instruction code (5) indicating a write that outputs an acknowledge packet is, for example, [1,X,1°1.0, the input queue (1
), the 1rI 4th word becomes the 2nd word (2), and the 2nd word becomes the 2nd word.
Each is latched in register (3). No. Rujistha (
Among the contents latched in 2), the processing instruction code (5)
is successfully determined by the determination/control circuit (7), and a control signal (8) is output that controls writing to output the following acknowledge packet. Among the contents latched in the register (2), the set name is loaded into the set name update means (27), and this is used as an address in the pointer address memory (
9), of this output of the pointer address memory (9) and the contents of the register (2), the environment number (
4) is the environment number/pointer address holding register (10
) is latched. The contents of the environment number/pointer address holding register (10) are used as an address to read out the pointer memory (12) and the differential memory (11).The output of the differential memory (11) is stored in the differential register (13) and ) output is pointer register (16
) and write the data (6) held by the input packet into the data memory (18) using the contents (17) of the pointer register (16) as an address. The contents of are added by a pointer update means (14) composed of an adder and written to the read address of the pointer memory (12), while the set name update means (27) is used as an address to write the return food memory (20). The read, return code (22), and unchanged information (23) are latched into the header register (21). An acknowledge packet containing the contents of the header register (21) as one word is output via the output queue (24).

■ The processing instruction hood (5) indicating a write without outputting an acknowledge packet is, for example, [1,X.

1.1, when one operand packet arrives, the first word is latched into the register (2) and the second word is latched into the second register (3) after passing through the input queue (1). Among the contents latched in the register (2), the processing instruction hood (5) has been successfully determined by the judgment/control circuit (7), and the control signal (8) that controls writing without outputting the following acknowledge packet is output. be done. Among the contents latched in the register (2), the set name is
7) and read out the pointer address memory (9) using this as an address. Among this output of the pointer address memory (9) and the contents of the register (2), the environment number (4) is the environment number/pointer It is latched into the address holding register (10). Then, the content of the environment number/pointer address holding register (10) is used as an address to the pointer memory (12) and the differential memory (11).
The output of the differential memory (11) is latched to the differential register (13), the output of the pointer memory (12) is latched to the pointer register (16), and the contents (17) of the pointer register (16) are input as an address. There is no output packet that writes the data (6) held by the packet into the data memory (18).

■ For example, if the processing instruction code (5) indicating reading is [1
,x,o,1. t], the first word is transferred to the input queue (1) and the first word is transferred to the first word register (2).
), the second word is latched into the second register (3), respectively. Among the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7), and a control code (8) for controlling the following reading is output. Among the contents latched in the register (2), the set name is loaded into the set name update means (27), and the pointer address memory (9) is read out using this as an address.
This output of the pointer address memory (9) and the environment number (4) of the contents of the register (2) are latched into the environment number/pointer address holding register (10).

This environment number/pointer address holding register (10)
The pointer memory (12) reads out the pointer memory (12) and the differential memory (11) using the contents of the address as an address.
) is stored in the pointer register (16), and the differential memory (
The outputs of 11) are respectively latched in the difference registers (13), the data memory (18) is read out using the contents (17) of the pointer register (16) as an address, and the contents are latched in the data register (19). Difference register (1
3) and the contents of the pointer register (16) are added by the pointer update means (14), and the contents of the pointer memory (1
Write to the address read in 2).

On the other hand, the return code memory (20) is read using the set name updating means (27) as an address, and the return code memory (20) is read out using the set name updating means (27) as an address.
22), and the unchanged information (23) is stored in the header register (2
1) and sets the contents of the header register (21) to 1.
A data packet with the contents of the data register (19) as the second word is output via the output queue (24).

Now, if the continuation identifier consisting of a 1-bit flag of data included in the pointer address memory (9) or return food memory (20) or provided independently indicates continuation with, for example, "°1", then the set Name update means (2
7) increments the contents, stops the output of the input queue (1), and causes the register (2) to hold its contents. The pointer address memory (9) is read out using the contents of the updated set name updating means (27) as an address. Out of this output of the pointer address memory (9>) and the contents of the register (2), the environment number (4) is read out. ) is latched in the environment number/pointer address holding register (10).The pointer address holding register (
Pointer memory (12) with the contents of lO) as the address
, and read the differential memory (11). The output of the pointer memory (12) is latched to the pointer register (16), the output of the differential memory (11) is latched to the differential register (13), and the contents of the pointer register (16) are latched. The data memory (18) is read using (17) as the address, and its contents are latched into the data register (19). The contents of the difference register (13) and pointer register (16) are added by the pointer updating means (14) and written to the read address of the pointer memory (12).

On the other hand, the return code memory (20) is read out using the set name actualization means (27) as an address, and the return code (
22) and the contents of the register (2), excluding the return code, are launched into the header register (21).The contents of the header register (21) are taken as the first word, and the contents of the data register (19) are loaded into the header register (21). A data packet having the second word is output via the output queue (24). This is repeated until the continuation identifier no longer indicates continuation (for example, "0").

0 In the data packet of FIG. 3, the processing instruction code 5) indicating dumping of the pointer address memory and return code memory is, for example, [S+, St.

When a dump packet with s, , s, , St code [0, 0, O, 0, 0 arrives, it is sent to the input queue (1).
The first word is latched into the second register (2), and the second word is latched into the second register (3). Among the contents latched in the register (2), the processing instruction code (5) has been successfully determined by the determination/control circuit (7), and the control signal (8) that controls the dump operation of the pointer address memory and return code memory below. ) can be output.

Of the contents latched in the register (2), the load (
dump) address (25) as the address, pointer address memory (9), and return code memory (20
), these contents are stored in the data register (19)
latched to. A data packet whose second word is the contents of this data register (19) is outputted to the host interface via the output queue (24).

When a dump packet whose processing instruction code (5) indicating a dump in the O pointer memory (12) is, for example, [0, 0, 0, 1, 0] arrives, it passes through the input queue (1) and the first word is transferred to the first register. In (2), the 23rd person is the second register (3)
You can cut 7 pieces each. Among the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7), and a control signal (8) for controlling the dump operation of the pointer memory described below is output. The pointer memory (
12>, this content is the data register (19)
wrapped in A data packet whose second word is the contents of this data register (19) is outputted to the host interface via the output queue (24).

@ When a dump packet whose processing instruction code (5) indicating a dump of the differential memory (11) is [0, 0, 1', 0, 0] arrives, it is sent to the input queue (1) and sent to 1.
The word and the 28th F1 are latched in the register (2) and the second register (3), respectively. Among the contents latched in the register (2), the processing instruction code (5) is determined by the determination/control circuit (7), and the control signal (8) that controls the dump operation of the differential memory shown below is output. . The differential memory (11) is read out using the load (dump) address (25) of the contents latched in the register (2), and this content is latched in the data register (19). A data packet whose second word is the content of this data register (19>) is output to the host interface via the output queue (24).

◎ Processing instruction code (5) indicating data memory dump
For example, when a dump packet with [0, 0, 0, 0, 11] arrives, the first word goes through the input queue (1) to the first word register (2), and 2gl! The second register (3) is latched into the second register (3). Among the contents latched in the register (2), the processing instruction hood (5) is successfully determined by the determination/control circuit (7), and the control signal (8) that controls the dump operation of the data memory below is output. . Among the contents latched in the register (2), the load (dump) address <2
5) is used as the address to read the data memory (18), and the contents are latched into the data register (19>).

A data packet whose second word is the contents of this data register (19) is outputted to the host interface via the output queue (24).

(g) Effects of the Invention According to this invention, when multiple users independently read a storage device, the data backup for reading the memory uses an environment number assigned to each user. When a different user reads a data element, even if the same set name is given, the pointer memory of the new address (same address of a different block),
and the differential memory, and updates the pointer at that address to the address of the next element to be read in the data set. Therefore, if each user independently and consecutively gives a set name, each user can read out the elements in the data set independently and consecutively. is a previously filed storage device that allows multiple users to independently and continuously read out a single storage device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of the data storage device of the present invention, FIG. 2 is a block diagram of a system using the data storage device of the present invention, and FIGS. 3 and 4 are diagrams of data packets used in the present invention. FIG. 5 is a block diagram showing an overview of the present invention, and FIG. 6 is another block diagram showing an overview of the present invention. (1)...Input queue, 2>...Second register,
(3)...Second register, (7)...Judgment/control circuit, (9)...Pointer address memory, (11)...
... Differential memory, (12) ... Pointer memory, (1
3)...Difference register, (14)...Pointer update means, (16)...Pointer register, (18)...
・Data memory, (19)...Data register, (
20)...Return code memory, (21)...Header register, (24)...Output queue.

Claims (6)

[Claims] (1) A data memory in which one or more data sets are stored, a pointer memory that stores address information in which the elements of the data set are stored in blocks, and elements of the data set in the pointer memory. A pointer address memory that stores an address where address information is stored, and stores a difference that is the difference between the addresses in the data memory of two data elements that should be continuously referenced in the same data set. It consists of a differential memory and a pointer update means for generating a new pointer value from the contents of the pointer memory and the contents of the differential memory, and includes a set name of the data set and an environment number identifying the environment in which the data set is referenced. A data storage device characterized in that a block of a pointer memory is selected in response to successive arrivals of data packets, and data elements in the data memory are successively read. (2) A data memory in which multiple data sets are stored, a pointer memory that stores address information in which the elements of the data set are stored in blocks, and the elements of the data set in the pointer memory are stored. A pointer address memory that stores an address in which address information is stored and a continuation identifier indicating whether or not the reference to the data memory is continued; a differential memory that stores a difference between addresses in the data memory;
a pointer update means for generating a new pointer value from the contents of the pointer memory and the contents of the differential memory; and a set name update means for updating a set name using the continuation identifier, the set name of the data set; and reading out specific element data in the data memory in response to the arrival of a data packet containing the environment number, and updating the set name according to the continuation identifier using the set name updating means, A data storage device characterized in that a specific data element of each of a plurality of data sets is successively read, and a plurality of data elements of each of the plurality of data sets are successively read by successive arrivals of the data packets. (3) The set name refers to the pointer address memory, and refers to the pointer memory and the differential memory using the pointer address output in response to the reference and the environment number. Data storage device according to clause 2. (4) The pointer memory is divided into a plurality of blocks, and the pointer memory is referenced by selecting one of the blocks according to the environment number and making the output of the pointer address memory the address of the block. 4. The data storage device according to claim 3, wherein said differential memory is referred to by said output of said pointer address memory. (5) The pointer memory and the differential memory are divided into a plurality of blocks, and one of the plurality of blocks of the pointer memory and one of the plurality of blocks of the differential memory are divided according to the environment number. The data storage according to claim 3, characterized in that the pointer memory and the differential memory are referenced by selecting one of the blocks and making the output of the pointer address memory the address of each selected block. Device. (6) The fourth aspect of the present invention is characterized in that the reference operation of the pointer address memory, the reference operation of the data memory, the reference operation of the pointer memory and the differential memory, and the update of the pointer are performed in parallel. 6. The data storage device according to items 5 to 6.