JP4363431B2 - Data transfer method - Google Patents

Description

  The present invention relates to a computer system that requires data transfer at regular intervals between a control device and a controlled device to be controlled, such as a programmable controller.

  Conventionally, in a programmable controller that controls various devices constituting an industrial facility, the industrial facility is controlled by taking in information from a sensor that reports the state of each device and giving an instruction to an actuator of each device. For the purpose of facilitating the creation of a control program executed on the programmable controller, a memory called a control memory is placed in the programmable controller, and sensor information and actuators of each device to be controlled are stored in each bit on the control memory. Map information. The programmable controller periodically communicates with each device via a network, and sensor information is transferred from the device side to the programmable controller side, and actuator information is transferred from the programmable controller side to the device side. The contents of the memory are matched with the state of the sensor information and actuator information of the device. By providing the control memory with such characteristics in the programmable controller, the control program can control each device only by accessing the control memory.

  However, in recent years, with the increase in size and performance of industrial equipment, the number of sensors and actuators in each device has increased with the increase in the number of devices to be controlled by the programmable controller. As a result, the amount of data transferred through the network between the programmable controller and each device increases and the processing of the control program also increases, so that the control program called a control cycle starts executing from the start of execution of the next control program It took a long time to be done. In order to shorten the control cycle, it is necessary to shorten the data transfer time between the programmable controller and each device in addition to shortening the execution time of the control program.

  There are two methods for shortening the data transfer time: a method using a high-speed network and a method for improving the efficiency of data transfer.

  In the method using the high-speed network, the data transfer performed between the programmable controller and each device becomes high speed, so that the data transfer time can be shortened. In order to improve the efficiency of data transfer, there is a method in which the control memory is divided into a sensor area for storing sensor information and an actuator area for storing actuator information. If sensor information and actuator information are mixed on the control memory, a table indicating whether the data of each address in the control memory is sensor information or actuator information is required in the programmable controller. In this case, since the table has to be drawn at the time of transfer between the program controller and each device, extra overhead is applied. In addition, when determining whether the information sent from the programmable controller on the device side is sensor information or actuator information, the programmable controller must also transfer sensor information, which is extra data, to the device side. Therefore, the amount of data transfer increases and it takes a long transfer time. The same can be said for sensor information. However, by dividing the area of the control memory, it is possible to eliminate the overhead of determining whether it is sensor information or actuator information and unnecessary data transfer between the programmable controller and each device. Data transfer time can be shortened.

  As described above, in order to increase the data transfer time, there are a method of using a high-speed network and a method of improving transfer efficiency by eliminating extra overhead and data transfer.

  In the former method using a high-speed network, the high-speed network itself is expensive, and in order to realize a high transfer speed, a memory having a high access time must be used as a control memory. turn into.

  Next, in the method of improving data transfer efficiency, since the control memory is divided into the sensor area and the actuator area, the sensor information and the actuator information belonging to the same device can be arranged as a group at consecutive addresses on the control memory. Because it is not possible to manage the information of each device, it is not possible to manage each device, and when many devices are controlled, the user interface deteriorates, and it is possible to check the creation of the control program and the operation of the control program on the programmable controller. It becomes difficult.

Another problem is cost. As the number of devices to be controlled increases, the number of sensors and actuators increases, and the capacity of the control memory increases. When the controlled circuit is controlled by analog instead of digital, the analog signal is converted into a 12-bit or 16-bit digital signal by using an A / D (analog / digital) converter. However, when the data bus of the control memory is 8 bits, access to analog data composed of 16 bits is performed twice for each byte. If the access from the communication processor enters between the first access and the second access from the controller, and data simultaneity is lost in the upper 8 bits and lower 8 bits of the analog data, the control is performed correctly. No problems occur. Therefore, many control memory data buses use 16-bit buses accordingly. As described above, the number of pins of the LSI and the memory constituting the controller is increased, so that there is a problem that a large LSI package is required and the cost is increased.

  In view of the above problems, an object of the present invention is to provide a control system that improves the data transfer efficiency between a control device and a controlled device at low cost.

In order to achieve the above object , the present invention provides a memory storing at least a process state and control data, a controller for generating control data based on the process information stored in the memory, and storing process information in the memory. Connected to the memory, the controller, and the processor, and the controller access data and the processor access data can be stored at the same time. Configured to hold a plurality of bit data, and with respect to read access from the controller and processor, the data size of the read access corresponds to the restriction on the size of the bus connected to the memory. The above lead acces are divided into the required number of times. The data to be processed is continuously read from the memory, divided into a plurality of data, stored in a register so that the data from the controller or the processor can be identified, and divided into the plurality of data. Data control for transferring the data stored in the register to the accessed one of the controller and processor so that at least part of the data is stored in parallel with at least a part of the data stored in the continuous register. Device.

In order to achieve the above object , the present invention provides a memory storing at least a process state and control data, a controller for generating control data based on the process information stored in the memory, and storing process information in the memory. Connected to the memory, the controller, and the processor, and the controller access data and the processor access data can be stored at the same time. The write access data size for a write access from the controller or processor, which has a register configured to hold a plurality of bit data and has a data size that exceeds a bus size constraint connected to the memory To the memory required for The write data subject to the write access is stored in the register so that it can be divided into the number of transfers, and the stored write data is stored so that it can be identified whether the data is from the controller or the processor. Data control for writing the write data stored in the register to the memory sequentially in divided units after any of the write data to be transferred to the memory is stored in the register. Device .

As described above , in the present invention, the process data control device operates in the controller that controls the industrial system, thereby guaranteeing data simultaneity to the controller.

  Hereinafter, the present invention will be described with reference to FIGS.

  FIG. 2 shows a control system using a programmable controller. In the control system, the control device 1000, the controlled device 2000, and the control device 1000 and the controlled device 2000 are connected via a network 1200.

  The control device 1000 includes a calculation device 101, a control memory 201, a control data transfer device 301, and a memory controller 401 having a content update determination device 4002 inside. The controlled device 2000 includes an input / output device 2001, a sensor 2101, an actuator 2102, and a device 3000.

  Next, a data flow between the control device 1000 and the controlled device 2000 will be described.

Information flowing between the control device 1000 and the controlled device 2000 is sensor information from one or more sensors 2101 attached to the device 3000 and actuator information to one or more actuators 2102 that control the operation of the device 3000. is there. Further, when the sensor information from the sensor 2101 or the actuator information to the actuator 2102 is assigned to each address of the control memory 201 in the control device 1000 and the control program executed by the control device 1000 wants information from a specific sensor. The sensor information is obtained by reading the address where the sensor information is stored in the control memory 201. Similarly, when it is desired to control a specific actuator, the actuator is controlled by writing the actuator information to an address in the control memory 201 where the actuator information is held. In addition, the bit length of sensor information varies depending on the type of sensor, including 1 bit and several bit lengths. Since the data length varies, the sensor information is input / output device 2001. The control device 1000 collects access units such as bytes (8 bits) and words (16 bits) that can be easily processed, and sends the access units to the control device 1000 via the network 1200 for each access unit. The control device 1000 writes the sensor information collected in the access unit sent from the controlled device 2000 to the corresponding address in the control memory 201. Similarly to the sensor information, a plurality of actuator information is grouped into access units, and the actuator information is written to the assigned address in the control memory. Thereafter, the actuator information is transferred to the controlled device 2000 for each access unit via the network 1200, and the plurality of actuator information collected in the access unit by the input / output device 2001 is divided for each actuator and transferred to the actuator 2102. To do. The actuator 2102 performs an operation on the device 3000 based on the data transferred from the input / output device 2001. As described above, the control device 1000 can control the device 3000 of the controlled device 2000.

  Here, taking the motor control as an example of the controlled device 2000, the operation of the entire control system in FIG. 2 will be described. A motor 3000 of the controlled device 2000 is a device 3000, a sensor 2101 for checking the rotation speed of the motor, and a current control device for controlling a current applied to the motor are an actuator 2102.

  The control program executed by the calculation device 101 in the control device 1000 reads the rotation speed of the motor by the sensor 2101 and compares it with a specified value. If it is higher, the supply current to the motor is reduced to the actuator 2102 to reduce the rotation speed of the motor. If it is low, the actuator 2102 is instructed to increase the motor current by increasing the current supplied to the motor. By controlling the current applied to the motor in this way, the number of revolutions of the motor is controlled to a specified value.

  The access unit is the number of bits that the computing device 101 can read from the control memory 201 at a time, and is 16 bits here.

  This motor control program is given by a ladder diagram. The data flow in FIG. 2 is as follows. The sensor 2101 measures the rotational speed of the motor and outputs it to the input / output device 2001 as an analog value. The input / output device 2001 converts it into 16-bit digital data via an A / D (analog / digital) converter. The converted rotational speed data of the motor is sent to the control device 1000 via the network 1200. The controller 1000 calculates actuator information for the actuator 2102 as follows. The control data transfer device 301 receives the digitized motor rotational speed data and writes it to the address a of the control memory 201. The calculation device 101 reads the address a in the control memory 201 and obtains the rotation speed information of the motor. Next, the specified value is compared with the rotation speed information of the motor, it is determined whether the rotation speed of the motor is higher or lower than the specified value, and the actuator information to the actuator 2102 which is a current control device for the motor is controlled. Write 2-bit data into the memory 201. When the number of rotations of the motor is higher than the specified value, 10 is set by 2-bit information to decrease the supply current to the motor, and when it is low, 01 is set by 2-bit information to increase the supply current to the motor. If the rotation speed of the motor is the same as the specified value, 00 is written in the address b of the control memory 201. Actuator information for the actuator 2102 written at address b is read by the control data transfer device 301 and transmitted to the controlled device 2000 via the network 1200.

  In the controlled device 2000, the input / output device 2001 receives the actuator information sent by the control data transfer device 301 and transfers the received actuator information to the actuator 2102. The actuator 2102 reduces the supply current to the motor if the actuator information transferred from the input / output device 2001 is 01, and conversely increases the supply current to the motor if the actuator information is 10. By doing in this way, the rotation speed of a motor can be kept at a regulation value.

Next, data transfer between the computing device 101 and the control memory 201 will be described. As shown in FIG. 1, the computing device 101 is connected to a control memory 201 via a memory controller 401. FIG. 3 shows the internal structure of the memory controller 401. There are three types of access methods from the computing device 101 to the control memory 201 via the memory controller 401: read, write, and read modify write. Read access is access to read data from the control memory 201, write access is data write access to the control memory 201, and read modify write access is access to rewrite only one bit on the control memory 201. The actuator information to the actuator 2102 described above is 2 bits. Therefore, if actuator information for another actuator is assigned to another bit at the same address b, if the actuator information for the actuator 2102 is simply written at address b, the other actuator information will be rewritten together. It will be. Therefore, the address b including the data of the actuator 2102 is once read (read) from the control memory 201, only the data portion to the actuator 2102 is rewritten (modified), and the rewritten data is written back to the address b of the control memory 201. By performing the (write) process, only the control data to the actuator 2102 can be rewritten. Further, the memory controller 401 has a function of determining whether the data content has been updated by the read-modify-write access by comparing the data read from the control memory 201 and the data to be written at the time of the read-modify-write access. Has a judgment function. With this content update determination function, it is possible to transfer only the data whose data content has been updated at the time of data transfer in the control data transfer device 301 to the controlled device 2000, so that the transmission data can be reduced, and the data transmission time Can be shortened.

  Next, the structure of the memory controller 401 will be described. The memory controller 401 has latches 4011, 4012, 4021, 4022, selectors 4201, 2 inputs and 1 output for selecting one of the two inputs, one input having the bit width of the access unit, and the other input being the input. Bit merge 4202 that outputs an access unit that replaces any one bit in an access unit that is input in one bit with one bit that is the other input. Bus fight in which outputs collide because the bus is a bidirectional bus. 3 state buffers 4301, 4302, and 4303 for preventing data, a content update determination device 4002 for determining whether the data content at the time of read-modify-write has been updated, and a sequencer 4001 that controls the above resources and operates as a memory controller. .

An address bus 141, which is an address output from the computing device 101, becomes an address bus 241 via a latch 4011 and serves as an address input to the control memory 201. Similarly, the data input / output bus 142 from the computing device 101 is connected to the selector 4201 and the bit merge 4202 via the sequencer 4001 and the latch 4012, and the output of the selector 4201 is connected to the data bus 242 of the control memory via the three-state buffer 4301. The data bus 242 is connected to the three-state buffer 4302, the bit merge 4202, and the content update determination device 4002 via the latch 4021, and the output of the three-state buffer 4302 is connected to the data bus 142. . The memory control signal 143 is input to the sequencer 4001 and converted into a memory control signal 244 of the control memory 201. The output to the content update determination bit bus 243 which is a bidirectional bus is output from the output 4131 of the content update determination device 4002 via the three-state buffer 4303, and the input is input to the content update determination device 4002 via the latch 4022. . The bit merge 4202 is connected to the selector 4201 by replacing any one bit of the output of the latch 4021 with the lower 1 bit of the latch 4012. The control signal which is the output of the sequencer 4001 is the latch timing of the latches 4011, 4012, 4021 and 4022, the state of the three-state buffers 4301, 4302 and 4303 (output, high impedance), the select signal of the selector 4201, and the select signal of the bit merge 4202 , The determination enable signal of the content update determination device 4002 is output.

  The operation of the memory controller 401 will be described. The memory controller 401 has three types of operations of read / write / read-modify-write, and is activated from the computing device 101 by an address bus 141, a data bus 142, and a memory control signal 143.

The read access is started by outputting an address from the computing device 101 and a read request from the memory control signal 143. The sequencer 4001 outputs a latch signal to the latches 4011 and 4021, an output signal to the three-state buffer 4302, a high-impedance signal to the other three-state buffers 4301 and 4303, and a read signal to the memory control signal 244 to the control memory 201. The address output from the computing device 101 is output to the address bus 241. In the control memory 201, the data at the address specified by the address bus 241 is output to the data bus 242 and the content update bit information is output to the content update bit bus 243. The contents of the data bus 242 are output to the data bus 142 via the latches 4021 and 3-state buffer 4302, and the read access ends.

  Next, write access will be described. In the write access, an address is written from the computing device 101 to the address bus 141, write data is output to the data bus 142, and a write request is output to the memory control signal 143, and the memory controller 401 is activated. The sequencer 4001 causes the memory control signal 244 to write, the latches 4011 and 4012 to select the latch signal, the selector 4201 to select the latch 4102 side, the address bus 241 and the data bus 242 to respectively select the address bus 141 and the data bus 142. The contents are output, and the contents of the data bus 242 are written at the address specified by the address bus 241. Finally, read modify write access will be described. When the computer 101 outputs an address to the address bus 141, data having the format shown in FIG. 4 to the data bus 142, and a read modify write request to the memory control signal 143, the memory controller 401 is activated. The sequencer 4001 first outputs a latch signal to the latches 4011, 4012, 4021, and 4022, a read signal to the memory control signal 244 to the control memory 201, and outputs the contents of the address bus 141 to the address bus 241. The control memory 201 outputs the data at the address specified by the address bus 241 to 242 and the content update bit to the content update bit bus 243, which are latched in the latches 4021 and 4022, respectively. Next, the sequencer 4001 sets the memory control signal 244 to the control memory 201 as a write request, sets the three-state buffers 4301 and 4303 to the output state, sets the 4302 to the high impedance state, and selects the selector 4021 to the output side of the bit merge 4022. Then, the bit merge 4022 replaces the content of the bit address 901 shown in FIG. 8 with the bit data 902 and outputs a determination enable signal to the content update determination device 4002. The content update determination device 4002 compares the output of the latch 4021 that is read data with the data of the bit merge 4202 that is write data, calculates the content update bit to be written to the control memory 201 in consideration of the value of the latch 4022, and 4131 Output. The output of the bit merge 4202 is output to the data bus 242 via the selector 4201, the three-state buffer 4301, and the contents of the data bus 242 and the content update bit bus 243 are written to the address specified by the address bus 241 of the control memory 201. It is. The above is the operation of the memory controller 401. Time charts of the memory controller 401 are listed in FIGS.

FIG. 5 shows an outline of the content update determination device 4002. The content update determination device 4002 compares the read data 4121 from the control memory 201 at the time of read-modify-write access with the data 4111 to be written to the control memory 201, detects a change in data due to the read-modify-write, and outputs if there is a change. 1 is output to 4131. At this time, if the content update bit of the data in the control memory 201 is already 1, there is an OR gate 5002 for calculating the logical sum in order to save the information. The operation of the comparison circuit 5001 is as follows. The comparison circuit 5001 has four inputs, and includes an input A 4111 and an input B 4121, a comparison enable signal 4141 that is a control signal from the sequencer 4001, and a signal 4142 that provides an output signal at the time of non-comparison. The output of the comparator 5001 is as shown in FIG. 6. When the comparison enable signal 4141 is 0, the comparator 5001 outputs 1 if the input A4111 and the input B4121 match, and outputs 0 if the input does not match. If 1, the value of the output signal 4142 at the time of non-comparison is output as it is. By taking the logical sum of the inverted output of the comparison circuit 5001 and the output of the latch 4022, a signal indicating whether or not the content of data by read-modify-write has changed can be generated.

FIG. 7 shows an overview of the sequencer 4001. The sequencer 4001 reads, writes, and read-modify-write (memory control signal 143) from the computing device 101 based on inputs from the address bus 241 and data bus 142, and latch timings and selectors of the latches 4011, 4012, 4021, and 4022. 4201, selection signal to bit merge 4202, output enable signal to three-state buffers 4301, 4302, and 4303, comparison timing signal 4141 to content update determination device 4002, output selection signal 4142, and read / write timing to control memory 201 The signals 2441 and 2442 are generated. The output selection signal 4142 to the content update determination device 4002 is fixed to 0 in the control device 1000 shown in FIG. The output selection signal 4142 is used when the CPU 501 also serves as the calculation apparatus 101 and the control data transfer apparatus 301 shown in FIG. The memory control signal 143 includes a read request signal 1431 (hereinafter referred to as “RD signal”), a write request signal 1432 (hereinafter referred to as “WR signal”), a read modify write signal 1433 (hereinafter referred to as “RMW signal”), and a wait indicating that the memory access has not ended. The RD signal 1431, the WR signal 1432, and the RMW signal 1433 are inputs to the sequencer 4001, and the WAIT signal 1434 is an output from the sequencer 4001. The memory control signal 244 includes an output enable signal 2441 (hereinafter referred to as OE signal) and a write enable signal 2442 (hereinafter referred to as WE signal). Both the OE signal 2441 and the WE signal 2442 are outputs of the sequencer 4001. The output signal to the content update determination device is a comparison enable signal 4141 and an output setting signal 4142 when not comparing.

FIG. 8 shows a data format 900 output to the data bus 142 by the computing device 101 during RMW. In the data format 900, the least significant bit 0 is composed of write bit data 902, 901 indicating the address in the word of the bit to be rewritten, and for the data in the control memory 201 designated by the address output from the computing device 101, The memory controller 401 reads (reads) data from the control memory 201, replaces (modifies) one bit in the data designated by the in-word address 901 with 1-bit data 902, and writes back to the same address (write). Do.

FIG. 9 shows the configuration of the control data transfer apparatus 301. The control data transfer device 301 reads data from the control memory 201, and outputs the data on the data bus 232 to the network 1200 if the value of the content update bit bus 233 is 1. When data is received from the network 1200, the received data is written into the control memory 201. A memory control signal 234 including an address bus 231, an output enable signal 2341, and a write enable signal 2342 is an output of the transfer control device 3002. The data bus 232 is transferred to the transfer circuit 3001, and the content update bit bus 233 is transferred to the transfer circuit 3001 and the latch 3202. And the output of latch 3202 is connected to tristate buffer 3201. The tristate buffer 3201 is inserted on the output side of the latch 3202 because the output from the control memory 201 and the output of the latch 3202 do not collide with each other on the data bus 232 because the data bus 232 is a bidirectional bus. Further, the transfer device 3001 and the transfer control device 3002 are connected by a data line 3100.

The transfer device 3001 has a transfer determination circuit 3011 inside, and determines whether to output the data on the data bus 232 to the network 1200 by looking at the value of the content update bit bus 233. Further, the transfer control device 3002 has a counter 3012 indicating the address of the control memory 201 inside, and outputs the contents of the control memory 201 to the network 1200 in order by this counter.

  Next, the flow of data in the control device 1000 will be described. The computing device 101 outputs an access request to the memory controller via the address bus 141, the data bus 142, and the memory control signal 143 to exchange data with the control memory 201.

  Timing charts of the operation of the memory controller 401 are given in FIGS. FIG. 10 is a timing chart at the time of reading, FIG. 11 is a timing at the time of writing, and FIG. 12 is a timing chart at the time of read modify writing. In each timing chart, the clock timing at which the computing device 101 starts access is T0.

A time chart at the time of reading is shown in FIG. At the timing of T0, the computing device 101 outputs an address to the address bus 141 and asserts the RD signal 1431. At the timing of T1, the sequencer 4001 sends a latch signal to the latch 4011 at the beginning of T1, causes the latch 4011 to latch the value of the address bus 141, and asserts the WAIT signal 1434 and the OE signal 2441. To the control memory 201, an address is output to the address bus 241 and an OE signal 2441 is output to the memory control signal 244. The control memory 201 outputs the contents of the address specified by the address bus 241 to the data bus 242. At the timing of T2, the sequencer 4001 sends a latch signal to the latch 4021 at the beginning of T2, latches the value of the data bus 242, negates the WAIT signal 1434 and the OE signal 2441, sends an enable signal to the tristate buffer 4302, and latches The data of the output 4121 of 4021 is read into the data bus 142 and the data is output. At the timing of T3, the computing apparatus 101 confirms that the WAIT signal 1434 has been negated, stops outputting to the address bus 141, negates the RD signal 1431, and captures the contents of the data bus 142. The sequencer 4001 stops the enable signal of the three-state buffer 4302 and stops outputting data to the data bus 142. The above is the operation of the memory controller 401 at the time of reading.

FIG. 11 shows a time chart at the time of writing. At the timing of T0, the computing device 101 outputs an address to the address bus 141, writes data to the data bus 242, and asserts a WR signal 1432. At the timing of T1, the sequencer 4001 sends a latch signal to the latches 4011 and 4012 at the beginning of T1, causes the latch 4011 to latch the value of the address bus 141 and the latch 4012 to latch the value of the data bus 142, respectively.
The WE signal 2442 is asserted, and a selection signal for causing the selector 4201 to select the output 4102 of the latch 4012 is sent to the tristate buffers 4301 and 4303. As a result, an address is output to the address bus 241, data is output to the data bus 242, content update bit information is output to the content update bit bus 243, and a WE signal 2442 is output to the memory control signal 244, and the control memory 201 is addressed by the address bus 241. The contents of the data bus 242 and the content update bit bus 243 are written into the memory. At the timing of T2, the sequencer 4001 negates the WAIT signal 1434 and the WE signal 2442, and tristate buffers 4301,
The enable signal of 4303 is stopped, and data output to the data bus 242 and the content update bit bus 243 is stopped. At the timing of T3, the computing apparatus 101 confirms that the WAIT signal 1434 has been negated, stops outputting to the address bus 141 and the data bus 142, and negates the WR signal 1432. The above is the operation of the memory controller 401 at the time of writing.

FIG. 12 shows a time chart during read-modify-write. At the timing of T0, the computing device 101 outputs an address to the address bus 141, outputs write data to the data bus 242, and asserts an RMW signal 1433. At the timing of T1, the sequencer 4001 sends a latch signal to the latches 4011 and 4012 at the beginning of T1, causes the latch 4011 to latch the value of the address bus 141 and the latch 4012 to latch the value of the data bus 142, respectively, and the WAIT signal 1434 and the OE signal 2441. Is asserted. To the control memory 201, an address is output to the address bus 241, and an OE signal 2441 is output to the memory control signal 244. The control memory 201 outputs the contents of the address specified by the address bus 241 to the data bus 242. At the timing of T2, the sequencer 4001 sends a latch signal to the latches 4021 and 4022 at the beginning of T2, causes the latch 4021 to latch the value of the data bus 242, causes the latch 4022 to latch the value of the content update bit bus 243, and negates the OE signal 2441. To do. At the timing of T3, the sequencer 4001 sends a selection signal that causes the selector 4201 to select the output 4111 of the bit merge 4202 and a bit address that replaces the bit merge 4202 with an enable signal to the four-state buffers 4301 and 4303, and the content update determination device 4002 The enable signal 4141 and the WE signal 2442 are asserted, and the WAIT signal 1434 is negated. As a result, an address is output to the address bus 241, data is output to the data bus 242, content update information is output to the content update bit bus 243, and a WE signal 2442 is output to the memory control signal 244, and the control memory 201 is set to the address specified by the address bus 241. The contents of the data bus 242 and the content update bit bus 243 are written. At the timing of T4, the sequencer 4001 negates the enable signal 4141, the WAIT signal 1434, and the WE signal 2442, stops the enable signal of the three-state buffers 4301 and 4303, and stops the data output to the data bus 242 and the content update bit bus 243. At the timing of T5, the calculation apparatus 101 confirms that the WAIT signal 1434 has been negated, stops outputting to the address bus 141 and the data bus 142, and negates the RMW signal 1433. The above is the operation of the memory controller 401 during read-modify-write.

  The operation in the content update determination device 4002 is as follows.

During a read-modify-write operation, the same address in the control memory 201 is read and then the contents of the control memory 201 are rewritten and written back. At the time of read-modify-write, the enable signal 4141 of the comparison circuit 5001 is asserted, and if A4111 that is data read from the control memory 201 that is two inputs of the comparison circuit 5001 and B4121 that is data to be written to the control memory 201 match, If the output 5101 is 1 and 4111 and 4121 do not match, 0 is output. In addition, the contents of the content update bit bus 243 are latched by the latch 4022 at the time of reading of the read modify write access, and the contents of the latch 4022 and the comparison result of the comparison circuit 5001 are logically summed at the time of writing, thereby updating the contents by the read modify write. Prevent missing bits.

  At the time of reading and writing, the enable signal 4141 of the comparison circuit 5001 is negated and 0 is output to the output 5101 of the comparison circuit 5001 from the truth table shown in FIG. Regardless of the value of 4132, 1 is output. Since the content update determination cannot be performed because no read operation is involved at the time of writing, the content update bit is set to 1.

  The flow of data between the control memory 201 and the control data transfer device 301 is based on the sensor data transferred from the controlled device 2000 via the address bus 231, the data bus 232, the content update bit bus 233, and the memory control signal 234. And the actuator information on the control memory 201 is transferred to the controlled device 2000.

FIG. 13 and FIG. 14 show timing charts of the access operation of the control data transfer apparatus 301 to the control memory 201. FIG. FIG. 13 is a timing chart when reading into the control memory 201, and FIG. 14 is a timing chart when writing into the control memory 201. When transferring actuator data from the control device 1000 to the controlled device 2000, the control data transfer device 301 sends address information to the address memory 231 and an output enable signal to the memory control signal 234 from the control memory 201 to the control memory 201. The data at the address specified by the bus 241 is output to the data bus 232 and the content update bit information is output to the content update bit bus 233. The control data transfer device 301 looks at the value of the content update bit bus 233. If the value is 0, the control data transfer device 301 determines that the data has not been updated from the previous transfer to the controlled device 2000 and transfers the data to the controlled device 2000. There is no need to do it. On the other hand, if the value of the content update bit bus 233 is 1, it is determined that the content of this data has been updated since the previous transfer, and this data is transferred to the controlled device 2000 via the network 1200 and at the same time the content update bit information is set to 0. Reset. When sensor data is transferred from the controlled device 2000 side to the controller side, the control data transfer device 301 sends the address information to the address memory 231 from the control memory 201 to the control memory 201, and the control data transfer device 301 sends data from the network 1200 to the data bus 232. A write signal is sent to the received data information and memory control signal 234, and the data is written to the address specified by the address bus 231 of the control memory 201. At this time, the content of the content update bit is 0. By using this content update determination bit, only data that has been changed by the access of the computing device 101 is transferred to the controlled device 2000 side, so that extra data transfer can be omitted. Time can be shortened.

In the read timing chart shown in FIG. 13, the transfer control device 3002 outputs the value of the counter 3002 to the address bus 231 and asserts the OE signal 2341 at the timing T0. The control memory 201 outputs the contents of the address designated by the address bus 231 to the data bus 232 and the contents update bit information to the contents update bit bus 233. At the timing of T1, the transfer control circuit 3002 sends a latch signal to the buffer 3201 and the latch 3202, the values of the data bus 232 and the content update bit bus 233 are latched in the buffer 3201 and the latch 3202, respectively, and the OE signal 2341 is negated. The content determination circuit 3001 looks at the content of the latch 3202 and determines that no transfer is made if it is 0, counts up the counter 3012, stops the address output to the address bus 231 and ends the read operation. If it is 1, in order to transfer the data to the controlled device 2000, the data is output to the network 1200 at the timing of T2, and the transfer control device 3002 asserts the WE signal 2342 and enables the three-state buffer 3211. A signal is sent, the content of the latch 3202 holding the read data is output to the data bus 232 as 0 to the content update bit bus 233, and the content update bit of the address in the control memory 201 is reset. At the timing of T3, the transfer control device 3002 negates the WE signal 2342 and stops outputting the address to the address bus 241 to complete the timing chart.

  In the write timing chart shown in FIG. 14, when the transfer circuit 3001 receives data from the controlled device 2000 via the network 1200, the transfer control device is notified through 3100 that the data has been received, and the write timing chart is started. . At the timing T0, the transfer control circuit 3002 outputs an address to the address bus 231, asserts the WE signal 234, and the transfer circuit 3001 outputs 0 to the content update bit bus, and outputs 0 to the content update bit bus. The data is written to the address designated by the address bus 231. At timing T1, the transfer control circuit 3002 negates the WE signal 2342, and the write operation is completed.

FIG. 15 shows a controller 1100 in which the CPU 501 serves as both the calculation device 101 and the control data transfer device 301 in FIG. 1 as another embodiment. The CPU 501 and the memory controller 401 are connected by an address bus 451, a data bus 452, a memory control signal 453, and a content update bit bus 251, and the memory controller 401 and the control memory 201 are connected to an address bus 261, a data bus 262, and a memory control signal 263. It is connected to the content update bit bus 251. The configurations of the control memory 201 and the memory controller 401 are the same as in FIG. 3, and the address bus 451, data bus 452, and memory control signal 453 correspond to the address bus 141, data bus 142, and memory control signal 453 in FIG. The bus 261, data bus 262, memory control signal 263, and content update bit bus 251 correspond to the address bus 241, data bus 242, memory control signal 244, and content update bit bus 243 in FIG. Since the CPU 501 also serves as the processing of the calculation device 101 and the control data transfer device 301 in FIG. 1, as shown in FIG. 16, the control program execution that the CPU 501 in the address space of the CPU 501 accesses the memory space 6000 of the control memory 201 is executed. The area 6001 and the CPU 501 map to the data transfer area 6002 that is accessed when data is transferred to the controlled device 2000. The sequencer 4001 decodes the address input 241 to determine whether the access from the CPU 501 is an access to the area 6001 or the area 6002. If the access to the area 6001 is 0, the content update determination is 0. By outputting the control signal 4142 to the device 4002, the content update determination device 4002 outputs 1 as the content update bit when accessing the region 6001 and 0 as the content update bit when accessing the region 6002. As a result, the CPU 501 can perform an operation equivalent to the calculation device 101 and the control data transfer device 301 of FIG.

The time chart when the CPU 501 accesses the control memory 201 via the memory controller 401 is the same as the timing chart of the operation when accessing the area 6001 accessed when the control program is executed. 12, the address buses 141 and 241 are the address buses 451 and 261, the data buses 142 and 242 are the data buses 452 and 262, the memory control signals 143 and 244 are the memory control signals 453 and 263, and the content update bit bus 243 is the content. This corresponds to the update bit bus 251. The timing chart of the operation when accessing the area 6002 to be accessed at the time of data transfer is the same as 3 and 14 shown in FIG. 17 at the time of reading and FIG. 18 at the time of writing. Similarly, the address bus 231 is an address bus. . Although the operation itself is the same as that of the control data transfer apparatus 301, the operation is complicated because the memory controller 401 is used.

FIG. 17 shows a time chart when the CPU 501 reads transfer data from the control memory 201. At timing T0, the CPU 501 outputs an address to the address bus 451, write data to the data bus 452, and asserts an RD signal 4531. At the timing of T1, the sequencer 4001 sends a latch signal to the latch 4011 at the beginning of T1, causes the latch 4011 to latch the value of the address bus 451, and asserts the WAIT signal 1434 and the OE signal 2441. To the control memory 201, an address is output to the address bus 261, and an OE signal 2631 is output to the memory control signal 244. The control memory 201 updates the contents of the address specified by the address bus 261 to the data bus 262, and the contents update bit information updates the contents. The data is output to the bit bus 251.

  At the timing of T2, the sequencer 4001 sends a latch signal to the latches 4021 and 4022 at the beginning of T2, causes the latch 4021 to latch the value of the data bus 262, causes the latch 4022 to latch the value of the content update bit bus 251 and negates the OE signal 2631. To do. At the timing of T3, the sequencer 4001 sends a selection signal for causing the selector 4201 to select the output 4111 of the bit merge 4202, a signal for causing the bit merge 4202 to pass the value 4121 to the output 4111, and an enable signal for 4301 and 4303 for the three-state buffer. 1 is output to the output setting signal 4142 to the content update determination device 4002, the WE signal 2631 is asserted, and the WAIT signal 4534 is negated. As a result, an address is output to the address bus 261, data latched to the data bus 262 is latched to the latch 4021, 0 is output to the content update bit bus 251, and a WE signal is output to the memory control signal 263. The control memory 201 is designated by the address bus 261. The contents of the data bus 262 and the content update bit bus 251 are written to the address thus set. At the timing of T4, the sequencer 4001 negates the WAIT signal 4534 and the WE signal 2632, stops the enable signals of the three-state buffers 4301 and 4303, and stops the data output to the data bus 262 and the content update bit bus 251. At timing T5, the CPU 501 confirms that the WAIT signal 4534 has been negated, stops outputting to the address bus 451 and the data bus 452, and negates the RD signal 4533. The above is the operation of the memory controller 401 when reading transfer data.

  FIG. 18 shows a time chart when the data transferred from the controlled device 2000 is written in the control memory 201. At the timing of T0, the CPU 501 outputs an address to the address bus 451, writes data to the data bus 452, and asserts a WR signal 4532. At the timing of T1, the sequencer 4001 sends a latch signal to the latches 4011 and 4012 at the beginning of T1, causes the latch 4011 to latch the value of the address bus 451 and the latch 4012 to latch the value of the data bus 452, respectively, and causes the WAIT signal 4534 and WE signal 2632 to be latched. Is output, 1 is output to the output selection signal 4142 to the content update determination device 4002, and an enable signal is sent to the three-state buffers 4301 and 4303. As a result, an address is output to the address bus 261, data is output to the data bus 262, 0 is output to the content update bit bus 251, and a WE signal 2632 is output to the memory control signal 263, and the control memory 201 outputs the data bus to the address specified by the address bus 261. 262 and the contents of the contents update bit bus 251 are written. At the timing of T2, the sequencer 4001 negates the WAIT signal 4534 and the WE signal 2632, stops the enable signals of the three-state buffers 4301 and 4303, and stops the data output to the data bus 262 and the content update bit bus 251. At the timing of T3, the CPU 501 confirms that the WAIT signal 4534 has been negated, stops outputting to the address bus 451 and the data bus 452, and negates the WR signal 4532. The above is the operation of the memory controller 401 at the time of writing.

  Next, an embodiment for the cost problem will be described with reference to FIGS.

  As shown in FIG. 19, the process control device 10000 includes a controller 10001, a process data control device 10002, a memory 10003, a communication processor 10004, an input / output device 10005, a sensor 10006, an ammeter 10007, and a display lamp 10008. The device 10002 is connected to the controller 10001 via an IO data bus 21000, to the memory 10003 via a memory data bus 23000, and to the communication processor 10004 via a communication data bus 24000.

The communication processor 10004 is connected to an input / output device 10005 via a serial line, and the input / output device 10005 is connected to a sensor 10006, an ammeter 10006, and a display lamp 10008. In this process control apparatus, when information is received from the sensor 10006, the current value of the ammeter 10007 is checked, and if it is lower than the reference value, the lamp 10008 is turned on as an OK sign.

  The data movement in the process control device 10000 is as follows.

The controller 10001 reads the data of the sensor 10006 from the memory 10003 via the process data control device 10002, and if the information of the sensor 10006 is 1, reads the data of the ammeter 10007 from the memory 10003 via the process data control device 10002. If the read data of the ammeter 10007 is lower than the reference value, 1 is written to the memory 10003 through the process data control device 10002 as 0 to the lamp 10008 if 1 is high. The controller 10001 executes this series of processing at regular intervals. On the other hand, the communication processor 10004 starts the input / output device at regular intervals, reads the data of the sensor 10006 and the ammeter 10007, writes the data of the sensor 10006 and the ammeter 10007 into the memory 10003 via the process data control device, The data of the lamp 10008 is read from the memory 10003 via the process data control device 10002 and transferred to the PIO device 10005. When the PIO device 10005 is activated by the communication processor, it takes in data from the sensor 10006 and the ammeter 10007, converts the data of the ammeter 10007 into 2-byte digital information using an A / D converter, and the communication processor 10004. Forward to. Further, the data transferred to the lamp 10008 transferred from the communication processor 10004 is fetched. If the data is 1, the lamp is turned on. If the data is 0, the lamp is turned off. The process control device 10000 operates as described above.

  First, access from the controller 10001 will be described. Access from the controller 10001 to the memory 10003 via the process data control device 10002 is performed in units of 2 bytes. As shown in FIG. 20, an access space of the process data control device 10002 is allocated to a part of the IO address space of the controller 10001, and the controller 10001 accesses the memory 10003 through this IO space. The IO space includes an address pointer upper byte 12001 that constitutes a 2-byte address pointer in the process data control device 10002, an address pointer lower byte 12002, an upper byte write buffer 12002 used by the controller 10001 during write access to the memory 10003, and a memory write. The buffer 10003 is composed of a high-order byte read buffer 12005 and a memory read buffer 12006 that the controller 10001 uses at the time of read access to the memory 10003. The controller 10001 accesses the space consisting of 6 bytes of these 12001 to 12006 and accesses the memory 10003. Access.

FIG. 21 shows how the controller 10001 accesses the memory 10003. In order for the controller 10001 to perform write access to the memory 10003, the controller 10001 writes the upper byte of the address to be accessed on the memory 10003 to the address pointer upper byte 12001 and the lower byte to the address pointer lower byte 12002 (13001). Next, the controller 10001 writes the upper byte of the 2-byte data to be written to the address set in 13001 in the upper byte write buffer 12003 (13003). Similarly, by writing the lower byte of the 2-byte data to be written into the memory write buffer 12004 (13003), the process data control device 10002 has the address indicated by the address pointer consisting of the address pointer upper byte 12001 and the address pointer lower byte 12002. To memory write buffer 2004
The value of the upper byte write buffer 12003 is continuously written in the memory 10003 at the next address indicated by the address pointer.

When the controller 10001 reads data from the memory 10003, the controller 10001 sets the address of the data to be read from the memory 10003 in the address pointer upper byte 12001 and lower byte 12002 (13011). Unlike the previous writing, the controller 10001 first reads the memory read buffer 12006. Then, the process data control device 10002 sends the address value indicated by the address pointer consisting of the address pointer upper byte 12001 and the lower byte 12002 from the memory 10003 to the memory read buffer 12006 with the address indicated by the address pointer. The next address value is continuously read into the upper byte read buffer 12005 (13012). Therefore, when the controller 10001 reads the memory read buffer 12006, the controller 10001 can read the value of the address on the memory 10003 indicated by the address pointer. Next, the controller 10001 reads the upper byte read buffer 12005, reads the upper byte, and the read access ends (13013). As described above, the process data control apparatus 10002 accesses the memory 10003 in units of 2 bytes for access from the controller 10001, thereby ensuring the simultaneity of 2-byte data. In addition, the process pointer is incremented every time the process data control device 10002 accesses 1-byte data to the memory 10003 by accessing the read / write buffer 12003 to 12006 from the controller 10001, thereby providing an auto-increment function. Once the controller 10001 sets an address in the address pointer, the controller 10001 simply accesses the read / write buffers 12003 to 12006, and the controller 10001 continues the memory 10003 without setting new addresses in the address pointers 12001 and 12002. You can access the address.

On the other hand, the access from the communication processor 10004 to the memory 10003 is different from the access from the controller 10001, and the entire memory space of the memory 10003 can be specified by the address output from the communication processor, and the communication data bus 24000 is 2 bytes. An address output from the communication processor 10004 to the memory 10003 is an even address (the least significant bit of the address is 0). Next, a method for accessing the memory 10003 from the communication processor 10004 will be described.

  During a write access from the communication processor 10004 to the memory 10003, the communication processor 10004 outputs an address to the memory 10003 and 2-byte write data to the communication data bus 24000 to the process data control device 10002. Since the memory data bus 23000 has a 1-byte bus width for write access to the memory 10003, the process data control device 10002 first sends the lower byte of the communication data bus 24000 consisting of 2 bytes from the communication processor 10004 to the memory 10003. Write to the specified address (even address), then perform two consecutive write accesses to write the upper byte of the communication data bus 24000 to the next address (odd address: the least significant bit of the address is 1), The process data control apparatus 10002 ends the write access from the communication processor 10004 to the memory 10003.

  Next, at the time of read access to the memory 10003 from the communication processor 10004, the address to the memory 10003 is output to the communication processor 10004 and the process data control device 10002 in the same manner as at the time of writing. Since the memory data bus 24000 is a 1-byte bus, the process data control device 10002 reads the contents of the memory 10003 indicated by the address (even address) designated from the communication processor 10004, and uses this as the lower byte to continue to the next address Is read out from the memory 10003 (odd address: the least significant bit of the address is 1), and this is used as the upper byte, and is output to the communication processor 10004 as two-byte data in total, thereby performing a process twice. The data control device 10002 ends the read access from the communication processor 10004 to the memory 10003.

  As described above, access from the communication processor 10004 to the memory 10003 is performed. Further, since the controller 10001 and the communication processor 10004 operate asynchronously in the process data control device 10002, when an access request is simultaneously generated from the controller 10001 and the communication processor 10004 to the process data control device 10002 (access contention to the memory 10003). ) Exists. As a method of resolving this conflict, the process control device 10000 does not solve the conflict by software such as test and set, but has a conflict resolution circuit in the process data control device 10002 to quickly resolve the conflict by hardware and to access the memory by the conflict. The overhead of time is reduced. By this conflict resolution, access exclusiveness to the memory 10003 is realized in 2-byte access units, and simultaneity of 2-byte data is guaranteed.

FIG. 22 shows the configuration of the process data control apparatus 10002. The process data control device 10002 is the controller 10001, the IO data bus 21000 and the IO address bus, the communication processor 10004 is the communication data bus 24000 and the communication address bus, and the memory 10003 is the memory data bus 23000 and the memory address bus. The IO data bus 21000, the communication data bus 24000, and the memory data bus 23000 are bidirectional buses of 1 byte width, 2 byte width, and 1 byte width, respectively. All address buses are 2 bytes wide. This process data control device 10002 has an IO decoder 10021 that decodes an IO address output from the controller 10001, a 2-byte simultaneous guarantee circuit 10023 that controls data at the time of access from the controller 10001, and guarantees 2-byte simultaneous guarantee, and an access from the controller 10001. Sometimes the address pointer 10024 for holding the address to the memory, the memory sequencer 10025 for controlling the data at the time of access from the communication processor, the output data from the 2-byte simultaneous guarantee circuit 10025, and the output data from the memory sequencer 10025 are selected and the memory data is selected. Select the selector 10027 to be output to the bus 23000, the address output from the address pointer 10024 and the address output from the communication processor 10004, and A selector 10026 for outputting to the bus, a 3-state buffer 11001 for controlling the output from the 2-byte simultaneous guarantee circuit to the IO data bus 21000, a 3-state buffer 11003 for controlling the output from the memory sequencer 10025 to the communication data bus 24000, and a selector 10027 outputs to memory data bus 23000
It comprises a three-state buffer 11002 that controls the output to and a control device 100022 that controls them.

The IO decoder 10021 decodes the IO address when accessing the process data control device 10002 from the controller 10001, and determines whether the access is to the address pointer 10024 or the memory 10003 if the access is to the process data control device 10002. To do. When the access from the controller 10001 is an access to the address pointer 10024, a data set signal for the upper or lower byte of the address pointer is output to the address pointer 10024. In the case of memory access (access to the memory write buffer 12004 and memory read buffer 12006), an access request is output to the control circuit 10022. The control circuit 10022 has a contention determination circuit 10221 inside, and determines whether contention in access to the memory 10003 occurs. If a conflict with the memory 10003 occurs, the memory sequencer 10025 waits until the access to the memory 10003 is completed, and if the conflict does not occur, an access permission is given to the 2-byte simultaneous guarantee circuit 10027, and the selector 10026 causes the output of the address pointer 10024 to be selected. Further, when the access from the controller 10001 is a read access, a read request is continuously output twice to the memory 10003 and the three-state buffer 11001 to the IO data bus 21000 is set in an output state. If the access from the controller 10001 is a write access, a write request is output twice in succession to the memory 10003 and the selector 10027 is made to select the output of the 2-byte simultaneous control circuit, so that 3 is sent to the memory data bus 23000. The status buffer 11002 is driven. The 2-byte simultaneous guarantee circuit 10025 obtains access permission from the control circuit 10022 and starts accessing the memory 10003.

  Further, when accessing from the communication processor 10004, the memory sequencer 10025 outputs an access request to the control circuit 10022, and the contention determination circuit 10221 of the control circuit 10022 determines whether or not an access contention to the memory 10003 occurs. If this occurs, the 2-byte simultaneous guarantee circuit 10023 will wait until the access to the memory 10003 is completed. If there is no access contention to the memory 10003, the control circuit 10022 gives access permission to the memory sequencer 10025 and The control unit 10002 selects the address output of the communication processor 10004. Further, when the access from the communication processor 10004 is a read access, a read request is output twice in succession to the memory 10003 and the three-state buffer 11003 to the communication data bus 24000 is driven. If the access from the communication processor 10004 is a write access, a continuous write request is output twice to the memory 10003 and the selector 10027 is made to select the output of the memory sequencer 10025 to provide a three-state buffer to the memory data bus 23000. Drive 11002.

FIG. 23 shows the configuration of the 2-byte simultaneous guarantee circuit 10027. The 2-byte simultaneous guarantee circuit 10027 includes a simultaneous guarantee control circuit 10231, a latch 10232 for holding upper byte data when writing to the memory 10003, a selector 10235 for selecting write data to the memory 10003, and an upper byte when reading to the memory 10003. A latch 10233 for holding data, a latch 10234 for holding lower bytes, and a selector 10236 for selecting read data to the controller 10001 are configured. The 2-byte simultaneous guarantee circuit 100023 is activated upon receiving an access permission from the control circuit 10022, and from the IO decoder 10021 to any of the upper byte write buffer 12003, the memory write buffer 12004, the upper byte read buffer 12005, and the memory read buffer 12006. Receive access. The operation of the simultaneous guarantee control circuit 10231 is as follows. In the case of access to the upper byte write buffer 12003, the simultaneous guarantee control circuit 10231 outputs a latch signal to the latch 10232 and causes the latch 10232 to latch the data on the IO data bus 21000. In the case of access to the upper byte read buffer 12005, the simultaneous guarantee control circuit 10231 causes the selector 10236 to select the output of the latch 10234 and causes the IO data bus 21000 to output the upper byte data held in the latch 10234. At the time of accessing the memory write buffer 12004, the simultaneous guarantee control circuit 10231 outputs a write request to the memory 10003 to the control circuit 10022 and waits for access permission from the control circuit 10022. When access permission is received from the control circuit 10022, the selector 10235 causes the IO data bus 21000 to be selected, the write data to the memory write buffer 12004 is written to the memory 10003, and then the simultaneous guarantee control circuit 10231 causes the selector 10235 to latch 10232. By selecting, the value of the upper byte read buffer is output to the memory 10003, and the data of the latch 10232 is written, whereby the 2-byte data is continuously written to the memory 10003.

  When accessing the memory read buffer 12006, a read request to the memory 10003 is output to the control circuit 10022 in the same manner, and waiting for access permission from the control circuit 10022. When the simultaneous guarantee control circuit 10231 receives an access permission from the control circuit 10022, a read request is output continuously twice from the control device 10022. Therefore, the simultaneous guarantee control circuit 10231 outputs a latch signal to the latch 10233 and outputs the first read. Data (lower byte data) is held in the latch 10233, and subsequently, a latch signal is output to the latch 10234, and the read data (upper byte) from the memory 10003 is held in 10234. Further, the simultaneous guarantee circuit 10231 selects the selector 10235 to output to the latch 10233 and outputs the lower byte data to the IO data bus 21000.

  FIG. 24 shows an outline of the address pointer 10024. The address pointer 10024 includes a latch 10241 for holding an upper byte of an address to be output to the memory 10003 and a latch 10242 for holding a lower byte, a 16-bit (2 bytes) incrementer 10243 for performing auto-increment to the memory 10003, a selector 10244, The selectors 10244 and 10245 select whether the input data to the latches 10241 and 10242 is the output of the IO data bus 21000 or the 16-bit incrementer 10243, respectively. The selectors 10244 and 10245 normally select the output of the 16-bit incrementer 10243, but when the controller 10001 accesses the address pointer, both the selectors 10244 and 10245 select the IO data bus 21000 side. When the controller 10001 accesses the address pointer upper byte 12001, a latch signal is output from the IO decoder 10021 to the latch 10241, the value of the IO data bus 21000 is output to the latch 10241, and when the controller 10001 accesses the address pointer lower byte 12002, the IO decoder A latch signal is output from 10021 to the latch 10242, and the value of the IO data bus 21000 is written to the latch 10242. When the controller 10001 accesses the memory write buffer 12004 and the memory read buffer 12006, a read / write request signal is output from the control circuit 10022 to the memory 10003, and a latch signal is output to the latches 10241 and 10242. The value of the address pointer is incremented for each access, and the address pointer is incremented by one at the time of two consecutive accesses, so that memory access can be performed correctly.

FIG. 25 shows an outline of the memory sequencer 10025. The memory sequencer 10025 selects the upper byte and the lower byte of the write data of the communication data bus 24000 having a width of 2 bytes when the communication processor 10004 writes, and outputs the higher byte to the memory data bus 23000 and the upper byte when the communication processor 10004 reads. It comprises a latch 10253 for holding, a latch 10254 for holding the lower byte, and a memory sequencer control circuit 10251 for controlling them. At the time of writing from the communication processor 10004, the memory sequencer control circuit 10251 outputs a write request signal to the control circuit 10022 and waits for access permission from the control circuit 10022. When access permission is received from the control circuit 10022, the memory sequencer causes the selector 10254 to respond to two consecutive write access requests to the memory 10003 output from the control circuit 10022. Data on the communication data bus 24000 is written to consecutive addresses in the memory 10003 by selecting the upper byte at the time of write access and outputting 0 at the first write access and 1 at the next write access. . When the communication processor 10004 reads from the memory 10003, it outputs a write request signal to the control circuit 10022 and waits for access permission from the control circuit 10022. The control circuit 10022 gives access permission to the memory sequencer control circuit 10251 and outputs read access requests to the memory 10003 twice in succession. When the memory sequencer 10251 receives access permission from the control circuit 10028, the latch 10253, the latch 10253 holds the read data from the first memory 10003 in the latch 10253, and the next read data in the latch 10254.
A latch signal is output to 10254, and the latch 10253,
2-byte data is output consisting of 10254 outputs. As described above, 2-byte simultaneous guarantee is realized for memory access from the communication processor 10004.

  FIG. 26 shows a time chart when the controller 10001 accesses the memory 10003, and FIG. 27 shows a time chart when the communication processor 10004 accesses the memory 10003.

  As described above, the process data control apparatus 10002 operates to guarantee the 2-byte data simultaneity to the controller 10001.

The schematic diagram of the example 1 of application of the data transfer system which is this invention. The schematic diagram of the control system using a programmable controller. FIG. 2 is a detailed diagram of the memory controller of FIG. 1. FIG. 4 is a detailed control memory of the content update determination device of FIG. 3. The truth table of the comparison circuit of FIG. The figure which shows the access unit of control memory. FIG. 5 is a schematic diagram of the sequencer in FIG. 4. The figure which shows the data format at the time of read modify write. FIG. 2 is a schematic diagram of the transfer device in FIG. 1. The operation | movement timing chart figure of the memory controller at the time of reading. The operation | movement timing chart figure of the memory controller at the time of writing. The operation | movement timing chart figure of the memory controller at the time of read modify write. FIG. 4 is a timing chart of an operation for reading data into a control memory of a transfer device. 6 is a timing chart of the write operation to the control memory of the transfer apparatus. The schematic diagram of the example 2 of application of the data transfer system of this invention. The memory map of CPU501 of FIG. The operation | movement timing chart of the memory controller 401 at the time of the data transmission of CPU501 of FIG. FIG. 16 is an operation timing chart of the memory controller 401 when the CPU 501 in FIG. 15 receives data. FIG. 1 is a schematic diagram of a process control device. The IO address mapping visible from the controller of FIG. Memory access procedure from the controller of FIG. 19 via the process control device. FIG. 20 is a schematic diagram of the process data control device of FIG. 19. FIG. 23 is a schematic diagram of the 2-byte simultaneous guarantee circuit of FIG. 22. FIG. 23 is a schematic diagram of the address pointer of FIG. 22. FIG. 23 is a schematic diagram of the memory sequencer of FIG. 22. FIG. 20 is a time chart of memory access from the controller of FIG. 19. FIG. FIG. 20 is a time chart of memory access from the communication processor of FIG. 19. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Computer, 141, 231, 241, 261, 451 ... Address bus, 142, 232, 242, 262, 452 ... Data bus, 143, 234, 244, 263
453 ... Memory control signal, 201 ... Control memory, 233,243,251 ... Content update bit bus, 301 ... Control data transfer device, 401 ... Memory controller, 501 ... CPU, 1000 ... Control device, 1200 ... Network, 2000 ... Control device, 2001 ... Input / output device, 2101 ... Sensor, 2102 ... Actuator, 3000 ... Device, 4001 ... Sequencer, 4002 ... Content update determination device, 4011, 4012, 4022 ... Latch, 4201 ... Selector, 4202 ... Bit merge, 4301 , 4302, 4303... Three-state buffer, 5001... Comparison circuit, 5002.

Claims (2)

At least memory that stores process status and control data,
A controller that generates control data based on the process information stored in the memory;
A processor for performing an operation for storing process information in the memory and for performing an operation for reading control data stored in the memory;
The memory is connected to the controller and the processor, the access data of the access data and the processor of the controller is configured to be stored in the same time has a register for holding a plurality of bit data from the controller and processor For the read access, the data for the read access is continuously increased by dividing the number of times required by the data size of the read access against the restriction on the size of the bus connected to the memory. serial and read out from the memory, data read is divided into upper Symbol plurality is stored in the register so as to identify whether the data from the data or the processor from the controller, to a continuous register is divided into the plurality In parallel with the storage of at least a part of it in time. Process control device, characterized in that it comprises a data control unit for transferring the data stored in the data data to those who received the access of the controller and the processor. At least memory that stores process status and control data,
A controller that generates control data based on the process information stored in the memory;
A processor for performing an operation for storing process information in the memory and for performing an operation for reading control data stored in the memory;
Connected to the memory , the controller, and the processor, and configured to store the access data of the controller and the access data of the processor at the same time, and has a register that holds a plurality of bit data, and is connected to the memory The write access target is divided into the number of transfers to the memory required for the write access data size for the write access from the controller or processor having a data size exceeding the bus size constraint. The write data is stored in the register, and the stored write data is stored so that it can be identified whether the data is from the controller or the processor, and is divided for transfer to the memory. All of the write data After being stored in the static process control device, characterized in that it comprises a data control unit for writing the write data stored in the register, in the memory in sequence in units divided.

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