JPH10269134A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of data transfer between a controlling unit and a controlled device, by reading data rewritten by a memory controller so as to modify control contents, out of a memory and sending it. SOLUTION: State data showing the state of a controlled system and control data for controlling the controlled system are stored in a control memory 201 and a computer device 101 computes control data on the controlled system according to the stored state data. The state stored in the control memory 201 is read out by a memory controller 401, the computed data is written in the read state data, and the resulting data is stored in the control memory 201. Then the data which is thus rewritten by the memory controller 401 is read out of the control memory 201, outputted to a network 1200 by a data transfer device 301, and sent to the controlled device. Consequently, the data transfer between the control unit 1000 and controlled device can be made efficient.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, such as a programmable controller, which requires data transfer at regular intervals between a control device and a controlled device to be controlled.

[0002]

2. Description of the Related Art Conventionally, a programmable controller for controlling various devices constituting an industrial facility has been configured to receive information from a sensor for reporting the status of each device and to give instructions to actuators of each device to thereby control the industrial facility. Controlling. For the purpose of facilitating the creation of a control program to be executed on the programmable controller, a memory called a control memory is placed in the programmable controller, and each bit on the control memory stores sensor information and actuator information of each device to be controlled. Map information. The programmable controller communicates with each device periodically via a network, and sensor information is transferred from the device to the programmable controller, and actuator information is transferred from the programmable controller to the device. The contents of the memory are matched with the states of the sensor information and actuator information of the device. By providing the programmable controller with a control memory having such characteristics, the control program can control each device only by accessing the control memory.

However, in recent years, as the number of devices to be controlled by a programmable controller has increased with the increase in size and performance of industrial equipment, the number of sensors and actuators in each device has also increased. As a result, the amount of data transferred through the network between the programmable controller and each device is increased, and the processing of the control program is also increased. The time before it was longer. In order to shorten the control cycle, it is necessary to shorten the data transfer time between the programmable controller and each device in addition to the time required to execute the control program.

There are two methods for reducing the data transfer time: a method using a high-speed network and a method for improving the efficiency of data transfer.

In a method using a high-speed network, data transfer between the programmable controller and each device is performed at a high speed, so that the data transfer time can be reduced. In order to improve the efficiency of data transfer, there is a method of dividing the control memory into two parts, a sensor area for storing sensor information and an actuator area for storing actuator information. If sensor information and actuator information are mixed on the control memory, a table indicating whether data at each address of the control memory is sensor information or actuator information is required in the programmable controller. in this case,
Since the table must be checked during transfer between the program controller and each device, extra overhead is required. When the device determines whether the information sent from the programmable controller is sensor information or actuator information, the programmable controller must also transfer the sensor information, which is unnecessary data, to the device. Therefore, the amount of data transfer increases and the transfer time increases. Similarly, the same can be said for the sensor information. However, by dividing the area of the control memory, the overhead of determining whether the information is sensor information or actuator information and unnecessary data transfer between the programmable controller and each device can be omitted. , The data transfer time can be reduced.

[0006]

As described above, in order to shorten the data transfer time, there are a method using a high-speed network and a method for improving the transfer efficiency by eliminating unnecessary overhead and data transfer. is there.

In the former method using a high-speed network, the high-speed network itself is expensive, and a memory having a high access time must be used as a control memory in order to realize a high transfer rate. Would be expensive.

Next, in the method of increasing the efficiency of data transfer, the control memory is divided into a sensor area and an actuator area so that sensor information and actuator information belonging to the same device are arranged as a group at continuous addresses on the control memory. Information cannot be managed on a device-by-device basis, and when controlling a large number of devices, the user interface deteriorates, creating a control program and confirming the operation of the control program on the programmable controller. It becomes difficult to do.

Another problem is cost. As the number of devices to be controlled increases, the number of sensors and actuators increases, and the capacity of the control memory increases. When the controlled circuit is controlled not by digital but by analog, the analog signal is converted to a 12-bit or 16-bit signal by using an A / D (analog / digital) converter.
Convert to a digital signal of bits. However, when the data bus of the control memory is 8 bits, the access to the analog data composed of 16 bits is twice per byte. If an access from the communication processor enters between the first access and the second access from the controller, and the upper 8 bits and lower 8 bits of the analog data impair the data synchronization, the control is performed correctly. There is no problem. Therefore, the data bus of the control memory often uses a 16-bit bus in accordance with it. As described above, the number of pins of the LSI and the memory constituting the controller increases, and therefore, a large LSI package is required, resulting in a problem that the cost is increased.

In view of the above problems, it is an object of the present invention to provide a control system in which the data transfer efficiency between a control device and a controlled device is improved at low cost.

[0011]

In order to achieve the above object, the present invention provides a memory for storing at least state data representing the state of a control target and control data for controlling the control target, and a memory for storing the control data for controlling the control target. A computer for obtaining control data of a control target based on the read state data, a memory controller for reading state data stored in the memory, writing data obtained by the computer in the read state data, and storing the data in the memory, A data transfer device for reading data rewritten by the memory controller to change the contents from the memory and transmitting the data.

[0012] To achieve the above object, the present invention provides:
A memory for storing at least data representing the state of the control target and data for controlling the control target, a computer for obtaining control data of the control target based on the data representing the state of the control target stored in the memory, and a memory Reads one-word data consisting of a plurality of bits from the data stored in the memory, transfers the data to be controlled to the computer, and stores the data for control obtained by the computer in the read one-word data in the write memory. A control device having a memory controller, a data transfer device that reads data rewritten by the memory controller from the memory and transmits the read data, a plurality of control targets, a plurality of sensors for measuring a state of the control target, and a control target. Multiple actuators for control and the state of the controlled object measured by multiple sensors Data representative sent, and having a controlled device having an input and output device for transferring a plurality of actuators data for control sent from the control device.

According to another aspect of the present invention, there is provided a memory for storing at least a process state and control data, a controller for generating control data based on process information stored in the memory, a memory and a controller. A first data and a first data to be read-accessed in response to a read access from the controller;
And a data controller for reading out second data following the data from the memory, transferring the first data to the controller, and holding the second data in the register.

According to the present invention, there is provided a memory for storing at least a process state and control data, a controller for generating control data based on process information stored in the memory, and a connection between the memory and the controller. And a register for holding a plurality of bit data. In response to a first write access from the controller, the first data to be subjected to the first write access is held in the register. 2
A data control device that continuously stores the second data to be subjected to the second write access and the first data held in the register in the memory for the write access. .

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
7 will be described.

FIG. 2 shows a control system using a programmable controller. The control system includes a control device 1000, a controlled device 2000, a control device
A network 120 is provided between the network 1000 and the controlled device 2000.
0. The control device 1000 includes a computing device 101, a control memory 201, a control data transfer device 301, and a memory controller 401 having a content update determination device 4002 therein. The controlled device 2
000 comprises an input / output device 2001, a sensor 2101, an actuator 2102, and a device 3000.

Next, the control device 1000 and the controlled device 20
The flow of data between 00 and 00 will be described.

Information flowing between the control device 1000 and the controlled device 2000 is based on sensor information from one or more sensors 2101 attached to the device 3000 and the device 3000.
Is the actuator information to one or more actuators 2102 that control the operation of. Also, the control device 1000
The sensor information from the sensor 2101 and the actuator information to the actuator 2102 are assigned to each address of the control memory 201 within the control memory 201. When the control program executed by the control device 1000 needs information from a specific sensor, The sensor information is obtained by reading the address where the sensor information is held. When it is desired to control a particular actuator, the actuator is similarly controlled by writing the actuator information to an address of the control memory 201 where the actuator information is held. In addition, the sensor information has a bit length that varies depending on the type of sensor, and may have a bit length of one bit or several bits. Since the data length is various, the sensor information is input and output by the input / output device 2001. Bytes (8
The data is collected into access units such as bits (bits) and words (16 bits), and sent to the control device 1000 via the network 1200 for each access unit. The control device 1000 writes the sensor information collected in the access unit sent from the controlled device 2000 to a corresponding address of the control memory 201. As for the actuator information, a plurality of pieces of actuator information are grouped into access units in the same manner as the sensor information, and written into the assigned addresses of the control memory. Thereafter, the actuator information is stored in the controlled device 20 for each access unit via the network 1200.
The data is transferred to the actuator 2102 by dividing the data of a plurality of pieces of actuator information, which are transferred to the input / output device 2001 and compiled in access units by the input / output device 2001, for each actuator. Then, the actuator 2102 transmits the data to the device 300 based on the data transferred from the input / output device 2001.
The operation is performed for 0. As described above, the control device 1
000 can control the device 3000 of the controlled device 2000.

Here, the operation of the entire control system in FIG. 2 will be described using motor control as an example of the controlled device 2000. The motor of the controlled device 2000 is
00, a sensor 2101 for checking the number of rotations of the motor, and a current control device for controlling a current supplied to the motor are referred to as an actuator 2102.

The control program executed by the calculation device 101 in the control device 1000 reads the number of rotations of the motor by the sensor 2101 and compares it with a specified value. It instructs to decrease the rotation speed, and if it is lower, instructs the actuator 2102 to increase the current supplied to the motor to increase the rotation speed of the motor. By controlling the current supplied to the motor in this way, the rotation speed of the motor is controlled to a specified value.

For the access unit, the computer 101
Is the number of bits that can be read from the control memory 201 at one time, and here is 16 bits.

This motor control program is given by a ladder diagram. The data flow in FIG. 2 is as follows. The sensor 2101 measures the number of rotations of the motor and outputs the measured value to the input / output device 2001 as an analog value. The input / output device 2001 converts the data into 16-bit digital data via an A / D (analog / digital) converter. The converted data on the number of rotations of the motor is sent to the control device 1000 via the network 1200. In the control device 1000, the actuator 2
Calculate actuator information for 102. The motor rotation speed data digitized by the control data transfer device 301 is received and written into the address a of the control memory 201. The computing device 101 reads the address a in the control memory 201 and obtains information on the number of rotations of the motor. Next, the specified value is compared with the information on the number of revolutions of the motor, and it is determined whether the number of revolutions of the motor is higher or lower than the specified value. Write 2-bit data to the memory 201. If the rotation speed of the motor is higher than a specified value, 10 is used to reduce the supply current to the motor, and if the rotation speed is lower, 2 is used to increase the supply current to the motor.
01 is written in the bit information, and 00 is written to the address b of the control memory 201 if the number of rotations of the motor is the same as the specified value. The actuator information for the actuator 2102 written at the address b is read by the control data transfer device 301, and is controlled via the network 1200 by the controlled device 2000.
Send to In the controlled device 2000, the input / output device 20
01 receives the actuator information sent by the control data transfer device 301, and transfers the received actuator information to the actuator 2102. The actuator 2102 decreases the current supplied to the motor if the actuator information transferred from the input / output device 2001 is 01, and increases the current supplied to the motor if the actuator information is 10. By doing so, the number of rotations of the motor can be maintained at the specified value.

Next, the computing device 101 and the control memory 201
Will be described. As shown in FIG. 1, the computing device 101 is connected to a control memory 201 via a memory controller 401. FIG. 3 shows the internal structure of the memory controller 401. There are three methods for accessing the control memory 201 from the computing device 101 via the memory controller 401: read, write, and read-modify-write. Read access is access for reading data from the control memory 201, write access is data write access to the control memory 201,
The read-modify-write access is performed in the control memory 201.
This access is for rewriting only the upper one bit. The actuator information for the actuator 2102 described above is 2
Is a bit. Therefore, if actuator information for another actuator is assigned to another bit of the same address b, the actuator 210 is simply assigned to the address b.
When the actuator information is written in the second actuator information, the other actuator information is also rewritten together. Therefore, the address b including the data of the actuator 2102 is once read from the control memory 201 (read),
Only the data portion to the actuator 2102 is rewritten (modify), and the rewritten data is written back to the address b of the control memory 201 (write), whereby only the control data to the actuator 2102 can be rewritten. . Further, the memory controller 401 compares the data read from the control memory 201 with the data to be written at the time of the read-modify-write access to determine whether the data content has been updated by the read-modify-write access. Has a judgment function. With this content update determination function, only data whose data content has been updated can be transferred to the controlled device 2000 at the time of data transfer in the control data transfer device 301, so that transmission data can be reduced and data transmission time can be reduced. Can be shortened.

Next, the structure of the memory controller 401 will be described. The memory controller 401 has a latch 4
011, 4012, 4021, 4022, and selectors 4201, 2 and 1 output for selecting one of two inputs. One input is input unit bit width, and the other input is 1 bit input. A bit merge 42 that outputs an access unit that replaces an arbitrary one bit of the access unit with one bit that is the other input.
02, three-state buffers 4301 and 430 for preventing bus fights in which outputs collide because the bus is a bidirectional bus
2,4303, a content update determination device 400 for determining whether the data content at the time of read-modify-write has been updated
It comprises a sequencer 4001 that controls two or more resources and operates as a memory controller.

An address bus 141, which is an address output from the computing device 101, becomes an address bus 241 via a latch 4011 and becomes an address input of the control memory 201.
Similarly, the data input / output bus 142 from the computing device 101 is connected to the selector 4201 and the bit merge 4202 via the sequencer 4001 and the latch 4012, and the output of the selector 4201 is connected to the data bus 242 of the control memory via the three-state buffer 4301. And the data bus 242 is connected to the three-state buffer 43 via the latch 4021.
02, bit merge 4202, content update determination device 400
2 and the output of the tri-state buffer 4302 is connected to the data bus 142. Memory control signal 1
43 is input to the sequencer 4001 and the control memory 20
It is converted into one memory control signal 244. The output to the content update determination bit bus 243, which is a bidirectional bus, is based on the output 4131 of the content update determination device 4002 and the three-state buffer 43.
03, and the input is input to the content update determination device 4002 via the latch 4022. The bit merge 4202 replaces any one bit of the output of the latch 4021 with the lower one bit of the latch 4012 and selects the selector 42.
01 is connected. Control signals, which are outputs of the sequencer 4001, are latches 4011, 4012, 4021, and 402.
Latch timing of 2, 3-state buffers 4301, 43
02, 4303 state (output, high impedance),
Select signal of selector 4201, bit merge 420
2 and a determination enable signal of the content update determination device 4002 are output.

The operation of the memory controller 401 will be described. The memory controller 401 has three types of operations: read / write / read-modify-write.
2. It is started by the memory control signal 143.

The read access is started when the address is read from the computer 101 and the read request is output from the memory control signal 143. Sequencer 4001 has latches 4011 and 40
21, a latch signal, an output signal to the three-state buffer 4302, a high impedance signal to the other three-state buffers 4301 and 4303, and a memory control signal 2 to the control memory 201.
A read signal is output to 44, and an address output from the computing device 101 is output to the address bus 241. In the control memory 201, data of the content of the address specified by the address bus 241 is output to the data bus 242, and the content update bit information is output to the content update bit bus 243. The contents of the data bus 242 are output to the data bus 142 via the latch 4021 and the 3-state buffer 4302, and the read access ends.

Next, write access will be described. Write access is performed from the computing device 101 to the address bus 141.
Then, an address is written to the data bus 142, data is written to the memory control signal 143, and the memory controller 401 is activated. Sequencer 4001 is
A write request is sent to the memory control signal 244, and the latch 4011, 4
012 and the latch signal to the selector 4201.
02, the address bus 241 and the data bus 2
42, an address bus 141 and a data bus 14
2 is output, and the content of the data bus 242 is written to the address specified by the address bus 241. Finally, read-modify-write access will be described. An address is output to the address bus 141 from the computing device 101, data having the format shown in FIG. 4 is output to the data bus 142, and a read-modify-write request is output to the memory control signal 143, and the memory controller 401 is activated. First, the sequencer 4001 has latches 4011 and 40
12, 4021, 4022, a read signal as a memory control signal 244 to the control memory 201, and the contents of the address bus 141 to the address bus 241. The control memory 201 outputs the data at the address designated by the address bus 241 to 242 and the content update bit to the content update bit bus 243, and the data is latched by the latches 4021 and 4022, respectively. Next, sequencer 400
1 sets the memory control signal 244 to the control memory 201 to a write request, sets the three-state buffers 4301 and 4303 to the output state, sets the four-state buffer 4302 to the high impedance state, and makes the selector 4021 select the output side of the bit merge 4022, It causes the merge 4022 to replace the content of the bit address 901 shown in FIG. 8 with the bit data 902, and outputs a determination enable signal to the content update determination device 4002. The content update determination device 4002 compares the output of the latch 4021 that is the read data with the data of the bit merge 4202 that is the write data.
A content update bit to be written to the control memory 201 is calculated in consideration of the value of “22” and output to 4131. The output of the bit merge 4202 is supplied to the selector 4201, the 3-state buffer 4
The data is output to the data bus 242 via the interface 301, and the contents of the data bus 242 and the content update bit bus 243 are written to the address specified by the address bus 241 of the control memory 201. The above is the operation of the memory controller 401. Time charts of the memory controller 401 are shown in FIGS.

FIG. 5 shows an outline of the content update judging device 4002. The content update determination device 4002 controls the control memory 201 at the time of read-modify-write access.
Is compared with the data 4111 to be written to the control memory 201 to detect a change in the data due to the read-modify-write.
1 is output to 131. At this time, the control memory 2
When the content update bit of the data 01 is 1, the OR gate 5 for calculating the logical sum stores the information.
002. The operation of the comparison circuit 5001 is as follows. The comparison circuit 5001 has four inputs.
4111, an input B 4121, a comparison enable signal 4141 which is a control signal from the sequencer 4001, and a signal 4142 for providing an output signal at the time of non-comparison. The output of the comparator 5001 is as shown in FIG. 6. When the comparison enable signal 4141 is 0, the comparator 5001
If 4111 and the input B 4121 match, 1 is output. If they do not match, 0 is output. If the comparison enable signal 4141 is 1, the value of the output signal 4142 at the time of non-comparison is output as it is. Inverted output of comparison circuit 5001 and latch 4
By taking the logical sum with the output of the data 022, the signal indicating whether the content of the data by the read-modify-write has changed can be generated.

FIG. 7 shows an outline of the sequencer 4001.
The sequencer 4001 reads / writes / reads / modifies / writes from the computer 101 (memory control signal 1
43), the address bus 241 and the data bus 142
From each of the latches 4011, 4012, 4021,
Latch timing of 4022, selection signal to selector 4201, bit merge 4202, 3-state buffer 430
1, 4302, 4303, and a comparison timing signal 414 to the content update determination device 4002.
1, an output selection signal 4142, reading into the control memory 201, and generation of write timing signals 2441 and 2442 are performed. The output selection signal 4142 to the content update determination device 4002 is fixed to 0 in the control device 1000 shown in FIG. Calculation device 1 shown in FIG. 15 described later
The output selection signal 4142 is used when the CPU 501 also serves as the control data transfer device 301 and the control data transfer device 301. The memory control signal 143 includes a read request signal 1431 (hereinafter, RD signal), a write request signal 1432 (hereinafter, WR signal), a read modify write signal 1433 (hereinafter, RMW signal), and a wait indicating that memory access has not been completed. RD signal 1431, WR signal 1432, and RMW signal 1433 are input to sequencer 4001 and WAIT signal 1
Reference numeral 434 denotes an output of the sequencer 4001. The memory control signal 244 is an output enable signal 2441 (hereinafter: O)
E signal), write enable signal 2442 (hereinafter: WE
OE signal 2441, WE signal 2442
Both are the outputs of the sequencer 4001. Output signals to the content update determination device are a comparison enable signal 4141 and an output setting signal 4142 when no comparison is made.

FIG. 8 shows a data format 900 output from the computing device 101 to the data bus 142 at the time of RMW. The data format 900 has the least significant bit of 0.
The bit consists of write bit data 902 and 901 indicating the address of the bit to be rewritten in a word. For the data in the control memory 201 specified by the address output from the computing device 101, the memory controller 401 Reading (read), one bit in the data specified by the address 901 in the word is replaced with 1-bit data 902 (modify), and a process of writing back (write) to the same address is performed.

FIG. 9 shows the configuration of the control data transfer device 301. The control data transfer device 301 reads data from the control memory 201 and, if the value of the content update bit bus 233 is 1, transfers the data of the data bus 232 to the network 1
Output to 200. When data is received from the network 1200, the received data is stored in the control memory 2.
Write to 01. A memory control signal 234 including an address bus 231, an output enable signal 2341, and a write enable signal 2342 is an output of the transfer control device 3002, the data bus 232 is connected to the transfer circuit 3001, and the content update bit bus 233 is connected to the transfer circuit 3001 and the latch 3202. The output of the latch 3202 is connected to a tri-state buffer 3201. This three-state buffer 32
01 is inserted on the output side of the latch 3202 because the output from the control memory 201 and the output from the latch 3202 do not collide on the data bus 232 because the data bus 232 is a bidirectional bus. The transfer device 3001 and the transfer control device 3002 are connected by a data line 3100.

The transfer device 3001 includes therein a transfer determination circuit 3
011 and determines whether to output data on the data bus 232 to the network 1200 by looking at the value of the content update bit bus 233. Also, the transfer control device 3002
Is a counter 3 internally pointing to the address of the control memory 201
012, and the contents of the control memory 201 are sequentially output to the network 1200 by this counter.

Next, the flow of data in the control device 1000 will be described. The computing device 101 has an address bus 141,
An access request is output to the memory controller via the data bus 142 and the memory control signal 143, and the control memory 20
Exchange data with 1. Memory controller 401
10 to 12 are timing charts of the operation. 10 is for reading, FIG. 11 is for writing, FIG.
Is a timing chart at the time of read-modify-write. In each of the timing charts, the clock timing at which the computing device 101 starts accessing is T0.

FIG. 10 shows a time chart at the time of reading. At the timing of T0, the computing device 101 outputs an address to the address bus 141 and asserts the RD signal 1431. At timing T1, the sequencer 4001 sends a latch signal to the latch 4011 at the beginning of T1, causes the latch 4011 to latch the value of the address bus 141, and
The IT signal 1434 and the OE signal 2441 are asserted.
Address to the control memory 201, address to the address bus 241
An OE signal 2441 is output as the memory control signal 244,
The control memory 201 outputs the contents of the address specified by the address bus 241 to the data bus 242. At the timing of T2, the sequencer 4001 sends a latch signal to the latch 4021 at the beginning of T2 to latch the value of the data bus 242, and the WAIT signal 1434 and the OE signal 2441.
, And sends an enable signal to the three-state buffer 4302 to read the data of the output 4121 of the latch 4021 into the data bus 142 and output the data. At the timing of T3, the computing device 101 sends the WAIT signal 1434
Is confirmed, the output to the address bus 141 is stopped, the RD signal 1431 is negated, and the contents of the data bus 142 are fetched. The sequencer 4001 stops the enable signal of the three-state buffer 4302 and stops outputting data to the data bus 142. The above is the operation of the memory controller 401 at the time of reading.

FIG. 11 shows a time chart at the time of writing. At timing T0, the computing device 101 writes an address on the address bus 141 and outputs data on the data bus 242, and asserts the WR signal 1432. At timing T1, the sequencer 4001 sends a latch signal to the latches 4011 and 4012 at the beginning of T1, and
1 and the value of the data bus 142 are latched by the latch 4012 and the value of the data bus 142, respectively.
434, the WE signal 2442 is asserted, and the selector 42
01 and an enable signal to the three-state buffers 4301 and 4303. Thus, the address bus 241 has the address, the data bus 242 has the data, and the content update bit bus.
243 indicates the content update bit information, and W indicates the memory control signal 244.
An E signal 2442 is output, and the control memory 201 writes the contents of the data bus 242 and the content update bit bus 243 to the address specified by the address bus 241. T2
At the timing of, the sequencer 4001
434, the WE signal 2442 is negated, the enable signals of the three-state buffers 4301 and 4303 are stopped, and the data output to the data bus 242 and the content update bit bus 243 is stopped. At the timing of T3, the computing device 101
After confirming that the IT signal 1434 has been negated, the output to the address bus 141 and the data bus 142 is stopped, and WR
The signal 1432 is negated. The above is the operation of the memory controller 401 at the time of writing.

FIG. 12 is a time chart at the time of read-modify-write. At the timing of T0, the computing device 1
01 is an address on the address bus 141 and data bus 2
The write data is output to 42 and the RMW signal 1433 is asserted. At the timing of T1, the sequencer 400
1 sends a latch signal to the latches 4011 and 4012 at the beginning of T1, causes the latch 4011 to latch the value of the address bus 141 and the latch 4012 to latch the value of the data bus 142, and asserts the WAIT signal 1434 and the OE signal 2441. To the control memory 201, an address is output to an address bus 241, and an OE signal 2441 is output to a memory control signal 244. The control memory 201 outputs the content of the address specified by the address bus 241 to the data bus 242.
At the timing of T2, the sequencer 4001 sends a latch signal to the latches 4021 and 4022 at the beginning of T2, causes the latch 4021 to latch the value of the data bus 242, the latch 4022 to latch the value of the content update bit bus 243, and negates the OE signal 2441. I do. At the timing of T3, the sequencer 4001 sends the bit merge 420 to the selector 4201.
A bit address for replacing the selection signal for selecting the output 4111 of 2 with the bit merge 4202 is sent to the 3-state buffer 4301 and 4303, and the enable signal 4141 and the WE signal 2442 to the content update determination device 4002 are asserted. , WAIT signal 1434
To negate. Thereby, the address is transmitted to the address bus 241, the data is transmitted to the data bus 242, the content update information is transmitted to the content update bit bus 243, and the WE is transmitted to the memory control signal 244.
A signal 2442 is output, and the control memory 201 writes the contents of the data bus 242 and the content update bit bus 243 to the address specified by the address bus 241. At the timing of T4, the sequencer 4001 outputs the enable signal 4
141, the WAIT signal 1434 and the WE signal 2442 are negated, the enable signals of the three-state buffers 4301 and 4303 are stopped, and the data output to the data bus 242 and the content update bit bus 243 is stopped. At the timing of T5, the computing device 101 confirms that the WAIT signal 1434 has been negated, and the address bus 141, the data bus 14
2 and the RMW signal 1433 is negated. The above is the operation of the memory controller 401 at the time of read-modify-write.

The operation of the content update determining device 4002 is as follows.

At the time of the read-modify-write operation, data is read from the same address in the control memory 201, and then the contents of the control memory 201 are rewritten and rewritten. At the time of read-modify-write, the enable signal 4141 of the comparison circuit 5001 is asserted. 1 for output 5101, 4
If 111 and 4121 do not match, 0 is output. Also, the content of the content update bit bus 243 is latched by the latch 4022 at the time of read of the read-modify-write access, and the content of the latch 4022 is compared with the content of the comparison circuit 5 at the time of write.
By taking the logical sum with the comparison result of 001, it is possible to prevent the occurrence of the loss of the content update bit due to the read modify write.

At the time of reading and writing, the comparison circuit 50 is used.
01 enable signal 4141 is negated,
From the truth table shown in FIG.
Since 0 is output to 01, 1 is output to the output 4131 of the OR gate 5002 regardless of the value of 4132. The content update bit is set to 1 because the content update determination cannot be performed at the time of writing because no read operation is involved.

Control memory 201 and control data transfer device 3
The data flow with 01 is the address bus 231, the data bus 232, the content update bit bus 233, and the memory control signal.
The sensor data transferred from the controlled device 2000 via 234 is written into the control memory 201, and the actuator information on the control memory 201 is transferred to the controlled device 2000.

FIGS. 13 and 14 show the control data transfer device 30.
1 shows a timing chart of an access operation to the control memory 201. FIG. 13 is a timing chart when reading into the control memory 201 and FIG. 14 is a timing chart when writing into the control memory 201. When the actuator data is transferred from the control device 1000 to the controlled device 2000, the control data transfer device 301 sends address information to the address bus 231 to the control memory 201 to the address bus 231 and an output enable signal to the memory control signal 234. The data of the address specified by the bus 241 is stored in the data bus 232 and the content update bit information is stored in the content update bit bus 2.
33. The control data transfer device 301 looks at the value of the content update bit bus 233, and if it is 0, determines that the data has not been updated since the previous transfer to the controlled device 2000, and performs data transfer to the controlled device 2000. No need to do. On the other hand, if the value of the content update bit bus 233 is 1, it is determined that the content has been updated since the previous transfer, and the controlled device 2000 via the network 1200.
At the same time, the content update bit information is reset to 0. When sensor data is transferred from the controlled device 2000 to the controller, the control data transfer device 301 sends address information to the control memory 201 via the address bus 231 and the data bus 232 sends the control data transfer device 301 from the network 1200. A write signal is sent to the received data information and the memory control signal 234, and the data is written to the address specified by the address bus 231 of the control memory 201. At this time, the content of the content update bit is 0. By using the content update determination bit, as for the data in the control memory 201, only the data changed by the access of the computing device 101 is transferred to the controlled device 2000 side, so that unnecessary data transfer can be omitted and the data transfer can be performed. Time can be reduced.

In the timing chart at the time of reading shown in FIG. 13, the transfer control device 3002 outputs the value of the counter 3002 to the address bus 231 at the timing of T0,
Assert signal 2341. In the control memory 201, the content of the address specified by the address bus 231 is output to the data bus 232, and the content update bit information is output to the content update bit bus 233. At the timing of T1, the transfer control circuit 3002 sends a latch signal to the buffer 3201, the latch 3202, and the values of the data bus 232 and the content update bit bus 233 are stored in the buffer 3201, the latch 320, respectively.
2 and the OE signal 2341 is negated. The content determination circuit 3001 looks at the content of the latch 3202, and
In this case, it is determined that the transfer is not performed, the counter 3012 is counted up, the address output to the address bus 231 is stopped, and the read operation ends. If it is 1, the data is transferred to the network 1200 at the timing of T2 in order to transfer the data to the controlled device 2000, and the transfer control device 3002 outputs the WE signal 2342
And sends an enable signal to the tri-state buffer 3211 to latch the read data.
2 to the data bus 232 and the content update bit bus 23
3 is output as 0, and the content update bit of the corresponding address in the control memory 201 is reset. At the timing of T3, the transfer control device 3002 negates the WE signal 2342 and stops outputting the address to the address bus 241, and the timing chart ends.

The write timing chart shown in FIG.
When the data is received by the transfer circuit 3001 via the "00", the transfer control device is notified via the 3100 that the data has been received.
The write timing chart starts. At the timing of T0, the transfer control circuit 3002 outputs an address to the address bus 231, asserts the WE signal 234, and transfers the data received by the transfer circuit 3001 to the data bus 232
It outputs 0 to the content update bit bus, and writes the data to the address specified by the address bus 231 of the scan memory. At the timing of T1, the transfer control circuit 3002 negates the WE signal 2342, and the write operation ends.

FIG. 15 shows a controller 1100 in which the CPU 501 also serves as the computing device 101 and the control data transfer device 301 in FIG. 1 as another embodiment. The CPU 501 and the memory controller 401 are connected to an address bus 451 and a data bus 45.
2, memory control signal 453, content update bit bus 251
The memory controller 401 and the control memory 201 are connected by an address bus 261, a data bus 262,
The memory control signal 263 and the content update bit bus 251 are connected. The configurations of the control memory 201 and the memory controller 401 are the same as those in FIG.
1, the data bus 452 and the memory control signal 453 correspond to the address bus 141, the data bus 142 and the memory control signal 453 of FIG.
62, memory control signal 263, content update bit bus 25
1 is an address bus 241 and a data bus 2 in FIG.
42, memory control signal 244, content update bit bus 24
Corresponds to 3. As shown in FIG. 16, the CPU 501 allocates the memory space 6000 of the control memory 201 to the CPU 5 as shown in FIG.
In the address space 01, the control program execution area 6001 is accessed when the CPU 501 executes the control program, and the data transfer area 6002 is accessed when the CPU 501 transfers data to the controlled device 2000. Sequencer 4001 decodes address input 241 and outputs CP
Judge whether the access from the U501 is to the area 6001 or the area 6002, and output 0 as the access to the area 6001 and 1 as the access to the area 6002 as the control signal 4142 to the content update judging device 4002. Then, the content update determination device 4002 outputs 1 as the content update bit when accessing the area 6001 and 0 when accessing the area 6002 at the time of writing. This allows the CPU 501 to
Operation equivalent to the calculation device 101 and the control data transfer device 301 can be performed.

The time chart when the CPU 501 accesses the control memory 201 via the memory controller 401 is the same as the timing chart of the operation when accessing the area 6001 to be accessed when the control program is executed. 10 to address bus 1 in FIG.
41 and 241 are address buses 451 and 261 respectively, and data buses 142 and 242 are data buses 452 and 242, respectively.
262 and the memory control signals 143 and 244 are the memory control signals 453 and 263 and the content update bit bus 243, respectively.
Correspond to the content update bit bus 251. In addition, the timing chart of the operation at the time of accessing the area 6002 accessed at the time of data transfer is the same as that of FIG. 17 at the time of reading and FIG. 18 at the time of writing, and similarly, the address bus 231 is an address bus. . Although the operation itself is the same as that of the control data transfer device 301, the operation is complicated because the operation is performed via the memory controller 401.

FIG. 17 is a time chart when the CPU 501 reads the transfer data from the control memory 201. At the timing of T0, the CPU 501 outputs an address to the address bus 451 and outputs write data to the data bus 452.
Assert signal 4531. At the timing of T1, the sequencer 4001 sends a latch signal to the latch 4011 at the beginning of T1, causes the latch 4011 to latch the value of the address bus 451, and asserts the WAIT signal 1434 and the OE signal 2441. Address bus 26 to control memory 201
1 for the address, OE signal 263 for the memory control signal 244
1 is output, and the control memory 201
Are output to the data bus 262, and the content update bit information is output to the content update bit bus 251.

At the timing of T2, the sequencer 4001
Sends a latch signal to the latches 4021 and 4022 at the beginning of T2, causes the latch 4021 to latch the value of the data bus 262, the latch 4022 to latch the value of the content update bit bus 251 and negates the OE signal 2631. At timing T3, the sequencer 4001 outputs a selection signal for causing the selector 4201 to select the output 4111 of the bit merge 4202, and outputs the value of 4121 to the bit merge 4202.
The signal to be passed to 1 is passed to the three-state buffer 4301,
Send an enable signal to the content update determination device 4303
In addition to outputting 1 to the output setting signal 4142 to 002, the WE signal 2631 is asserted, and the WAIT signal 45
34 is negated. Thereby, the address bus 261
, The data latched on the latch 4021 on the data bus 262, 0 on the content update bit bus 251,
The WE signal is output as the memory control signal 263, and the control memory 201 writes the contents of the data bus 262 and the content update bit bus 251 to the address specified by the address bus 261. At the timing of T4, the sequencer 400
1 negates the WAIT signal 4534 and the WE signal 2632, stops the enable signals of the three-state buffers 4301 and 4303, and sets the data bus 262 and the content update bit bus 25.
Stop data output to 1. CPU5 at the timing of T5
01 confirms that the WAIT signal 4534 has been negated, stops outputting to the address bus 451 and the data bus 452, and negates the RD signal 4533. The above is the operation of the memory controller 401 when reading the transfer data.

FIG. 18 is a time chart for writing data transferred from the controlled device 2000 to the control memory 201. At the timing of T0, the CPU 501 writes an address on the address bus 451 and outputs data on the data bus 452, and asserts the WR signal 4532. At timing T1, sequencer 4001 latches at the beginning of T1.
011, 4012 and the latch 4011
The value of the address bus 451 is latched by the latch 4012, and the value of the data bus 452 is latched by the latch 4012.
34, the WE signal 2632 is asserted, and the selector 420 is asserted.
1 to select the output 4102 of the latch 4012, and the output selection signal 41 to the content update determination device 4002.
1 is output to 42 and the 3-state buffers 4301 and 4303
The enable signal. Thereby, the address bus 2
An address 61, data on the data bus 262, 0 on the content update bit bus 251 and a WE signal 2632 on the memory control signal 263 are output. The contents of the bus 251 are written. At the timing of T2, the sequencer 4001 outputs the WAIT signal 45
34, negates the WE signal 2632, stops the enable signals of the three-state buffers 4301 and 4303, and stops the data output to the data bus 262 and the content update bit bus 251. At the timing of T3, the CPU 501 sets the WAIT signal 4
534 is confirmed to be negated, and the address bus 45
1, output to the data bus 452 is stopped, and the WR signal 453 is output.
Negate 2. The above is the operation of the memory controller 401 at the time of writing.

Next, an embodiment for the cost problem will be described with reference to FIGS.

As shown in FIG. 19, the process control device 1
0000 is a controller 10001, a process data control device 10002, a memory 10003, a communication processor 10004, an input / output device 10005, a sensor 1000
6, an ammeter 10007 and a display lamp 10008, and the process data control device 10002
The controller 10001 is an IO data bus 21000
Thus, the memory 10003 is connected to the memory data bus 230
00 and a communication processor 10004 by a communication data bus 24000.

The communication processor 10004 is connected to an input / output device 10005 via a serial line.
The input / output device 10005 includes a sensor 10006 and an ammeter 1000
6 and the display lamp 10008 are connected. In this process control device, when information is received from the sensor 10006, the current value of the ammeter 10007 is checked.
An operation of lighting the lamp 10008 as a sign of K is performed. The data movement in the process control device 10000 is as follows.

The controller 10001 reads the data of the sensor 10006 from the memory 10003 via the process data controller 10002. If the information of the sensor 10006 is 1, the data of the ammeter 10007 is read from the memory 10003 via the process data controller 10002. read out. If the read data of the ammeter 10007 is lower than the reference value, 1 is increased, and if the data is higher, 0 is ramped.
Is written to the memory 10003 via the process data control device 10002 as data to The controller 10001 executes this series of processing at regular intervals. On the other hand, the communication processor 10004 starts the input / output device at regular intervals, reads the data of the sensor 10006 and the ammeter 10007, and stores the data of the sensor 10006 and the ammeter 10007 via the process data control device into the memory 10.
003 and the process data control device 10
002 via the memory 10
003 and transferred to the PIO device 10005. When activated by the communication processor, the PIO device 10005 fetches data from the sensor 10006 and the ammeter 10007, converts the data of the ammeter 10007 into 2 bytes of digital information using an A / D converter, and Transfer to The communication processor 10
The data transferred from 004 to the lamp 10008 is fetched. If the data is 1, the lamp is turned on, and if the data is 0, the lamp is turned off. The process control device 10000 operates as described above.

First, access from the controller 10001 will be described. The memory 1000 from the controller 10001 via the process data control device 10002
Access to 3 is performed in 2-byte units. As shown in FIG. 20, an access space of the process data control device 10002 is allocated to a part of the IO address space of the controller 10001, and the controller 1 is connected via this IO space.
0001 accesses the memory 10003. The IO
The space is composed of an address pointer upper byte 12001 constituting a 2-byte address pointer in the process data control device 10002, an address pointer lower byte 12002, and an upper byte write buffer 12002 used by the controller 10001 for write access to the memory 10003,
The memory write buffer 12003 is composed of an upper byte read buffer 12005 and a memory read buffer 12006 which are also used by the controller 10001 for read access to the memory 10003.
Reference numeral 001 accesses a space composed of these 6 bytes of 12001 to 12006, and accesses the memory 10003.

The controller 10001 has the memory 1000
3 is shown in FIG. Controller 1
In order for 0001 to perform write access to the memory 10003, the controller 10001 writes the upper byte of the address to be accessed on the memory 10003 to the upper byte 12001 of the address pointer, and similarly writes the lower byte to the lower byte 12002 of the address pointer (1300).
1). Next, the controller 10001 writes the upper byte of the 2-byte data to be written to the address set in 13001 into the upper byte write buffer 12003.
(13003). Then, the process data control device 10002 writes the lower byte of the two-byte data to be written to the memory write buffer 12004 (13003).
01 and the value of the memory write buffer 12004 at the address indicated by the address pointer composed of the address pointer lower byte 12002, and the value of the upper byte write buffer 12 at the next address indicated by the address pointer.
The value of 003 is continuously written to the memory 10003.

The controller 10001 has the memory 1000
When the data is read from the memory 1000, the controller 10001 sets the address of the data to be read from the memory 10003 in the address pointer upper byte 12001 and lower byte 12002 (13011) in the same manner as at the time of writing. Unlike the first embodiment, the controller 10001 first operates the memory read buffer 1200
Read 6. Then, the process data control device 1000
2 is an address pointer upper byte 12001 and a lower byte 12 from the memory 10003 to the memory 10003.
The value of the address indicated by the address pointer 002 is successively read into the memory read buffer 12006, and the value of the address next to the address indicated by the address pointer is successively read into the upper byte read buffer 12005 (13).
012). Therefore, when the controller 10001 reads the memory read buffer 12006, the controller 10001 returns to the memory 10 indicated by the address pointer.
003 can be read. Next, the controller 10001 sends the upper byte read buffer 1
2005 is read, the upper byte is read, and the read access ends (13013). As described above, the process data control device 10002 accesses the memory 10003 in units of 2 bytes for access from the controller 10001, thereby guaranteeing the synchronization of 2-byte data. The process data control device 10002 accesses the read / write buffers 12003 to 12006 from the controller 10001 to
The controller 10001 sets the address once in the address pointer by providing the address pointer with an auto-increment function for incrementing the address pointer every time 1-byte data is accessed to 003.
6, the controller 10001 can access consecutive addresses in the memory 10003 without setting new addresses in the address pointers 12001 and 12002.

On the other hand, the access from the communication processor 10004 to the memory 10003 is performed by the controller 10001.
Unlike the access from the communication processor 10004, since the entire memory space of the memory 10003 can be specified by an address output from the communication processor and the communication data bus 24000 is 2 bytes,
The address output to 3 is an even address (the least significant bit of the address is 0). Next, a method for accessing the memory 10003 from the communication processor 10004 will be described.

From the communication processor 10004 to the memory 10
At the time of write access to 003, the communication processor 100
Reference numeral 04 denotes an address to the memory 10003 and a communication data bus 2400 to the process data control device 10002.
Output 2-byte write data to 0. Since the bus width of the memory data bus 23000 is 1 byte for write access to the memory 10003, the process data control device 10002 first transfers the lower byte of the communication data bus 24000 consisting of 2 bytes to the memory 10003 from the communication processor 10004. Write to the specified address (even address) and then the communication data bus 24000
Is written twice to the next address (odd address: the least significant bit of the address is set to 1), and the process data control device 10
002 is the communication processor 10 for the memory 10003
The write access from 004 ends.

Next, at the time of read access from the communication processor 10004 to the memory 10003, the address to the memory 10003 is output to the communication processor 10004 and the process data control device 10002 in the same manner as at the time of writing. Since the memory data bus 24000 is a 1-byte bus, the process data control device 10002 reads out the contents of the memory 10003 indicated by the specified address (even address) from the communication processor 10004 and uses this as the lower byte, and the next next address The contents of
(Odd address: the least significant bit of the address is 1) from the memory 10003, and this is set as the upper byte,
Communication processor 1000 as 2-byte data in total
The process data control device 10002 terminates the read access from the communication processor 10004 to the memory 10003 by performing the continuous read twice to output the data to the memory 1000.

As described above, the communication processor 1000
4 accesses the memory 10003. Further, in the process data control device 10002, since the controller 10001 and the communication processor 10004 operate asynchronously, the controller 10001 and the communication processor 10004 simultaneously transmit the process data control device
002 when an access request occurs (memory 1000
3). As a method of resolving the conflict, the process controller 10000 does not use a software such as test and set to resolve the conflict. Instead, a conflict resolution circuit is provided in the process data controller 10002 to quickly resolve the conflict by hardware and access the memory by the conflict. Time overhead is reduced. By this conflict resolution, the exclusiveness of the access to the memory 10003 is realized in units of 2-byte access, and the simultaneousness of 2-byte data is guaranteed.

FIG. 22 shows a process data control device 1000.
2 is shown. The process data control device 10002 is connected to the controller 10001 by an IO data bus 21000.
The communication processor 10004 is connected to the communication data bus 24000 and the communication address bus, and the memory 10003 is connected to the memory data bus 23000 and the memory address bus.
000, a communication data bus 24000, and a memory data bus 23000 are bidirectional buses having a 1-byte width, a 2-byte width, and a 1-byte width, respectively. The IO address bus, the communication address bus, and the memory address bus are all 2-byte widths. . The process data control device 10002 includes an IO decoder 10021 for decoding an IO address output from the controller 10001, a 2-byte simultaneous guarantee circuit 10023 for controlling data at the time of access from the controller 10001, and guaranteeing 2 bytes simultaneously,
An address pointer 10024 for holding an address to a memory at the time of access from 001 and a memory sequencer 100 for controlling data at the time of access from a communication processor
A selector 10027 that selects output data from the 25 and 2-byte simultaneous guarantee circuit 10023 and output data from the memory sequencer 10025 and outputs the selected data to the memory data bus 23000, an address output from the address pointer 10024, and an address output from the communication processor 10004. Selector 1002 for selecting and outputting to memory address bus 3-state buffer 11 for controlling output to IO data bus 21000 from simultaneous 2-byte guarantee circuit
001, a three-state buffer 11003 that also controls the output from the memory sequencer 10025 to the communication data bus 24000, and a three-state buffer 1 that also controls the output of the selector 10027 to the memory data bus 23000.
1002 and a control device 10022 for controlling them.
Consists of

The IO decoder 10021 is connected to the controller 1
When the process data control device 10002 is accessed from 0001, the IO address is decoded, and if the process data control device 10002 is accessed, it is determined whether the access is to the address pointer 10024 or the memory 10003. When the access from the controller 10001 is the access to the address pointer 10024, a data set signal to the upper or lower byte of the address pointer is output to the address pointer 10024. In the case of memory access (access to the memory write buffer 12004 and the memory read buffer 12006), an access request is output to the control circuit 10022. The control circuit 10022 has a conflict determination circuit inside.
10221, and determines whether or not a conflict occurs in access to the memory 10003. Memory 100
If a conflict occurs with the memory sequencer 1002
After waiting until the access to the memory 10003 from 5 is completed, if no conflict occurs, access permission is given to the 2-byte simultaneous assurance circuit 10023 and the selector 10026 is made to select the output of the address pointer 10024. Further, when the access from the controller 10001 is a read access, a read request is output twice consecutively to the memory 10003, and the three-state buffer 11001 to the IO data bus 21000 is set to the output state. If the access from the controller 10001 is a write access, the memory 10003 outputs a write request to the memory 10003 twice in succession and causes the selector 10027 to select the output of the 2-byte simultaneous control circuit. Status buffer 1
Drive 1002. 2-byte simultaneous guarantee circuit 100
Reference numeral 23 denotes a memory 1 which has been granted access permission from the control circuit 10022 and
Access to 0003 is started.

When accessing from the communication processor 10004, the memory sequencer 10025
An access request is output to the control circuit 10022
Of the memory 1000
It is determined whether a contention for access to the memory 1 occurs.
0003 until the access to 0003 is completed.
If there is no contention for access to 0003, the control circuit 10022 grants access to the memory sequencer 10025 and causes the selector 10026 to select the address output of the communication processor 10004. Further, when the access from the communication processor 10004 is a read access, a read request is output twice consecutively to the memory 10003 and the three-state buffer 11003 to the communication data bus 24000 is driven. If the access from the communication processor 10004 is a write access, a continuous write request is output twice to the memory 10003, and the selector 10027 is caused to select the output of the memory sequencer 10025.
Drive the three state buffer 11002 to 3000.

FIG. 23 shows a 2-byte simultaneous guarantee circuit 10023.
Is shown. The 2-byte simultaneous guarantee circuit 10023 includes a simultaneous guarantee control circuit 10231 and a latch 10232 for holding upper byte data when writing to the memory 10003 and a selector 1 for selecting write data to the memory 10003.
0235, a latch 10233 for holding upper byte data at the time of reading to the memory 10003, a latch 10234 for holding lower byte, and a controller 10001.
And a selector 10236 for selecting read data to be read. This 2-byte simultaneous guarantee circuit 100023
Are activated upon receiving an access permission from the control circuit 10022, and are transmitted from the IO decoder 10021 to the upper byte write buffer 12003 and the memory write buffer 12004.
It receives which of the upper byte read buffer 12005 and the memory read buffer 12006 is accessed. The operation of the simultaneous guarantee control circuit 10231 is as follows.
In the case of accessing the upper byte write buffer 12003, the simultaneous guarantee control circuit 10231
And the latch 10232 causes the latch 10232 to latch the data on the IO data bus 21000. In the case of accessing the upper byte read buffer 12005, the simultaneous assurance control circuit 10231 causes the selector 10236 to
234 is selected, and the upper byte data held in the latch 10234 is output to the IO data bus 21000. When accessing the memory write buffer 12004, the simultaneous guarantee control circuit 10231
The simultaneous guarantee control circuit 10231 outputs a write request to the memory 10003 and waits for access permission from the control circuit 10022.
022, the selector 1023
5 selects the IO data bus 21000, and
In 003, write data to the memory write buffer 12004 is written.
Causes selector 10235 to select latch 10232,
By outputting the value of the upper byte read buffer to the memory 10003 and writing the data of the latch 10232, the 2-byte data is continuously written to the memory 10003.

When accessing the memory read buffer 12006, a read request to the memory 10003 is output to the control circuit 10022 in the same manner.
Wait for permission from 0022. When the simultaneous guarantee control circuit 10231 receives an access permission from the control circuit 10022, the control device 10022 outputs a read request twice consecutively.
Numeral 31 outputs a latch signal to the latch 10233 to cause the latch 10233 to hold the first read data (lower byte data). To be held. Simultaneous guarantee circuit 1
Reference numeral 0231 selects the output of the selector 10235 to the latch 10233, and outputs the lower byte data to the IO data bus 21000.

FIG. 24 shows an outline of the address pointer 10024. Address pointer 10024 is in memory 10003
Latch 1024 that holds the upper byte of the address to be output to
A latch 10242 for holding 1 and the lower byte, a 16-bit (2-byte) incrementer 10243 for performing auto-increment to the memory 10003, and selectors 10244 and 10245.
44 and 10245 are latches 10241 and 10241, respectively.
Input data to 242 is transferred to IO data bus 21000 or 16
It selects whether it is the output of the bit incrementer 10243.
The selectors 10244 and 10245 normally select the output of the 16-bit incrementer 10243. However, when the controller 10001 accesses the address pointer, both the selectors 10244 and 10245 use the IO data bus 2.
Select 1000 side. When the controller 10001 accesses the upper byte 12001 of the address pointer,
A latch signal is output from the O decoder 10021 to the latch 10241, and the IO data bus 21 is supplied to the latch 10241.
000 when the controller 10001 accesses the lower byte 12002 of the address pointer.
A latch signal is output from the decoder 10021 to the latch 10242, and the IO data bus 21000 is supplied to the latch 10242.
Is written. When the controller 10001 accesses the memory write buffer 12004 and the memory read buffer 12006, a read / write request signal is output from the control circuit 10022 to the memory 10003, and a latch signal is output to the latches 10241 and 10242. Since the value of the address pointer is incremented for each access and the address pointer is incremented by one at the time of two consecutive accesses, the memory access can be performed correctly.

FIG. 25 shows an outline of the memory sequencer 10025. Memory sequencer 10025 is communication processor 1
2400-byte communication data bus 2400 when writing 0004
Selector 1025 that selects the upper byte and lower byte of write data of 0 and outputs it to memory data bus 23000
2, a latch 10253 for holding the upper byte when reading the communication processor 10004, a latch 10254 for holding the lower byte, and a memory sequencer control circuit 10251 for controlling these. Communication processor 1
At the time of writing from 0004, the memory sequencer control circuit 10251 outputs a write request signal to the control circuit 10022 and waits for an access permission from the control circuit 10022. When the access permission is received from the control circuit 10022, the memory sequencer sets the selector 10254 in response to the two consecutive write access requests to the memory 10003 output from the control circuit 10022, at the time of the first write access, to the next lower byte. The data on the communication data bus 24000 is written to consecutive addresses of the memory 10003 by selecting the upper byte at the time of write access and outputting the least significant bit of the address as 0 at the first write access and 1 at the next write access. . Also, the communication processor 10004 stores the memory 10
When reading from 003, a write request signal is output to the control circuit 10022 and the control circuit 10022 waits for an access permission. The control circuit 10022 gives an access permission to the memory sequencer control circuit 10251 and outputs a read access request to the memory 10003 twice consecutively. Memory sequencer 10
251 receives the access permission from the control circuit 10022 and latches the first read data from the memory 10003 to the latch 10253 and the next read data from the memory 1023 to the latch 1023.
Latches 10253 and 10254
, And a 2-byte data consisting of the outputs of the latches 10253 and 10254 is output to the communication data bus 24000. As described above, the communication processor 100
A 2-byte simultaneous guarantee is also realized for the memory access from 04.

FIG. 26 is a time chart when the controller 10001 accesses the memory 10003 in FIG.
7, the memory 10003 from the communication processor 10004
Here is a time chart at the time of access to.

The process data control device 10002 operates as described above, and
01 guarantees the simultaneity of 2-byte data.

[0070]

As described above in detail, according to the present invention, in the controller for controlling the industrial system, the control memory and the memory in the I / O are used to reduce the amount of data transfer between the control memory and the I / O in the controller. By adding a content update bit indicating whether or not the content of the data in the memory has been updated for each access unit, it is possible to reduce the amount of transfer by transferring only the data with the updated content. Also, it is noted that the access to the memory is mostly read-modify-write, and there is a high probability that the next write access following the read access is performed to the same address, and this method is effective. Also, the determination as to whether or not the content has been updated can be made without any overhead for the determination by overlapping during the read-modify-write access. Also,
The connection between the controller and the process data control device is connected not with a dedicated bus but with a versatile IO bus.
By reducing the bus width of the data bus from the controller to 1 byte, the number of pins of the LSI is reduced and the cost of the entire process control device is reduced. Normally, analog data is handled in two bytes, so that a method for guaranteeing the simultaneity of two-byte data has been described. Also, since the controller and the process data control device are connected by an IO bus,
It is difficult to map the entire space of the memory holding the process data on the IO bus. Therefore, by providing an address pointer in the process data control device and employing an indirect addressing method using the address pointer,
It has become possible to overcome the narrowness of the O-bus space.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an application example 1 of a data transfer method according to the present invention.

FIG. 2 is a schematic diagram of a control system using a programmable controller.

FIG. 3 is a detailed view of the memory controller in FIG. 1;

FIG. 4 is a detailed view control memory of the content update determination device of FIG. 3;

FIG. 5 is a truth table of the comparison circuit of FIG. 4;

FIG. 6 is a diagram showing an access unit of a control memory.

FIG. 7 is a schematic diagram of the sequencer of FIG. 4;

FIG. 8 is a diagram showing a data format at the time of read modify write.

FIG. 9 is a schematic diagram of the transfer device of FIG. 1;

FIG. 10 is an operation timing chart of the memory controller at the time of reading.

FIG. 11 is an operation timing chart of the memory controller at the time of writing.

FIG. 12 is an operation timing chart of the memory controller at the time of read modify write.

FIG. 13 is a timing chart of an operation of reading data from a transfer device into a control memory.

FIG. 14 is a timing chart of a write operation to a control memory of the transfer device.

FIG. 15 is a schematic diagram of a second application example of the data transfer method of the present invention.

FIG. 16 is a memory map of the CPU 501 of FIG.

17 is an operation timing chart of the memory controller 401 when the CPU 501 in FIG. 15 transmits data.

18 is an operation timing chart of the memory controller 401 when the CPU 501 in FIG. 15 receives data.

FIG. 19 is a schematic diagram of a process control device.

FIG. 20 is an IO address mapping viewed from the controller of FIG. 19;

FIG. 21 shows a memory access procedure from the controller of FIG. 19 via the process control device.

FIG. 22 is a schematic diagram of the process data control device in FIG. 19;

FIG. 23 is a schematic diagram of the 2-byte simultaneous guarantee circuit of FIG. 22;

FIG. 24 is a schematic diagram of the address pointer of FIG. 22;

FIG. 25 is a schematic diagram of the memory sequencer of FIG. 22;

FIG. 26 is a time chart of memory access from the controller of FIG. 19;

FIG. 27 is a time chart of memory access from the communication processor of FIG. 19;

[Explanation of symbols]

101 ... calculator, 141, 231, 241, 261
451: Address bus, 142, 232, 242, 26
2,452: data bus, 143, 234, 244, 2
63,453 ... memory control signal, 201 ... control memory,
233, 243, 251: content update bit bus, 301
... Control data transfer device, 401 ... Memory controller,
501 CPU, 1000 control device, 1200 network, 2000 controlled device, 2001 input / output device, 2101 sensor, 2102 actuator, 3
000 device, 4001 sequencer, 4002 content update determination device, 4011, 4012, 4022 latch, 4201 selector 4202 bit merge, 4
301,4302,4303 ... 3-state buffer, 500
1: comparison circuit, 5002: OR gate.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tadashi Okamoto 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant of Hitachi, Ltd. (72) Yoshihiro Miyazaki 5-chome, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Inside the Omika Plant of Hitachi, Ltd.

Claims (6)

[Claims] 1. A memory for storing at least state data representing a state of a control target and control data for controlling the control target, and a computer for obtaining control data of the control target based on the state data stored in the memory. And reading the status data stored in the memory,
A memory controller that writes the data obtained by the computer into the read state data and stores the data in the memory; A control device comprising: 2. The memory controller according to claim 1, wherein the memory controller writes control data obtained by the computer into the read state data.
A control device storing data indicating that the content of data has changed in the memory. 3. A memory for storing at least data representing a state of the control target and data for controlling the control target, and control data of the control target based on the data representing the state of the control target stored in the memory. And a computer that reads one-word data consisting of a plurality of bits from the data stored in the memory, transfers the data to be controlled to the computer, and obtains the one-word data read by the computer. A control device having a memory controller that writes data for control and stores the data in the memory, a data transfer device that reads data rewritten by the memory controller from the memory and transmits the data, a plurality of control targets, and the control A plurality of sensors for measuring the state of the object and a plurality of sensors for controlling the control object. An input / output device for transmitting data representing the state of the control target measured by the plurality of sensors and transmitting data for control sent from the control device to the plurality of actuators; A control system, comprising: a control device. 4. A memory for storing at least process status and control data; a controller for generating control data based on process information stored in the memory; A first data to be read-accessed and a second data following the first data in response to a read access from the controller.
Is read from the memory, the first data is transferred to the controller, and the second data is transferred to the controller.
And a data control device for holding the data of the register in the register. 5. A memory for storing at least process status and control data, a controller for generating control data based on the process information stored in the memory, a memory connected to the memory and the controller, and holding a plurality of bit data. A first data to be subjected to the first write access in the register in response to a first write access from the controller, and a second write access from the controller. And a data controller for continuously storing the second data to be subjected to the second write access and the first data held in the register in the memory. Control device. 6. The data control device according to claim 4, wherein said data control device has an address pointer, and is an indirect access for accessing an address indicated by a corresponding address pointer of said memory in response to access from said controller. A process control device characterized in that: