JPH0283734A - Parallel processing system for digital signal processor - Google Patents

Abstract

PURPOSE:To improve the data arithmetic/transfer processing ability by providing the memory parts on an arithmetic part to store the data showing the arithmetic and transfer instructions respectively and carrying out both arithmetic and transfer jobs of data independently of each other. CONSTITUTION:A selection means 260 of a sequence control part selects and outputs the data read out of a 1st memory circuit 350 when a data arithmetic instruction is synchronous with a data transfer instruction and then selects and outputs the data read out of a 3rd memory circuit 250 when both data instructions are not synchronous with each other. A transfer control signal is outputted from a decoder 370 and an arithmetic control signal is outputted from a decoder 280. Furthermore the data indicating the arithmetic and transfer instructions are stored in a 5th memory circuit 410 and a 6th memory circuit 6 respectively. Then the data read out of both circuits 410 and 420 are computed by an arithmetic/logic circuit 450. Thus the data arithmetic and transfer jobs are carried out independently of each other. Then the data arithmetic/transfer processing ability is improved.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a parallel processing method that improves the processing ability of data calculation and transfer regarding the parallel processing method of a digital signal processor. In the digital signal processor, the digital signal processor has a sequence control section for controlling the data, and an arithmetic section for performing data calculations. first and third memory circuits that determine addresses for storage; and a second memory circuit that is connected to the first memory circuit and reads and stores data stored in the first memory circuit using a timing signal output from the decoder. and the first and second memory circuits 44a; I. A decoder that reads the data, decodes the data contents, and outputs the corresponding control signal for transfer, and when the data operation instruction and transfer instruction are synchronized, the data read from the first storage circuit. a selection means that selects data and selects and outputs data read from the third notation ttlT81 path when the data operation instruction and transfer instruction are asynchronous; The fourth note to remember
The circuit is connected to the selection means and the fourth storage circuit, reads and inputs the output data of the selection means and the data stored in the fourth storage circuit, decodes the contents of the data, and reads the output data of the selection means and the data stored in the fourth storage circuit. A second decoder that outputs a control signal is provided, and the arithmetic unit stores data representing an arithmetic instruction at a predetermined address consisting of addresses of a plurality of words, and data representing a transfer instruction at another predetermined address. Fifth and sixth memory circuits and an arithmetic/logic circuit that inputs data read from the fifth and sixth memory circuits and performs arithmetic/logical operations are provided, and data operations and transfer are performed independently. Configure it as follows.

[Industrial application field]

The present invention relates to a digital signal processor (hereinafter referred to as DSr).
This paper relates to improvements in parallel processing methods (referred to as ').

At this time, there is a need for a parallel processing method that improves the throughput of data calculation and transfer.

[Conventional technology]

FIG. 5 is a block diagram showing the configuration of an example DSP.

FIG. 6 is a block diagram showing the configuration of a conventional sequence control section.

FIG. 7 is a block diagram showing the configuration of a conventional calculation section.

The DSP made with 1.5I performs audio band compression, NC control,
Widely used for image processing, etc. As shown in FIG. 5, the DSP 6 generally includes a RAM 3 that stores input data, an arithmetic section 4 that performs data operations, an address generation section 2 that orders addresses for reading/writing data, It consists of an input/output section 5 that inputs and outputs data, and a sequence control section 1 that controls sequences.

FIG. 6 is a diagram illustrating in detail the control unit 1 shown in FIG. 5. As shown in FIG. In the same figure, a switching circuit (hereinafter S
The adder 9 adds "]" to the output value of the program counter (hereinafter referred to as PC) 8 every clock (machine cycle), and adds Sl! +, 7 to connect the PCB manually. Then, on the PCB, the count value is increased one by one.

Note that the input of SEL 7 is used in the case of a branch instruction.

Corresponding to the address indicated by the count value of the PCB, RO? Data representing an instruction is read from I10. The read data is input to an instance 1-action register (hereinafter referred to as JR) II and is stored at - time, and an address for storing it in the RAM 3 is calculated.

The data temporarily stored in IRII is read out after the above calculation is performed, and the data is read out from II? 12 and temporarily stored.

Then, the data stored in IRII and 12 are read out by a read signal from a decoder (hereinafter referred to as DEC) 13, and control signals for calculation and transfer are created separately in DEC 13, and sent to RA3, etc. Sent out.

On the other hand, in the arithmetic unit shown in FIG. 7 (indicated by 4 in FIG. 5), each one word of data read from the IIAM 3 is input to the registers 14 and 15, and is stored at -. When the data is multiplied, the data is read from the registers 14 and 15, and multiplied by the multiplier (hereinafter referred to as MPY) 16. Temporarily record the multiplication result in register 17 1
．． a.

Next, when it is desired to add the data written in register 14 and the multiplication result of MPY16, the data written in registers 14 and 17 is read out, and the arithmetic/logic circuit (
The addition is performed in step 18 (hereinafter referred to as ALIJ).

”-1 The addition result is temporarily stored in the register 19.

Furthermore, for example, when subtracting data temporarily stored in register 19 and data stored in register 14, the data is input from registers 14 and 19 to i! 2j is output, added to ALU 18, and subtracted.

Then, while data is being transferred from the RAM 3 to the registers 14 and 15, the data is multiplied, for example, in the MPY 16. In this way, data transfer and calculation were performed in parallel.

[Problem to be solved by the invention]

However, in the above-mentioned circuit configuration, there is a problem in that the rate at which computation and data transfer are combined is about 20 to 30%, which is the limit for improving processing efficiency.

Accordingly, an object of the present invention is to provide a parallel processing method that improves the throughput of data calculation and transfer.

[Means to solve the problem]

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, in a digital signal processor having a random access memory, a sequence control section that controls a program sequence, and an arithmetic section that performs data operations, 350 and 250 input data representing a predetermined program instruction. First and third storage circuits determine addresses for storing the data in the random access memory.

A second storage circuit 360 is connected to the first storage circuit and reads and stores data stored in the first storage circuit in accordance with a timing signal output from the decoder 370.

370 is connected to the first and second 0 circuits, and the first
and a decoder that reads data stored in the second storage circuit, decodes the content of the data, and outputs a corresponding control signal for transfer.

260 selects the data read from the first storage circuit when the data operation instruction and the transfer instruction are synchronized, and selects the data read from the third storage circuit when the data operation instruction and the transfer instruction are asynchronous. This is a selection means for outputting.

A fourth storage circuit 270 is connected to the selection means and inputs and stores the output of the selection means.

280 is connected to the selection means and the fourth storage circuit, reads and inputs the output data of the selection means and the data stored in the fourth storage circuit, decodes the contents of the data, and generates the corresponding control signal for calculation. This is the second decoder that outputs. ”7
350.360.370.250.260.270 and 280 are provided in the sequence control section.

410 and 420 consist of multiple word addresses, and the fifth and sixth # marks indicate data representing an arithmetic instruction at a predetermined address and data representing a transfer command at another predetermined address.
This is a memory circuit.

450 is an arithmetic/logic circuit that reads data stored in the fifth and sixth storage circuits and manually performs arithmetic/logical operations. The above 410, 420 and 450 are provided in the calculation section.

Then, data calculation and transfer are performed independently.

[For production]

In FIG. 1, selection means 2 provided in the sequence control section
At 60, when the data calculation command and the transfer command are synchronized, the data read from the first storage circuit 350 is selected, and when the data calculation command and the data transfer command are asynchronous, the data read from the third storage circuit 250 is selected. Select and output the data.

Then, the decoder 370 outputs a control signal for transfer, and the second decoder 280 outputs a control signal for calculation.

Furthermore, the fifth and sixth storage circuits 410 and 420 of the arithmetic unit are configured to store data representing a calculation instruction at a predetermined address and data representing a transfer instruction at another predetermined address. do. For example, 172 address areas of each of the fifth and sixth memory circuits old 05420 are used for calculations, and the remaining 1/2 address area is used for transfer.

As a result, calculation and transfer can be performed independently.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a sequence control section according to an embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of the arithmetic unit according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating the operation of butterfly calculation when using the circuit of the embodiment.

The same reference numerals indicate the same objects throughout the figures.

FIG. 2 shows the configuration of the sequence control section, in which one sequence control circuit is provided for calculation and one for transfer. In the figure, when the transfer instruction and the calculation instruction operate synchronously (that is, at the same timing), SP, L
26 selects the input from lR35 from the control signal B from DliC37, and for example, data representing arithmetic instructions of 7 out of 32 bits is stored in ROM34-lR35-5EL.
26 → lR27, and a calculation control signal is created in D13C2B.

If the transfer and calculation are to be performed independently, the 5EL26 selects the input from the 1R25. As a result, the two sequence control circuits become completely independent.

However, since the transfer is performed to prepare data for calculation, if the calculation registers (registers I4.15 and 1 of the calculation section shown in Figure 7) are used for calculation, the transfer can be performed independently. However, efficiency does not improve. Therefore, the examples described below are added to the examples of 7j water.

In Figure 3, register files 41, 42 and 4G
can read and write two pieces of data at the same time, and can read and write one piece of data.

Further, each register file has a size of, for example, 16 words, and 8 words are used for calculations, and the other 8 words are used for the next calculation.

As an example of a case where calculation and transfer are performed separately, butterfly calculation, which is the basis of fast Fourier transform, will be explained.

In Figure 4, the complex numbers a+jb, c+jd and u+j
Given v, find e, f, g, and h, respectively. The calculation formula is as follows.

That is, (c-1jd)X (u+jv)= (c u - d v ) 4- j (c v +
d u ), e+jf= (a+(cu-dv)l
+j (bl (cv 1-du) l, g+
jh-(a-(cu-dv)l →-j (b-(c■
Todu)l.

Data is stored in register files 41, 42 and 46 in the same figure (
Arrange as shown in bl. The register file 4G stores calculation results.

The calculation is performed by reading the data written in each register file. In this case, addresses 0 to 7 are used for calculations,
The addresses from 8 to F are used for transfer, but when one butterfly operation is completed, the addresses from 8 to F are used for the calculation, and the addresses from 0 to
7 address is used for transfer.

As a result, calculations and transfers can be performed completely independently, greatly improving processing efficiency.

FIG. 4 (C1) shows a time chart explaining the operation of the two series of embodiments, which shows that the operation can be executed in 10 machine cycles.

On the other hand, if implemented with a conventional circuit, an I9 machine pulse would be required.

〔Effect of the invention〕

As explained above, according to the present invention, parallel processing capability can be improved by performing data calculation and transfer completely independently.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a block diagram showing the configuration of a sequence control section according to an embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of a calculation section according to an embodiment of the present invention. Figure 4 is a diagram explaining the operation of butterfly calculation when using the circuit of the embodiment, Figure 5 is a block diagram showing the configuration of an example DSP, and Figure 6 is a block diagram showing the configuration of a conventional sequence control section. FIG. 7 is a block diagram showing the configuration of a conventional calculation section. In the figure, 350 is a first memory circuit, 360 is a second memory circuit, 2
50 is a third memory circuit, 270 is a fourth memory circuit, 41
0 is the fifth memory circuit, 420 is the sixth memory circuit, 260
370 is a decoder, 280 is a second decoder, and 450 is an arithmetic/logic circuit.ヰ-Example f) vsP/)s はC (indicating block colloquial words 5 轻 mumzu now water money 1〉-kensu I4Al fistyfuTnme corner without indicating pro...7) Nicha b good

Claims (1)

[Scope of Claims] A digital signal processor having a random access memory, a sequence control unit that controls a program sequence, and an arithmetic unit that performs data operations, wherein the sequence control unit is provided with data representing a predetermined program instruction. first and third storage circuits (350, 250) for inputting and storing data and determining an address for storing the data in a random access memory; a second storage circuit (360) that reads and stores the data stored in the circuit according to the timing signal output from the decoder (370);
A decoder (370) reads out the data stored in the storage circuit, decodes the contents of the data, and outputs a corresponding transfer control signal, and when the data operation instruction and transfer instruction are synchronized, the decoder (370) a selection means (260) for selecting the data read from the first storage circuit, and selecting and outputting the data read from the third storage circuit when the data calculation instruction and the transfer instruction are asynchronous; a fourth storage circuit (270) connected to input and store the output of the selection means;
a second memory circuit connected to the fourth memory circuit, which reads and inputs the output data of the selection means and the data stored in the fourth memory circuit, decodes the contents of the data, and outputs a corresponding control signal for calculation; a decoder (280), and in the arithmetic unit, fifth and sixth blocks are provided, each of which is composed of a plurality of word addresses and stores data representing an arithmetic command at a predetermined address and data representing a transfer command at another predetermined address. Storage circuits (410, 420) and an arithmetic/logic circuit (450) that inputs data read from the fifth and sixth storage circuits and performs arithmetic/logical operations are provided, and data operations and transfer are performed independently. A parallel processing method for a digital signal processor that is characterized in that it performs processing in parallel.