JP2001242878A - Data processor and pcm sound source device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct primary data processing at a high speed while conducting audio signal processing with a DSP by not conducting address computations in a product sum arithmetic section. SOLUTION: An address generating circuit is provided for each of special processing such as waveform tracing in the DSP besides the product sum arithmetic section. For example, in the waveform tracing address generating circuit, a leading address that is set first is selected and outputted by a first address selecting circuit 232. Then, the address is sequentially increased by one at a time by a +1 incrementor 236 until an end address that is later set and outputted. When audio signals are data which include loop portions, a loop address set by a second address selecting circuit 238 is selected and the addresses from the above address to the end address are successively repeatedly outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and a PCM tone generator for performing a PCM tone generator on a PCM audio signal, for example.

[0002]

2. Description of the Related Art In a conventional basic DSP for audio signal processing, the operation resources of a product-sum operation circuit are used not only to process audio data but also to generate an address of an internal working memory (address operation) and to store an external memory. It must be used for address generation (address operation). However, such a product-sum operation circuit of the DSP for audio signal processing is a circuit designed to execute audio signal processing (convolution operation such as FIR filter processing, IIR filter processing, etc.) at high speed. When it is used for a special operation other than the audio signal processing such as an address generation processing of a memory such as an address jump processing, the operation efficiency becomes very poor.

Therefore, in a recent DSP for audio signal processing,
A circuit configuration that can generate addresses without imposing a load on the product-sum operation circuit is employed. FIG. 6 shows a circuit configuration of such an audio signal processing DSP. FIG.
FIG. 1 is a diagram showing a configuration of a sound source device 900 using such a conventional DSP 920 for processing an audio signal. In the DSP for audio signal processing 920 shown in FIG.
, An address generation circuit 922 performs an address generation process of the internal working memory 923, and an address generation circuit 924 performs an address generation process of the external memory 940 based on the instruction from the CPU. Further, a DMA circuit 925 for performing DMA transfer is separately provided, so that data transfer with the external memory 940 can be performed at high speed.

Each of these address generation circuits 922, 924
In, linear addressing that automatically increments or decrements the address by one, mo
Address generation processing is performed in an addressing mode such as dulo addressing and bit reverse addressing. Then, the product-sum operation circuit 927 calculates
For example, FIR (Finite Impulse Response) filter processing, IIR (Infinite Impulse Response) filter processing, FFT (Fast Fourier Transform) processing, Interpola
When performing the Option filter processing and Decimation filter processing, the external memory 940 is exclusively provided via the working memory 923 and the external memory interface 926.
It is sufficient to perform these arithmetic processings on input data, and it is possible to avoid spending resources on address arithmetic processing for acquiring data.

[0005]

However, the function of the above-described address generation circuit provided in the conventional DSP for audio signal processing is very limited. Widely used P
The address generation function required for processing the CM audio signal could not be realized.

More specifically, in PCM audio signal processing such as PCM sound source processing, for example, an address is traced from a specified start address to an end address, and the processing ends.
Memory access such as looping between specific addresses, or tracing an address from a specified start address to an end address and then jumping to another address is required. However, the address operation for performing such a memory access is a process for performing a complicated operation, and the address generation circuit of the sound signal processing DPS cannot cope with the conventional operation.

As a result, the address is generated by using the operation resources of the product-sum operation circuit of the DSP, and the operation resources cannot be used only for the processing of the original sound signal such as the sound source processing. There is a problem that the performance of the audio signal processing, that is, the processing speed cannot be increased.

Accordingly, an object of the present invention is to provide an address generation circuit which can appropriately generate an address necessary for processing a PCM audio signal, and thereby, when applied to the processing of a PCM audio signal, has an original function. It is an object of the present invention to provide a data processing device capable of performing desired signal processing efficiently and at high speed such that signal processing can be performed at high speed. Another object of the present invention is to provide an address generating circuit capable of appropriately generating an address necessary for processing a PCM audio signal, thereby efficiently and quickly performing a sound source process using the PCM audio signal. It is an object of the present invention to provide a PCM sound source processing device capable of performing the above.

[0009]

According to a first aspect of the present invention, there is provided a data processing apparatus for performing desired data processing on arbitrary data to be processed. General-purpose arithmetic processing means for performing a predetermined arithmetic processing based on an input command with respect to the data, and an arithmetic processing means for performing the specific data processing in the arithmetic processing means when performing the specific data processing And first address generating means for generating an address for performing a memory access accompanying the above.

Preferably, the arithmetic processing means further includes a second address generating means for generating an address for performing a memory access in the arithmetic processing means relating to processing other than the specific data processing. Means are
A memory access is performed based on the address generated by the first address generation unit and the address generated by the second address generation unit, and the desired data processing including the specific data processing is performed. Preferably, the apparatus further includes a processing procedure storage unit that stores a processing procedure for performing a predetermined data process on a series of time-series data, wherein the arithmetic processing unit performs processing according to the stored processing procedure. The predetermined arithmetic processing is performed on each data of the series of time-series data.

[0011] Specifically, the series of time-series data is:
Audio signal data, the predetermined data processing is arbitrary audio signal processing, and the specific data processing is processing including trace processing of the audio signal data. More specifically, the series of time-series data is PCM audio waveform data, and the predetermined data processing is performed by the PCM.
M sound source processing, and the specific data processing is performed by the PC
It includes one or both of trace processing of M audio waveform data and reverb processing of audio signals.

Further, the PCM tone generator according to the present invention comprises: an external memory means for storing a series of PCM sound waveform data and arbitrary data relating to the PCM sound source processing for the PCM sound waveform data;
A data processing device for performing the PCM sound source processing on the audio waveform data and outputting baseband digital audio data; and a digital / analog conversion means for converting the output baseband digital audio data to an analog audio signal. Wherein the data processing device has a processing procedure storing means for storing a processing procedure of the PCM sound source processing, and a predetermined procedure for each data of the series of PCM audio waveform data according to the stored processing procedure. An arithmetic processing means for performing arithmetic processing; and a first means for generating an address when performing a memory access for the specific data processing in the arithmetic processing means when performing a specific data processing included in the PCM tone generator processing. Address generating means and an internal memory for temporarily storing arbitrary data during the arithmetic processing A stage, an internal memory address generating means for generating an address when performing a memory access to the internal memory means, and an external memory address generating means for generating an address when performing a memory access to the external memory means External memory interface means for performing memory access to the external data storage means based on the generated address, wherein the arithmetic processing means comprises an address generated by the first address generation means. Accessing the internal memory means and the external memory means based on an address generated by the internal memory address generation means and an address generated by the external memory address generation means, and including the specific data processing; Perform processing.

Specifically, the specific data processing includes a waveform data trace processing. More specifically, the specific data processing includes reverb processing of audio data.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
This will be described with reference to FIGS. In the present embodiment, the present invention will be described by exemplifying a PCM sound source device that demodulates an input PCM audio signal and generates an analog audio signal that can be output from a speaker, for example. FIG. 1 is a block diagram showing a configuration of the PCM sound source device 1. The PCM tone generator 1 has a host CPU 10, an audio signal processing DSP 20, a D / A converter 30, and an external memory 40 as its main components.

First, the overall configuration of the PCM tone generator 1 will be outlined. The host CPU 10 is a PC
PCM so that the M tone generator 1 can perform desired operations as a whole and appropriately reproduce and output analog audio signals.
Each component of the sound source device 1 is controlled. Specifically, for example, a PCM audio signal to be processed (hereinafter, this may be referred to as waveform data) is obtained via input / output means (not shown), and external memory is obtained via the audio signal processing DSP 20. Store in 40. Also, various control commands are sent to the audio signal processing DSP 20 so that the audio signal processing DSP 20 appropriately performs desired processing.

The audio signal processing DSP 20 includes a host CP
Under the control of U10, the PCM audio signal recorded in the external memory 40 is subjected to desired processing such as demodulation processing to generate a baseband digital audio signal, which is output to the D / A converter 30. I do. The configuration and operation of the audio signal processing DSP 20 will be described later in detail.

The D / A converter 30 converts the baseband digital audio signal input from the audio signal processing DSP 20 into an analog signal, and outputs the analog audio signal from the PCM tone generator 1 as an analog audio signal that can be output from a speaker or the like. I do.

The external memory 40 is a DSP for processing an audio signal.
20 is a memory for storing data used for desired processing. The external memory 40 stores a PCM audio signal to be processed, which is DMA-transferred from the host CPU 10 via the audio signal processing DSP 20. Further, when the DSP 20 for audio signal processing performs reverb processing (reverberation processing) or the like, it is used as a long-term delay memory.

Next, the DS for audio signal processing according to the present invention will be described.
The configuration of P20 will be described in detail. As shown in FIG. 1, the DSP 20 for audio signal processing includes an instruction memory 202,
Control section 206, internal memory address generation circuit 208, working memory 210, PCM sound source processing address generation circuit 2
12, external memory address generation circuit 252, DMA circuit 254, external memory interface (I / F) 25
6. It has a product-sum operation circuit 258 and an external input / output interface (I / F) 260.

The instruction memory 202 includes an audio signal processing DS.
This is a memory for storing processing procedures performed in P20, and is sequentially read by the control unit 206.

The control unit 206 includes an audio signal processing DSP 2
0 controls each component of the audio signal processing DSP 20 so that the desired processing is performed as a whole. Specifically, based on a command according to a control command from the host CPU 10, a processing program for executing the command is stored in the command memory 2.
Read sequentially from 02. Then, a parameter for controlling an address for accessing data used for the processing is set to the internal memory address generation circuit 20 as needed.
8. Write to the PCM tone generator address generation circuit 212 and the external memory address generation circuit 252, respectively. Then, a product-sum operation instruction is output to the product-sum operation circuit 258, and a desired process is actually performed.

The internal memory address generating circuit 208 is controlled by the control unit 206 to
Generates an address in the working memory 210 in which the data to be used for the processing is stored, or in which the data resulting from the processing in the product-sum operation circuit 258 is stored,
Apply to working memory 210.

PCM tone generator address generation circuit 212
Stores data to be used for the waveform data tracing process and the digital reverb process in the product-sum operation circuit 258 based on the parameters and control commands set by the control unit 206 when the process is performed. An address in the external memory 40 is generated and applied to the external memory 40.

PCM tone generator address generating circuit 212
Will be described in more detail with reference to FIGS. FIG. 2 shows an address generation circuit 21 for PCM sound source processing.
2 is a block diagram showing a configuration of FIG. The PCM tone generator address generation circuit 212 includes a parameter register 214,
It has a waveform data trace address generation circuit 230 and a digital reverb address generation circuit 240.

The parameter register 214 is a register unit for storing parameters serving as control data when performing an automatic address generation process in the waveform data trace address generation circuit 230 and the digital reverb address generation circuit 240 to be described later. The parameters are stored in each register by the control unit 206.

Specifically, the parameter register 214
Has a start address register 216, an end address register 218, a loop start address register 220, and a work register 222, as shown in FIG. 3, as registers for storing data referred to by the waveform data trace address generation circuit 230.

Here, an audio signal to be processed by the PCM tone generator 1 and an address generation specification for tracing the audio signal will be described with reference to FIG. PCM tone generator 1
The audio signal to be processed is a signal without loop (waveform)
And a signal with a loop (waveform). The non-loop signal is, for example, an audio signal as shown in FIG. 4A, and has a waveform such that the same waveform does not repeat from the start point to the end point. On the other hand, the loop presence signal is, for example, an audio signal as shown in FIG. 4B, and a certain waveform (a waveform from the loop start circle to the loop end point) is repeated from a certain point after the start (loop start point). The waveform is as follows. Data obtained by sampling such audio signals and arranging them in chronological order is called waveform data.

The process of tracing such waveform data is a process of starting a trace from a designated start address, tracing to a designated end address, and stopping the trace in the case of a waveform without a loop. . In the case of a waveform with a loop, tracing starts from a specified start address, traces to a specified end address, then jumps to a specified loop start address and returns to trace to an end address. This is a process for repeating the process. Therefore, in order to perform such a trace, in the case of a waveform without a loop,
Need start and end address information,
In the case of a waveform with a loop, information on a start address, an end address, and a loop start address is required.

As described above, the waveform of the audio signal processed by the PCM tone generator 1 is defined, and accordingly, the head address register 216 of the parameter register 214 stores
The start address of the traced waveform data is stored, and the end address of the traced waveform data is stored in the end address register 218. The loop start address register 220 stores the start address of a loop in the case where the waveform data has a loop. The work register 222 stores the address of the waveform data to be traced next, that is, accessed, which is generated during the address generation processing.

The parameter register 214 is a register for storing data to be referred to by the digital reverb address generation circuit 240, as shown in FIG. 5, a ring buffer head address register 224, a ring buffer end address register 226, and a reverb tap. It has an address register 228. The ring buffer head address register 224 stores the head address of the ring buffer constructed in the external memory 40, and the ring buffer end address register 226 stores the end address of the ring buffer constructed in the external memory 40. Further, the reverb tap address register 228 stores a desired address in the ring buffer of the constructed external memory 40.

Address generation circuit 2 for waveform data trace
When the audio signal processing DSP 20 performs a process of tracing waveform data, the audio signal processing unit 30 sequentially generates an address of the external memory 40 of data used for the process.

Waveform data trace address generation circuit 2
30 will be described in further detail with reference to FIG.
The waveform data tracing address generation circuit 230 includes a first
Address selection circuit 232, last stage register 234, +
It has one incrementer 236 and a second address selection circuit 238.

The first address selection circuit 232 selects an address stored in any one of the start address register 216, the end address register 218, the loop start address register 220 and the work register 222 of the parameter register 214, Output to the final stage register 234.

The last-stage register 234 is a register that stores the address selected by the first address selection circuit 232 and that actually accesses the external memory 40.

The +1 incrementer 236 increments the address output from the final stage register 234 and applied to the external memory 40 by one, and outputs it to the second address selection circuit 238.

The second address selection circuit 238 selects one of the addresses stored in the end address register 218 or the loop start address register 220 of the parameter register 214 or the address generated by incrementing by one by the +1 incrementer 236. One of the addresses is selected, and the parameter register 214
In the work register 222.

In the waveform data tracing address generation circuit 230 having such a configuration, first, the first address selection circuit 232 first selects the address stored in the head address register 216, 234 is temporarily stored and applied to the external memory 40. The address stored in the final stage register 234 is incremented by one by a +1 incrementer 236, and compared with the end address stored in the end address register 218 in the second address selection circuit 238. Then, the end address register 21
If it does not exceed the address stored in 8,
This is selected and stored in the work register 222.

The address stored in the work register 222 is selected by the first address selection circuit 232, set in the final register 234, and applied to the external memory 40. This address is again incremented by +1 incrementer 236
And the second address selection circuit 23
At 8, the address is compared with the address stored in the end address register 218 and stored in the working register 222. Thereafter, in the second address selection circuit 238,
This process is repeated as long as the address incremented by one in the +1 incrementer 236 does not exceed the address stored in the end address register 218, and the address incremented by one from the address stored in the head address register 216. But,
It is applied to the external memory 40 in order.

During such processing, the second
In the address selection circuit 238, if the address incremented by one in the +1 incrementer 236 exceeds the address stored in the end address register 218, the address is then stored in the end address register 218 of the parameter register 214. The current address and the address stored in the loop start address register 220 are compared. If these addresses are equal, it is determined that the waveform data to be traced is not a loop waveform, and the trace processing in the audio signal processing DSP 20 is also terminated. The address generation processing is also terminated.

If the address stored in the end address register 218 of the parameter register 214 is different from the address stored in the loop start address register 220, it is determined that the waveform data to be traced is a loop waveform. , The second address selection circuit 23
8 selects an address stored in the loop start address register 220 and stores it in the work register 222. Then, the address stored in the work register 222 is selected by the first address selection circuit 232, set in the final register 234, and applied to the external memory 40. Thereby, the repetitive reproduction of the loop portion of the waveform data is started.

Thereafter, the address set in the last stage register 234 is incremented by 1 by a +1 incrementer 236 and the end address register 218 is added to the It is compared with the stored address. As long as the address does not exceed the address stored in the end address register 218, this is stored in the work register 222 and applied to the external memory 40 in order.

In the second address selection circuit 238,
If the address incremented by one exceeds the address stored in the end address register 218, the end address register 218 is processed in the same manner as described above.
The address stored in the loop start address register 220 is compared with the address stored in the loop start address register 220, and since these are different, the address stored in the loop start address register 220 is selected again and Set. Thus, the trace of the waveform data of the third loop is started. By repeating such processing, the control unit 206
The waveform data of the loop portion is repeatedly traced until the end of the processing is instructed to the waveform data tracing address generation circuit 230.

Digital reverb address generation circuit 2
When digital reverb processing (reverberation processing) is performed in the audio signal processing DSP 20, the address 40 sequentially generates addresses of data used in the processing in the external memory 40.

Digital reverb address generation circuit 2
40 will be described in detail with reference to FIG.
The digital reverb address generation circuit 240 includes a base address counter 242, an address adder 244, an address subtractor 246, an address adder 247, an address selection circuit 248, and a final register 250.

The base address counter 242 sequentially counts 1
This is a counter that increments by one.

The address adder 244 stores the count value of the base address counter 242 and the value of the parameter register 2
The addresses stored in the 14 ring buffer head address registers 224 and the addresses stored in the predetermined reverb tap address registers 228 _-i (i = 1 to n) are added and output to the address subtractor 246 and the address selection circuit 248. I do.

The address subtractor 246 subtracts the address stored in the ring buffer end address register 226 from the address of the addition result input from the address adder 244, and outputs the result to the address adder 247.

The address adder 247 adds the address stored in the ring buffer head address register 224 to the address of the subtraction result input from the address subtractor 246, and outputs the result to the address selection circuit 248.

The address selection circuit 248 selects either the address of the addition result input from the address adder 244 or the address of the addition result input from the address adder 247, and outputs the selected address to the final stage register 250.

The last-stage register 250 is a register for storing an address selected by the address selection circuit 248 and for actually accessing the external memory 40.

In the waveform data tracing address generation circuit 230 having such a configuration, first, in the address adder 244, the base address counter 2
The address of the ring buffer head address register 224 is added to the count value of 42, and furthermore, a predetermined reverb tap address register 228 _-i (i = 1 to n)
Add the address of

Next, in the address subtractor 246 and the address selection circuit 248, the result of the addition is compared with the address stored in the ring buffer end address register 226. If the addition result does not exceed the address stored in the ring buffer end address register 226, the ring buffer end address register 226 selects this addition result and stores it in the final stage register 250, and the external memory 40 Is applied.

If the addition result exceeds the address stored in the ring buffer end address register 226, the address subtractor 246 calculates the addition result from the ring buffer end address register 2
26, the address stored in the ring buffer head address register 224 is added to the result of the subtraction in the address adder 247, and this is added to the final register 250 via the address selection circuit 248. Store and apply to external memory 40.

When the address is output in this manner, the value of the base address counter 242 is incremented by one, and the same processing is performed again. Thereafter, this process is repeated until the control unit 206 instructs the digital reverb address generation circuit 240 to end the process. The above is the description of the PCM sound source processing address generation circuit 212.

The external memory address generation circuit 252 of the DSP 20 for audio signal processing stores data to be used for processing in the product-sum operation circuit 258 based on the control from the control unit 206, or the product-sum operation circuit 258 External memory 4 in which data of the result of the processing in
An address of 0 is generated and applied to the external memory 40 via the external memory I / F 256.

The DMA circuit 254 is a control circuit for DMA-transferring audio waveform data (PCM audio signal) to be processed from the host CPU 10 to the external memory 40.

The external memory I / F 256 is an interface between the audio signal processing DSP 20 and the external memory 40. The external memory I / F 256 includes a PCM sound source processing address generation circuit 212, an external memory address generation circuit 2
The address generated by either the DMA circuit 52 or the DMA circuit 254 is applied to the external memory 40. Then, when writing data to the external memory 40, the data input from the DMA circuit 254 or the product-sum operation circuit 258 is output to the external memory 40 in synchronization with the output of the address. When data is read from the external memory 40, the data stored at the applied address output from the external memory 40 is read and output to the product-sum operation circuit 258.

The product-sum operation circuit 258 operates based on the operation processing command input from the control
A desired product-sum operation is performed on the waveform data stored at 0 and read via the external memory I / F 256, and finally baseband digital audio data is generated and output to the external input / output I / F 260. At that time, the product-sum operation circuit 25
In step 8, the intermediate calculation result is appropriately written into the work memory 210, and the intermediate calculation result is read from the work memory 210 as appropriate, and the process proceeds.

The external input / output I / F 260 is an interface for outputting the baseband digital audio data generated and input by the product-sum operation circuit 258 from the audio signal processing DSP 20. Output to the D / A converter 30. The configuration of the audio signal processing DSP 20 has been described above.

Next, the PCM tone generator 1 having such a configuration will be described.
The operation of will be described. First, under the control of the host CPU 10, the waveform data of the sound to be produced by the PCM tone generator 1 is stored in the DMA of the DSP 20 for audio signal processing.
The data is transferred from the host CPU 10 to the external memory 40 via the audio signal processing DSP 20 using the transfer function.

Next, the host CPU 10 transmits parameters such as a start address, an end address, and a loop start address for tracing the transferred waveform data to the DSP 20 for audio signal processing. DSP2 for audio signal processing
In the case of 0, the control unit 206 accepts this and sets the parameter register 2 of the PCM sound source processing address generation circuit 212 to
14 is set in a predetermined register.

When the host CPU 10 instructs the audio signal processing DSP 20 to start sound generation, the control unit of the audio signal processing DSP 20
Read the processing program based on the command from
Based on the read program and an instruction from the host CPU 10, the internal memory address generation circuit 208, P
Commands are output and controlled to the CM sound source processing address generation circuit 212, the external memory address generation circuit 252, and the product-sum operation circuit 258 to start desired processing.

Specifically, first, the waveform data is traced according to the set parameters. That is, as described above, the waveform data tracing address generation circuit 230 of the PCM sound source processing address generation circuit 212 sequentially generates tracing addresses, and outputs the trace addresses to the external memory I / F 256.
And the waveform data is sequentially read out. The waveform data read from the external memory 40 is sequentially input to the product-sum operation circuit 258, and the product-sum operation circuit 258 performs processes such as a pitch process, a filter process, a reverb process, and a volume process.

Writing and reading to and from the working memory 210 and the external memory 40, such as data other than waveform data necessary for performing each of these processes and data to be temporarily stored, are performed by the internal memory. This is performed using the addresses generated by the address generation circuit 208 and the external memory address generation circuit 252. In particular, regarding the reverb processing, the external memory 4
The address for the external memory 40 at this time is generated by the digital reverb address generation circuit 240 of the PCM tone generator address generation circuit 212 by performing the above-described processing. I do.

Finally, the product-sum operation circuit 258 generates a baseband digital audio signal,
It is output to the D / A converter 30. The D / A converter 30 converts the digital audio signal to an analog signal, outputs the analog signal from the PCM sound source device 1, and reproduces the audio as an external speaker, for example.

As described above, in the PCM tone generator 1 of the present embodiment, the DSP 20 for audio signal processing is provided with an address generation circuit for generating a complicated address required at the time of tracing or reverberation of waveform data. Therefore, the product-sum operation circuit 25 of the audio signal processing DSP 20
8 can spend its resources only on the arithmetic processing on the original audio data. Therefore, PCM sound source processing can be performed efficiently at high speed. In other words,
If the same processing is performed, a PCM tone generator can be realized with a DSP that is slower than the conventional DSP.

Further, the address generation circuit can automatically generate a complicated address only by simple parameter setting, so that the instruction code can be easily programmed. That is, complicated programming does not have to be performed to perform complicated addressing. As a result, the size of the instruction code and the number of programming steps can be reduced. Also,
The address generation circuit can be realized with a simple circuit configuration as shown in FIGS.

Note that the present invention is not limited to the present embodiment, and various suitable modifications are possible. For example, in the present embodiment, the present invention has been described by exemplifying a PCM tone generator for processing a PCM audio signal.
The present invention is not limited to a device for processing M audio signals. The present invention may be applied to an audio signal that has been subjected to another modulation process, or may be applied to a similar process for another signal other than the audio signal. Further, the internal configuration of the PCM tone generator address generation circuit 212, the method of defining waveform data, the specification of setting parameters, and the like may be arbitrarily determined.

[0069]

As described above, according to the present invention, there is provided an address generation circuit which can appropriately generate an address necessary for processing a PCM audio signal, thereby providing an address generation circuit for processing a PCM audio signal. Can provide a data processing apparatus capable of performing desired signal processing efficiently and at high speed, such that the original signal processing can be performed at high speed. In addition, a PCM sound source that has an address generation circuit that can appropriately generate an address necessary for processing a PCM audio signal, and that can efficiently and quickly perform an original sound source process using the PCM audio signal A processing device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PCM tone generator according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a PCM sound source processing address generation circuit of the audio signal processing DSP of the PCM sound source device illustrated in FIG. 1;

FIG. 3 is a block diagram showing a configuration of a waveform data tracing address generation circuit of the PCM tone generator address generation circuit shown in FIG. 2;

FIG. 4 is a diagram for explaining an operation of the waveform data tracing address generation circuit 230 shown in FIG. 3 and an operation of the waveform data tracing address generation circuit in the audio signal processing DSP shown in FIG. 2; It is.

FIG. 5 is a block diagram showing a configuration of a digital reverb address generation circuit of the PCM tone generator address generation circuit shown in FIG. 2;

FIG. 6 is a block diagram showing a configuration of a sound source device using a conventional DSP for processing an audio signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... PCM tone generator, 10 ... Host, 20 ... DSP for audio signal processing, 30 ... D / A converter, 40 ... External memory, 202 ... Instruction memory, 206 ... Control part, 208 ...
Internal memory address generation circuit, 210: working memory, 2
12 ... PCM tone generator address generation circuit, 214 ... parameter register, 216 ... head address register, 2
18 End address register, 220 Loop start address register, 222 Work register, 224 Ring buffer head address register, 226 Ring buffer end address register, 228 Reverb tap address register, 230 Address generating circuit for waveform data trace 232 ... first address selection circuit, 23
4: Last stage register, 236 ... + 1 incrementer, 2
38, a second address selecting circuit, 240, a digital reverb address generating circuit, 242, a base address counter, 244, an address adder, 246, an address subtractor, 247, an address adder, 248, an address selecting circuit, 250 Last stage register, 252: external memory address generation circuit, 254: DMA circuit, 256: external memory I / F, 258: product-sum operation circuit, 260: external input / output I / F, 900: tone generator, 920: audio signal Processing DSPs 900, 921: control unit, 922, 924 address generation circuit, 923: working memory, 925: DMA circuit, 926: external memory interface, 927: product-sum operation circuit, 940: external memory

Claims (13)

[Claims] An apparatus for performing desired data processing on arbitrary data to be processed, wherein the general-purpose apparatus performs predetermined arithmetic processing on the arbitrary data to be processed based on an input command. And first address generating means for generating an address for performing a memory access associated with the arithmetic processing for the specific data processing in the arithmetic processing means when performing the specific data processing. Data processing device. 2. The apparatus according to claim 2, further comprising: a second address generating unit configured to generate an address for performing a memory access associated with the arithmetic processing in the arithmetic processing unit relating to processing other than the specific data processing. And performing memory access based on the address generated by the first address generation unit and the address generated by the second address generation unit, and performing the desired data processing including the specific data processing. 2. The data processing device according to 1. 3. An internal memory means for storing arbitrary data in accordance with arithmetic processing in the arithmetic processing means, and an external memory interface means for performing memory access to an external memory means for storing data relating to the arithmetic processing. Further comprising: an internal memory address generating unit configured to generate an address for performing a memory access to the internal memory unit; and a second memory unit configured to perform a memory access to the external memory unit. And an external memory address generating means for generating an address of the external memory address, wherein the arithmetic processing means includes an address generated by the first address generating means, an address generated by the internal memory address generating means, and the external memory address. Based on the address generated by the generating means, Accessing the memory means and said external memory means, the data processing apparatus according to claim 2 for performing the desired data processing, including the specific data processing. 4. A processing procedure storing means for storing a processing procedure for performing a predetermined data processing on a series of time-series data, wherein the arithmetic processing means operates in accordance with the stored processing procedure. 3. The data processing apparatus according to claim 2, wherein a predetermined calculation process is performed on each data of said series of time-series data. 5. The series of time-series data is audio signal data, the predetermined data processing is arbitrary audio signal processing, and the specific data processing includes a trace processing of the audio signal data. The data processing apparatus according to claim 4, wherein the processing is processing. 6. The series of time-series data is PCM sound waveform data, the predetermined data processing is the PCM sound source processing, and the specific data processing is a trace processing of the PCM sound waveform data. The data processing device according to claim 5, comprising: 7. The first address generation means includes: parameter storage means for storing parameters defining the PCM audio waveform data; and trace processing address generation means for tracing the PCM audio waveform data. The data processing device according to claim 6. 8. The parameter storage means stores a head address, an end address, and a loop start address of the PCM audio waveform data, and the trace processing address generation means first stores the stored head address. The PCM audio waveform data is output after selecting and outputting the address while sequentially incrementing the address by one to the stored end address. If the PCM audio waveform data is waveform data including a loop portion, the stored address is further stored. 8. The data processing device according to claim 7, wherein addresses from a loop start address to the stored end address are repeatedly output in order. 9. The series of time-series data is PCM audio waveform data, the predetermined data processing is the PCM sound source processing, and the specific data processing includes a reverb processing of an audio signal. 6. The data processing device according to 5. 10. The reverb processing means for reverberating the audio signal, wherein the first address generation means includes parameter storage means for storing parameters for controlling the reverberation processing. A data processing device according to claim 1. 11. An external memory means for storing a series of PCM audio waveform data and arbitrary data relating to PCM sound source processing for the PCM audio waveform data, and the PCM audio data for the stored series of PCM audio waveform data. A data processing device that performs sound source processing and outputs baseband digital audio data; and a digital / analog conversion unit that converts the output baseband digital audio data into an analog audio signal. A processing procedure storing means for storing a processing procedure of the PCM sound source processing; and
An arithmetic processing means for performing a predetermined arithmetic processing on each data of the M audio waveform data; and a specific data processing included in the PCM sound source processing. A first address generating means for generating an address for performing a memory access; and
An internal memory means for temporarily storing arbitrary data; an internal memory address generating means for generating an address for performing a memory access to the internal memory means; and a memory access for performing a memory access to the external memory means External memory address generating means for generating an address of the external data storage means, and external memory interface means for performing memory access to the external data storage means based on the generated address. Accessing the internal memory and the external memory based on the address generated by the first address generator, the address generated by the internal memory address generator, and the address generated by the external memory address generator; , The PCM including the specific data processing PCM sound source device that performs sound source processing. 12. The PCM tone generator according to claim 11, wherein said specific data processing includes a waveform data trace processing. 13. The PCM tone generator according to claim 11, wherein said specific data processing includes reverb processing of audio data.