JPH02264509A - Digital filter - Google Patents

Abstract

PURPOSE:To obtain a digital filter with a low cost by supplying alternately a new data to two storage areas performing the function of the delay element group of the digital filter and updating the oldest data in each storage area. CONSTITUTION:A latch circuit 51 keeps supplying an input data for a write period to RAMs 51b, 52b. A controller 47a is provided with the address designation patterns of a number in response to the address capacity of RAMs A, B and its generating means. A new data held in the latch 51a is alternately fetched in the RAMs A, B in the data write routine and the new data is stored in the address of the oldest data stored in the RAMs A, B. The addition term between odd numbered data and even numbered data is used as the unit of addition in the integration value calculation, they are separated in advance into the odd and even number data and stored separately in the two RAMs. When corresponding data pair is read, the data transfer between the RAMs is not required.

Description

[Detailed description of the invention] Technical field The present invention relates to a digital filter.

Background Art A conventional example of a digital filter will be explained with reference to FIG.

Figure 3 shows the FIR (Finite
An example of an Impulse Re5ponse) filter is shown in which input data, which is a series of sampling data, is supplied to one end of delay elements 1 to 1o connected in series. Each delay element is constituted by, for example, a shift register, operates in synchronization with a clock of a data sampling period, and sequentially delays input data.

The output data of each delay element is supplied to coefficient multipliers 11 to 20, respectively, and multiplied by a coefficient value aO-ag. The multiplication outputs of the coefficient multipliers 11 to 20 are added by an adder 40 to become output data of the FIR filter.

When the impulse response characteristics of such an FIR filter are symmetrical as shown in FIG. 9, the count value of the multiplier shown in FIG. 3 is aQ "a9 + al - aQ + a2"
There is a relationship as follows: ``a71 a3'' aQ 1 a4-85. In order to utilize this to reduce the circuit scale,
As shown in FIG. 4, coefficient multipliers 16 to 20 are removed and adders 31 to 35 are used instead to reduce the number of multiplications to five, and the same calculation result is obtained. Note that corresponding parts in the FIR filters shown in FIGS. 3 and 4 are given the same reference numerals.

The FIR filter shown in FIG. 4 can be further simplified as shown in FIG. 5 by performing its arithmetic processing in a time-sharing manner. That is, the adders 31 to 35 in FIG.
It is replaced with a selector 41 that alternatively selects the outputs of delay elements 6 to 5, a selector 42 that alternatively selects the outputs of delay elements 6 to 10, and an adder 43 that adds the outputs of both selectors. Further, the coefficient multipliers 11 to 15 are replaced with a coefficient selector 44 and a multiplier 45. Each of the selectors 41, 42, and 44 has a selector for selecting 1 of n pieces of data (n-5 in the example of FIG. 5), and is synchronized with each other by a controller (not shown) at 1/n of the input data supply period. The selector switching operation is performed according to the following cycle. Multiplier 45 multiplies the output of adder 43 by the coefficient output from coefficient selector 44 to obtain a multiplied value, and supplies the multiplied value to integrator 40 . The multiplier 40 performs multiplication for each group of multiplication values sequentially multiplied by the coefficient aQ-a4.

Therefore, when data DO to D9 are held in delay elements 1 to 10, respectively, the output data Σ0 of the integrator 40 is ΣO" (D9 + Do) X ao + (D8 + D
l)Xal + (D7 +D2)Xaz + (
DB+D3)Xaz+(D5+Da)Xa4
Next, when new input data DIG is supplied and the held data is shifted, output data Σ1 becomes Σ+ −(DIG
+DI)xaQ+(D9+D2)Xal
+ (D8+D3)Xaz + (D7+Da)
It is expressed as Xa3 + (DB +D5)Xa4.

Similarly, Σ2. Σ3... is obtained.

FIG. 7 shows the data selected by the selectors 41 and 42, the combination of coefficients selected by the selector 44, and the integrated value Σn in such arithmetic processing.

Incidentally, the delay elements 1 to 10 and the selectors 41 and 42 of the FIR filter shown in FIG. 5 are usually constituted by memories 51 and 52 for reasons such as circuit cost.

An example of such a configuration is shown in FIG.

In the FIR filter shown in FIG. 6, parts corresponding to those shown in FIG. 5 are given the same reference numerals.
The input data is sent to a latch circuit 51a that temporarily holds the data.
and RAM 511).

The RAM 51 +) stores input data at a write address designated in response to a write command supplied from the controller 47. Further, the data stored in the read address specified in response to the read command is read and supplied to one input terminal of the adder circuit 43, and the memory 52 consisting of the latch circuit 52a and the RAM 52b. The RAM 52b stores data held by the latch circuit 52a at a write address specified in response to a write command supplied from the controller 47. Further, the data stored in the read address specified in response to the read command is read and supplied to the other input terminal of the adder 43.

The adder 43 supplies the addition result of the re-input data to one input terminal of the multiplier 45 . The other input terminal of the multiplier 45 has RO
Coefficient data is supplied from M46.

When the ROM 46 is supplied with a read address from the controller 47, it reads out the coefficient stored at the address and supplies it to the multiplier 45. The output of the multiplier 45 is integrated by the integrator 40 for each multiplication value of a series of coefficients aO-84, and is output as output data. Note that the operation timing of each circuit is controlled by a controller 47.

Next, the operation of the controller 47 will be explained with reference to FIG. The controller 47 is composed of an MPU, etc., and includes a RAM and a RAM that form two storage areas.
A data write routine to write data to RAMB (RAM51b) and RAMB (RAM52b), a data read routine to read data from RAMA and RAMB, and a coefficient setting routine to set a multiplication coefficient to the multiplier 45 are executed.

The data write routine moves the oldest data in RAM to the address in RAMB that stores the oldest data in terms of time, and writes new data to the address in RAM that stores the oldest data. Control movement.

The data read routine specifies a series of read addresses as a read order pattern for RAMA and B in order to sequentially read the new and old data pairs shown in FIG.

For example, as shown in FIG. 8(A) < RAMA address 0 to 4
In a state where data D9 to D5 are stored in RAMB addresses 0 to 4, and data D and -DJ are stored in RAMB addresses 0 to 4, respectively, controller 47 executes addressing pattern 0 to obtain integrated value Σ0. At this time, the data read routine sequentially specifies addresses O to 4 to RAMA. Further, in synchronization with this, addresses 0 to 4 are sequentially specified in the RAMB, and coefficients aQ-a4 are sequentially outputted to the ROM 46 in synchronization with the address specification. Then, the read pair of data is supplied to the adder 43, and the adder 43
Addition value (Dg + Do), (DB +D+)
, (D7 +D2), (D6+D3) and (D5
+D4) are output one after another. A multiplier 4 is added to this added value.
The coefficient aO specified by the coefficient setting routine by 5
-ad are respectively multiplied, and the multiplication value ao (D9 +D
O), at (Da +D+).

a2 (D7 +D2), aa (DB +D3)
, aa(Ds +Da) are sequentially obtained. Totalizer 40
integrates each multiplication value one after another and outputs the above-mentioned integrated value Σ0.

After data reading from RAMA and B is completed, a data writing routine is executed. The data write routine is R
The oldest data D5 in RAMA stored at address 4 of AMA is transferred to and stored in address O where the oldest data Do is stored in RAMB. Then, the latest data D+o is stored at address 4 of RAMA.

Then, the data arrays of RAMA and B become as shown in FIG. 8(B), which is equivalent to shifting the data held by delay elements 1 to 10 by one in FIG. 5.

The controller 47 executes addressing pattern 1 to obtain the data shown in FIG. 8(B) and obtain Σ]. That is, the data read routine sequentially supplies read addresses 4, 0, 1, 2°3 to RAMA, and
Address 1 is added to RAMB in response to address supply to MA.
．． 2. 3.4°0 is supplied sequentially. Also, adder 4
The coefficient ao+a is stored in the ROM 46 in accordance with the output timing of 3.
l+a2. Output a3 and a4 sequentially. the result,
An integrated value Σ1 is obtained at the output of the integrator 40.

After reading data from RAM A and B,
Execute the data write routine and read RAM address 31.
3. Move the stored data D6 to address 1 of RAMB, and store new data DI+ to address 3 of RAMA. Therefore, the data arrangement of RAMA and B is shown in Figure 8 (C
).

The controller 47 similarly executes the addressing patterns shown in FIGS. 8(C) to 8(E),
Integrated values Σ2 to Σ4 are obtained.

The addressing pattern 5 as shown in FIG. 8(F) when obtaining the integrated value Σ5 is equivalent to the data arrangement of RAMA and B when the data arrangement in RAMA and B completes one cycle to obtain the integrated value Σ0. Therefore, by the controller 47 repeating the execution of addressing patterns 0 to 4,
Integrated values Σ0...Σn... are obtained.

Generally, a number of addressing patterns are prepared depending on the address capacity of the memory.

By the way, in the conventional digital filter mentioned above, the circuit was simplified by replacing the - group delay elements with two memories, but the digital filter is used as a component of the circuit, and is even lower in cost. requested.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a low cost digital filter.

In order to achieve the above object, sample value storage means; writing means for sequentially writing a series of manually sampled values into the sample value storage means at a predetermined writing cycle; reading means for reading sample values from n addresses by reading at a readout cycle of 1/n or less; multiplication means for multiplying the read n sample values by a predetermined coefficient corresponding to the multiplied value; In the digital filter, the sample value storage means has first and second areas consisting of n address groups, and the writing means is configured to store the input sample value. The sample values of 1 is repeated in order to read sample values, and the multiplication means multiplies the read n sample values by a group of coefficients in an array corresponding to each of the readout order patterns.

Embodiment The present invention eliminates the need for data transfer between two storage areas, thereby eliminating the need for a data latch circuit, a data bus for coupling re-storage areas, a transfer control circuit, etc.

FIG. 1 shows an embodiment of the present invention, and parts corresponding to those of the FIR filter shown in FIG. 6 are given the same reference numerals, and explanations of these parts will be omitted.

In FIG. 1, latch circuit 51. Input data is supplied to a at a predetermined sampling period. Latch circuit 51
a is a RAM that holds this input data during the write cycle.
51b and 52b.

The controller 47a controls data writing and data reading of the RAMs 51b and 52b. Also, controller 4
Reference numeral 7a controls the operation timing of each circuit using a timing clock (not shown) or the like to synchronize the operations. R.A.
The two data read from M51b and M52b are supplied to both input ends of adder 43. Other configurations are similar to the conventional example.

Next, the operation of the controller 47a will be explained with reference to FIG.

First, the controller 47a controls the RAM (RAM5
lb) and RAMB (RAM52b); a data read routine that reads data from RAMA and RAMB; and a coefficient setting routine that sets a multiplication coefficient in the multiplier 45. Further, the controller 47a has a ROM containing a number of addressing patterns corresponding to the address capacity of RAM and B.
It has an addressing pattern generating means consisting of an up counter, a down counter, etc. stored in the control program or formed on the control program. For example, as shown in Figure 2 (RA
When the address capacity of each of MA and B is 5, addressing patterns O to 9 are prepared.

The data write routine causes RAM and B to take in new data held in the latch 51a alternately, and each R
The oldest data of AM is stored at the stored address.

In this way, as shown in FIG. 7, since the integrated value calculation uses the adder for odd-numbered data and even-numbered data as the addition unit, the odd-numbered data and even-numbered data are separated in advance and stored in two RAMs. By storing data separately and reading out corresponding data pairs, data transfer between RAMs becomes unnecessary, and data reading can be simplified.

The data read routine is the sum of products Σ0...Σn...
In order to calculate the data pairs shown in FIG. 7, the corresponding readout order patterns are sequentially read out from a series of address designation patterns to designate the readout addresses of RAMA and B.

For example, as shown in FIG. 2A, even-numbered data Do, D2 . D4゜D9. DB is stored, and odd-numbered data D, , D3 . With D5°Dy and D9 stored, the controller 47a executes the addressing pattern O to calculate the integrated value Σ0.

When addressing pattern O is executed, the data read routine sequentially supplies addresses 0-4 to RAMA. In addition, addresses 4 to 0 are sequentially supplied to RAMB in synchronization with the supply of addresses to RAMA, and a coefficient sequence aO+ al + a of an arrangement corresponding to the reading order pattern of this data is generated.
d + a31 al is sequentially output to the ROM 46.

Then, the data pairs that RAMA and B supply to the adder 43 are Do and D9. D2 and Dy, D4 and D5. DB and D3. DB and Dl, and the output of the adder 43 is (D
o +Ds), (D2 +Dy), (
Da + Ds), (DB +03),
(Da+D1) is obtained. Multiplier 4 of these addition outputs
Multiplying coefficient ao + a2 + a in synchronization with the supply to 5
4+a3+al is supplied to the multiplier 45, so the multiplier 45 calculates (Do +D9) ao, (D2
+D7)al, (D4+Ds)aa, (DB
+Dt)a3°(Da +D+)al are sequentially output. Therefore, the integrated value Σ0 of the integrator 40 is Σo = (Do +D9) ao + (Da −
+-Dl )al + (D2 +D7)a2+ (
Do +D3) a3 + (DJ +D5) a
4, which is equivalent to Σ0 shown in FIG. 7(A).

After completing the data read routine, the controller 47a executes the data write routine. In this data write routine, the latest data Dll held in the latch 51a is written to address 0 where the oldest data DO is stored in RAMA. Therefore, the data arrays of RAMA and B are as shown in the second (B).

The controller 47a uses the addressing pattern 1 to obtain the integrated value Σ1 based on the data shown in the second (B).
Execute. That is, the data read routine is executed and the read addresses 1, 2, 3, 4, . 0 is sequentially supplied, and in synchronization with this, the read addresses 4, 3,
2.1.0. Also, coefficients al, a3 . a2. ao
are output sequentially. As a result, the integrated degree value Σ1 is obtained at the output of the integrator 40.

When the execution of the data read routine is finished, the data write routine is executed and the oldest data D1 in RAMB is written.
The latest data DI+ held in the latch 51a is written to the address 0 where is stored.

Therefore, the data arrangement of RAMA and B is as shown in FIG. 2(C).

The controller 47a is operated in the same manner as above in FIGS.
Addressing patterns 2 to 5 shown in FIG. 2(F) are executed to obtain integrated values Σ2 to Σ5. Although only part of the pattern is shown in FIG. 2, 10 addressing patterns (0 to 9) are prepared corresponding to the RAM and B storage capacities of 10. When five pieces of new data are supplied to each RAMA and B from the data array state shown in FIG. 2(A), the data arrays of RAMA and B go around and change to
Since it becomes equivalent again to the data array shown in A), by repeating the execution of addressing patterns 0 to 9, integrated values Σ0...Σn... are obtained.

Generally, if the address of each RAMA and B is n, 2n types of addressing patterns are required.
As shown in Figures (A) to (F), the read addresses of RAMA and B can be easily obtained by alternately incrementing an addition counter and a subtraction counter each time new data is supplied. Furthermore, the write addresses of RAMA and B can be easily obtained by alternately incrementing two counters each time new data is supplied.

In this way, data transfer between RAMA and RAM8 is unnecessary, and the latch circuit, data bus, and R
Control circuits and the like for data transfer between AMs are reduced.

Although the embodiment has been described using an even-order filter, it is also applicable to an odd-order filter exhibiting an impulse response characteristic as shown in FIG. 10 or a frequency response characteristic as shown in FIG. 11. Note that in FIG. 11, fs represents the sampling frequency, fc represents fs/4, and fd represents the passband width. In such a case, the number of read addresses between RAMA and RAMB differs by 1, but as mentioned above, RA
All that is required is to alternately write new data to MA and RAMB, update the oldest data, and read data according to the data read order pattern corresponding to the data arrangement of RAMA and RAMB.

As described in the detailed description of the invention, in the digital filter of the present invention, new data is alternately supplied to the two storage areas that function as the delay element group of the digital filter, and the oldest data in each storage area is updated. This configuration eliminates the need for data transfer between two storage areas, which is preferable because the configuration of the device becomes simpler and costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 (
A) to (F) are diagrams for explaining the address control operation of the controller 47a, FIG. 3 is a block diagram showing a configuration example of an FIR filter, and FIG. 4 is a diagram for explaining the address control operation of the controller 47a.
FIG. 5 is a block diagram showing an example of a simplified IR filter; FIG. 5 is a block diagram showing an example of time-sharing configuration of the FIR filter shown in FIG. 4; FIG. F
FIGS. 7(A) to 7(F) are block diagrams showing an example of an IR filter configured using RAM, and the FI filter shown in FIG.
Diagrams for explaining the operation of the R filter, FIG. 8(A) ~
(F) is a diagram for explaining the address control operation of the controller 47 shown in FIG. 6; FIGS. 9 and 10 are characteristic diagrams showing examples of impulse response characteristics of the filter;
FIG. 1 is a characteristic diagram showing an example of frequency response characteristics of a filter. Explanation of symbols of main parts 40...Integrator 43...Adder 45...Multiplier

Claims (1)

[Scope of Claims] Sample value storage means; writing means for sequentially writing a series of input sample values into the sample value storage means at a predetermined writing cycle; /
a reading means for reading sample values from n addresses by reading with a reading period of n or less; a multiplication means for multiplying the read n sample values by a predetermined coefficient corresponding to the multiplied value; a digital filter that includes an integrating means for integrating each value, the sample value storage means having first and second areas consisting of n address groups, and the writing means for integrating the input sample values. The sample values of the first
and writing so as to replace the oldest sample value in the second area, and the reading means reads the sample value by repeatedly executing one of n sets of read order patterns from the first and second areas. , the multiplication means reads n
A digital filter, wherein the sample values are multiplied by a group of coefficients in an array corresponding to each of the readout order patterns.