JP3177358B2 - Digital filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter used for digital audio equipment and the like.
The present invention relates to a separation filter that separates data into a plurality of components using a QMF (Quadrature Mirror Filter).

[0002]

2. Description of the Related Art As typical digital filters, a FIR (Finite Impulse Response) type and an IIR (Inline
finite Impulse Response) type. The FIR type is a method in which the influence of the impulse response of the input data on the output data is limited to a certain period, and the IIR type is a method in which the impulse response of the input data on the output data has an infinite effect.

[0003] The FIR digital filter is configured to obtain output data Y (n) by convolution of input data X (n) and an impulse response as shown in equation (1).

[0004]

(Equation 1)

[0005] Here, h (k) is a filter coefficient, and N is the number of taps. Then, when Expression (1) is Z-transformed,

[0006]

(Equation 2)

[0007] From this equation (2),

[0008]

(Equation 3)

Thus, the frequency response can be understood. And ω
= 2πk / N, equation (3) becomes

[0010]

(Equation 4)

## EQU1 ## This equation (4) can be regarded as an equation of a discrete Fourier transform (DFT). Therefore, the filter coefficient h (k) is obtained by inversely transforming the frequency characteristic given by the equation (4) (IDFT: Invers
e Discrete Fourier Transform). Figure 1 shows the configuration of a standard FIR digital filter
0 is shown.

A plurality of delay elements 1 connected in series are constituted by shift registers, and sequentially delay input data X (n) by a predetermined period (T). A plurality of multipliers 2 connected to the output side of each delay element 1 multiply the output of each delay element 1 by a filter coefficient h (k). This allows
Convolution processing with the impulse response is performed on the input data X (n). The sum adder 3 outputs the output of each multiplier 2,
That is, the sum of the outputs of the delay elements 1 multiplied by the predetermined filter coefficient h (k) is calculated, and output data Y (n) is output. Therefore, the operation according to equation (1) has been executed.

Such an FIR digital filter is
There is a problem that the circuit scale increases as the number of taps N increases. Therefore, as shown in FIG. 11, an FIR digital filter of a stored program type has been proposed. The RAM 11 sequentially stores input data X (n) input in time series. ROM 12
A plurality of filter coefficients h (k) are stored, and a specific filter coefficient h (k) is read out and output corresponding to the value of k which increases in each step. Note that k is equal to k shown in Expression (1). The multiplier 13 multiplies the input data X (nk) read from the RAM 11 by the filter coefficient h (k) read from the ROM 12. The accumulator 14 includes an adder 15 and a first register 16, and accumulates the multiplication result of the multiplier 13. That is, the output of the multiplier 13 and the output of the register 16 are added by the adder 15, and the addition result is stored in the register 16 again, so that the multiplication results of the multiplier 13 are sequentially added. The second register 17 takes in the cumulative addition result output from the accumulator 14 and outputs it as output data Y (n).

In this FIR type digital filter, RA
By sequentially reading the input data X (n) and the filter coefficient h (k) from the M11 and the ROM 12 and repeating the product-sum operation, the operation according to the equation (1) is executed to obtain the output data Y (n). . Therefore, even if the number of taps N increases, the circuit scale does not increase. By the way, with respect to the FIR digital filter having the _first filter coefficient h ₁ (n),

[0015]

(Equation 5)

The second filter coefficient h given by
_The FIR digital filter having ₂ (n) is called a mirror filter because of its frequency response. The relationship of Z conversion in such a mirror filter is as follows.

[0017]

(Equation 6)

## EQU1 ## Here, considering the frequency response,

[0019]

(Equation 7)

Therefore, equation (6) is

[0021]

(Equation 8)

## EQU1 ## This indicates that the frequency response of the mirror filter is symmetric at π / 2. Here, since π / 2 is ４ of the sampling period, this mirror filter is a QMF (Quadrature Mirror).
Filter). About this QMF, IEE Transactions on Acoustic Speech and Signal Processing,
IESP, Vol. 32, No. 3, June 1984, (IEEE
Trans. Acoust., Speech, Signal Process., Vol.ASSP-32,
No. 3, June 1984), pages 522 to 531.

In the separation filter that separates the frequency components by the above-described QMF, the equations (9) and (1)
As shown in 0), the input data X (n) and the convolution of the impulse response, by their addition or subtraction processing, the separation data in the input data X (n) 2 two output data Y _a (n) , Y _b (n).

[0024]

(Equation 9)

[0025]

(Equation 10)

FIG. 12 shows a separation filter for performing such band separation. Each delay element 21 connected in series
Delays the input data X (n) sequentially for a certain period (T). A multiplier 22 connected to the output side of the even-numbered delay elements 21 multiplies the output of each delay element 21 by a filter coefficient h (2k) and inputs the result to a sum adder 23. A multiplier 24 connected to the output side of the odd-numbered delay elements 21 multiplies the output of each delay element 21 by a filter coefficient h (2k + 1) and inputs the result to the sum adder 25. Thereby, the input data X (n)
And the impulse response are convolved. The sum adder 23 calculates the sum of the outputs of the respective multipliers 22, that is, the outputs of the respective delay elements 21 multiplied by a predetermined filter coefficient h (2k), and outputs data An. On the other hand, the sum adder 25
Calculates the sum of outputs of the delay elements 21 multiplied by a predetermined filter coefficient h (2k + 1), and outputs data Bn. Subtractor 26, from the data An for total adder 23 outputs, subtracts the data Bn of total adder 25 outputs, as output data Y _a (n). Further, the adder 27
The data An output from the sum adder 23 and the sum adder 2
5 adds the data Bn of outputting, output data Y _b (n)
Output as

[0027]

However, FIG.
(2) has a problem that the circuit scale increases as the number of taps increases. In particular, when one input data is separated into three or more components, it is necessary to multiplex the above-described separation filters, and the circuit scale is further increased.

It is therefore an object of the present invention to provide a separation filter that does not increase the circuit scale even when the number of taps increases, and to multiplex the filters without increasing the circuit scale.

[0029]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a first means is a memory for storing input time-series data, and a memory for storing input time-series data read from this memory. A multiplier for multiplying the series data by a predetermined filter coefficient; an accumulator for sequentially accumulating the multiplication results of the multiplier; a pair of registers for alternately receiving the accumulation results of the accumulator; Add or subtract the two accumulative addition results,
And an adder / subtractor that outputs the operation value as two output time-series data that becomes separated data of the input time-series data.

The second means is a memory for storing the input time-series data, a multiplier for multiplying the input time-series data read from the memory by a predetermined filter coefficient, and sequentially accumulating the multiplication results of the multiplier. Accumulator, a pair of registers for alternately taking the accumulative result of the accumulator, and adding or subtracting the two accumulative results taken out from the pair of registers, and using the operation value as separated data of input time-series data. An adder / subtractor that outputs two output time series data, and a selector that replaces the output time series data output from the adder / subtracter with the input time series data and inputs the data to the memory.

The third means is a memory for storing the input time-series data, a multiplier for multiplying the input time-series data read from the memory by a predetermined filter coefficient, and sequentially accumulating the multiplication results of the multiplier. Accumulator, a pair of registers for alternately taking the accumulative result of the accumulator, and adding or subtracting the two accumulative results taken out from the pair of registers, and using the operation value as separated data of input time-series data. An adder / subtracter that outputs two output time-series data, a first selector that replaces the output time-series data output from the adder / subtractor with input time-series data and inputs the data to the memory, The time-series output data input to the memory and read after a predetermined period elapses is output to the time-series output data from the adder / subtractor. It is characterized by comprising a second selector for outputting the replaced data.

[0032]

According to the first aspect of the present invention, the time-series input data read from the memory is multiplied by a predetermined filter coefficient, and the multiplied value is cumulatively added by the accumulator. Then, the accumulative values of the accumulator are alternately fetched into a pair of registers, and the accumulative values fetched into each register are added and subtracted from each other, thereby obtaining time-series output data separated into two components.

According to the second means, the selector is switched, and the time-series output data obtained in the same manner as in the first means is stored again in the memory. The time-series output data stored in the memory is treated as new time-series input data, and multiplication, accumulation, and addition / subtraction of filter coefficients are performed again. Therefore, multiplex separation processing is performed on the time-series input data, and time-series output data separated into three or more components is obtained.

According to the third means, the first selector is switched, and the output time-series data obtained in the same manner as in the first means is stored in the memory again. The time-series output data stored in the memory is treated as new time-series input data as in the second means, and the second selector is switched to be directly output from the memory. Accordingly, it is possible to delay the output of the output time-series data for a desired period at the same time as performing the multiple arithmetic processing on the time-series input data.

[0035]

FIG. 1 shows a separation filter according to the present invention. R
The AM 31 sequentially stores input data X (n) input in time series. The ROM 32 stores a filter coefficient h (k) in advance, and reads out and outputs a specific filter coefficient h (k) corresponding to the value of k that increases for each step.
Note that k is equal to k shown in the above equations (9) and (10). The multiplier 33 multiplies the input data X (nk) read from the RAM 31 by the filter coefficient h (k) read from the ROM 32. The accumulator 34 includes an adder 35 and a first register 36,
The result of multiplication by the multiplier 33 is cumulatively added. That is, the adder 35
Adds the output of the multiplier 33 and the output of the register 36,
By storing the addition result in the register 36 again, the outputs from the multipliers 33 are sequentially added. The second register 37 and the third register 38 store the accumulator 3
4 are alternately fetched and output at a predetermined timing. For example, the cumulative addition result (An) output at the odd number from the accumulator 34 is loaded into the second register 37, and the cumulative addition result (Bn) output at the even number is loaded into the third register 38. The adder / subtractor 39 subtracts and adds the cumulative addition results (An, Bn) taken into the two registers 37, 38. The fourth register 40 stores the subtraction result (An-Bn) of the adder / subtractor 39.
And the addition result captures (An + Bn), outputs the respective data Y _a (n), and outputs as a Y _b (n).

FIG. 2 shows the operation of the above separation filter.
This will be described according to the timing chart of FIG. Here, the number of taps is set to N = 4. Equation assuming the number of taps N = 4
When calculating (9) and equation (10), for equation (9),

[0037]

[Equation 11]

Then, with respect to equation (10),

[0039]

(Equation 12)

## EQU4 ## In FIG. 2, input data X (0)
Although the input of .about.X (7) is omitted, it is input in the same manner as the input data X (8), X (9), etc., and written into the RAM 31. When n = 4, first, the input data X (8) is read from the RAM 31, and when the filter coefficient h (0) is read from the ROM 32, the multiplier x multiplies these by the multiplier 33. It is supplied to an accumulator 34. At this time, the data of the accumulator 34 has been cleared, and the result of multiplication of the input data X (8) and the filter coefficient h (0) becomes the first data as A1 = h (0) .X (8). It is stored in the register 36. Subsequently, input data X (6) is sequentially input from the RAM 31.
X (4) and X (2) are read out, and filter coefficients h (2), h (4) and h (6) are read out sequentially from the ROM 32, and each is multiplied by the multiplier 33. Are sequentially supplied to the accumulator 34. In the accumulator 34, the input multiplication results are cumulatively added, and A2 = h (2) .X (6) + A1 A3 = h (4) .X (4) + A2 A4 = h (6) .X (2) + A3 Are sequentially stored in the first register 36. The finally stored data of A4 = h (0) .X (8) + h (2) .X (6) + h (4) .X (4) + h (6) .X (2) is stored in the accumulator 34. And is stored in the second register 37.

Similarly, the input data X (7)
Is read out, and when the filter coefficient h (1) is read out from the ROM 32, the multiplier 33 multiplies the filter coefficient h (1) and supplies the multiplication result to the accumulator 34.
At this time, the data of the accumulator 34 has been cleared, and the multiplication value of the input data X (7) and the filter coefficient h (1) becomes the first data as it is as B1 = h (1) .X (7). It is stored in the register 36. Subsequently, input data X (5) is sequentially input from the RAM 31.
X (3) and X (1) are read, and at the same time, filter coefficients h (3), h (5) and h (7) are read sequentially from the ROM 32, and the multiplication results are sequentially supplied to the accumulator 34. . Therefore, the data of B2 = h (3) .X (5) + B1 B3 = h (5) .X (3) + B2 B4 = h (7) .X (1) + B3 are sequentially stored in the first register 36. You. The finally stored data of B4 = h (1) .X (7) + h (3) .X (5) + h (5) .X (3) + h (7) .X (1) is stored in the accumulator 34. , And stored in the third register 38.

The data A4 and data B4 are supplied from the second register 37 and the third register 38 to the adder / subtracter 39.
After the data A4 and the data B4 are added,
Data B4 is subtracted from data A4. The operation result of the adder / subtractor 39 is stored in the fourth register 40, and the addition result, that is, A4 + B4 = h (6) .X (2) + h (4) .X (4) + h (2) .X (6 ) + H (0) · X (8) + h (7) · X (1) + h (5) · X (3) + h (3) · X (5) + h (1) · X (7) is the output data Y _b (4) and similarly output the subtraction result, that is, A4-B4 = h (6) .X (2) + h (4) .X (4) + h (2) .X (6) + h (0 ) .X (8) -h (7) .X (1) -h (5) .X (3) -h (3) .X (5) -h (1) .X (7) is the output data Y _a Output as (4). As a result, equation (1)
This means that the arithmetic processing represented by 1) and Expression (12) has been performed.

The addresses given to the RAM 31 and the ROM 32 are generated by an address generation circuit as shown in FIG. The preset counter 51 counts up by a first clock CK1 corresponding to a series of operation cycles of the accumulator 34, and generates preset data PD which is incremented each time the accumulator 34 completes the cumulative addition operation. After the preset data PD is preset, the first loop counter 52 outputs a second clock C that matches the operation cycle of the multiplier 33.
The address data A is counted up by K2 and incremented each time the multiplication operation of the multiplier 33 is completed.
Generate D1. This address data AD1 is stored in RAM
The address 31 is designated, and predetermined input data X (n) is read. The second loop counter 53 is reset by the reset clock RC that matches the cycle of the first clock CK1, then is counted up by the second clock CK2, and is incremented every time the multiplication operation of the multiplier 33 is completed. Address data AD2. The address data AD2 specifies an address of the ROM 32 and reads out a predetermined filter coefficient h (n). Thus, the address data AD1 supplied to the RAM 31 is
While the accumulator 34 shifts by one each time the accumulator operation is completed, the address data AD2 supplied to the ROM 32 repeats the same address each time the accumulator 34 performs the accumulator operation. Therefore, R
The same filter coefficient h (n) is repeatedly read from the OM 32, and the input data X (n) shifted one by one from the RAM 31 is read.

As described above, in the separation filter using QMF, the multiplication process of the input data X (n) and the filter coefficient h (n) is repeated by the multiplier 33, and the multiplication result is accumulated by the accumulator 34. Is added. As a result, the operation according to the above-described equations (11) and (12) is executed, and two output data Y (Y) are input data X (n).
_a (n) and Y _b (n) are obtained. Therefore, it is not necessary to increase the circuit scale even when the number of taps N is increased.

Next, the multiplexing of the separation filter will be described. Separated one input data X (n) to the three components, the three output data Y _a (n), Y _b (n), in the case of obtaining a Y _c (n), using two separate filters It is configured to perform two separation processes. For example, as shown in FIG. 3, two output data Y _c of QMF 1 receiving input data X (n)
(n), Z by an input data one the QMF2 of (n), finally the three output data _{Y a (n), Y b} (n), Y
_c (n).

In such a multiplexed separation filter, according to the equations (9) and (10), first, the input data X (n) is

[0047]

(Equation 13)

The following arithmetic processing is performed, and the output data Z (n) is

[0049]

[Equation 14]

The following arithmetic processing is performed. FIG.
In the case of the separation filter shown in FIG. 5, by adding one selector 41 as shown in FIG. 5, the same arithmetic processing as in the case where the separation filter is multiplexed becomes possible. That is, R
A selector 41 is provided on the input side of the AM 31 so that the input data X
By switching between (n) and the output data Z (n) output from the adder / subtractor 39 and storing them in the RAM 31, the output data Z (n) is handled again as input data. Therefore, two output data Y _c (n) and Z (n) are obtained by the first arithmetic processing on the input data X (n),
Two additional output data Y _a by a second operation to output data Z of the (n) (n), Y b (n) is obtained.

For the above separation filter, the number of taps N
= 2 will be described with reference to the timing chart of FIG. First, assuming the number of taps N = 2, the above equation (1
When calculating 3) and equation (14),

[0052]

(Equation 15)

Is as follows. Here, m = 2n (when m is an even number) or m = 2n-1 (when m is an odd number). Also, when calculating the above equations (15) and (16),

[0054]

(Equation 16)

Is as follows. In FIG. 6, input data X (0)
-X (7) and output data Z (1) -Z (3) are not shown in FIG.
(8), X (9) and output data Z (4)
It is stored in AM31. When m = 4, first, RAM
The input data X (8) is read out from the
When the filter coefficient h (0) is read from the counter 32, they are multiplied by a multiplier 33, and the multiplication result is stored in the accumulator 3.
4 is supplied. At this time, the data of the accumulator 34 has been cleared, and the result of multiplication of the input data X (8) and the filter coefficient h (0) is directly stored in the first register as data A1 = h (0) .X (8). 36. Subsequently, the input data X (6) is read from the RAM 31 and the filter coefficient h (2) is read from the ROM 32, each is multiplied by the multiplier 33, and the multiplication result is supplied to the accumulator. In the accumulator 34, the input multiplication results are cumulatively added, and the data of A2 = h (2) .X (6) + A1 = h (2) .X (6) + h (0) .X (8) is the first data. , And output from the accumulator 34 and stored in the second register 37.

Similarly, the input data X (7)
Is read out, and when the filter coefficient h (1) is read out from the ROM 32, the multiplier 33 multiplies the filter coefficient h (1) and supplies the multiplication result to the accumulator 34.
At this time, the data of the accumulator 34 has been cleared, and the result of multiplication of the input data X (7) and the filter coefficient h (1) is represented as B1 = h (1) · X (7) in the first register. 36. Subsequently, the input data X (5) is read from the RAM 31 and the filter coefficient h (3) is read from the ROM 32, and the respective multiplication results are sequentially supplied to the accumulator. Therefore, the data of B2 = h (3) .X (5) + B1 = h (3) .X (5) + h (1) .X (7) is stored in the first register 36 and output from the accumulator 34. And stored in the third register 38.

Then, the data A 2 and the data B 2 are supplied from the second register 37 and the third register 38 to the adder / subtractor 39.
After the data A2 and the data B2 are added,
Data B2 is subtracted from data A2. The addition result of the adder / subtractor 39, that is, the data of A2 + B2 = h (2) .X (6) + h (0) .X (8) + h (3) .X (5) + h (1) .X (7) , And stored in the fourth register 40 and output as output data Y _c (4). Also, the subtraction result of the adder / subtractor 39, that is, A2-B2 = h (2) .X (6) + h (0) .X (8) -h (3) .X (5) -h (1) .X (7) is stored in the RAM 31 from the selector 41 as new input data Z (4). As a result, the arithmetic processing represented by Expression (17) and Expression (18) is performed.

When m = 4, n = 2. When the input data Z (4) is read from the RAM 31 and the filter coefficient h (0) is read from the ROM 32 at the same time, they are multiplied by each other by the multiplier 33, and the multiplication result is obtained. Is supplied to the accumulator 34. The accumulator 34 has the data cleared,
The multiplied value of the input data Z (4) and the filter coefficient h (0) is stored in the first register 36 as it is as C1 = h (0) .Z (4). Subsequently, the input data Z (2) is read from the RAM 31 and the filter coefficient h (2) is read from the ROM 32. Each of the filter coefficients h (2) is multiplied by the multiplier 33, and the multiplication result is supplied to the accumulator. In the accumulator 34, the input multiplication results are cumulatively added, and data of C2 = h (2) .Z (2) + C1 = h (2) .Z (2) + h (0) .X (4) is stored in the first data. , And output from the accumulator 34 and stored in the second register 37.

Similarly, the input data Z (3)
Is read out, and when the filter coefficient h (1) is read out from the ROM 32, the multiplier 33 multiplies the filter coefficients h (1) by one another. The result of the multiplication is supplied to the accumulator 34. At this time, the accumulator 34 has cleared the data, and the multiplied value of the input data Z (3) and the filter coefficient h (1) becomes the first register as data of D1 = h (1) · Z (3). 36. Subsequently, the input data Z (1) is read from the RAM 31 and the filter coefficient h (3) is read from the ROM 32, and the multiplication results are sequentially supplied to the accumulator. Therefore, the data D2 = h (3) .Z (1) + D1 = h (3) .Z (1) + h (1) .Z (3) is stored in the first register 36 and output from the accumulator 34. And stored in the third register 38.

The data C2 and data D2 are supplied from the second register 37 and the third register 38 to the adder / subtractor 39.
After the data C2 and the data D2 are added,
Data D2 is subtracted from data C2. The operation result of the adder / subtractor 39 is stored in the fourth register 40, and the addition result,
That, C2 + D2 = h (2 ) · Z (2) + h (0) · Z (4) + h (3) · Z (1) + h (1) · Z (3) is output data Y _b (2) as an output Similarly, the subtraction result, that is, C2-D2 = h (2) .Z (2) + h (0) .Z (4) -h (3) .Z (1) -h (1) .Z ( 3) is output as the output data Y _a (2). As a result, equation (1)
This means that the arithmetic processing represented by 9) and Expression (20) has been performed.

The filter coefficient h (n) by which the input data Z (n) is multiplied may be different from the filter coefficient h (1) by which the input data X (n) is multiplied. . In the separation filter multiplexed as described above, the selector 41 is compared with the separation filter shown in FIG.
Only, the increase in circuit scale due to multiplexing is extremely small.

[0062] Incidentally, in the separation filter obtained by multiplexing a plurality of output data _{Y a (n), Y b} (n), a problem the output timing of the Y _c (n) does not match occurs. That is obtained by twice arithmetic processing output data Y _a (n),
Y _b (n) and output data Y obtained by one operation
The output timing with _c (n) will be shifted. To compensate for such displacement of the output timing, as shown in FIG. 7, by delaying the output data Y _c (n), the output data _{Y a (n), Y b} (n), Y c ( The output timing of n) is matched.

In the separation filter shown in FIG. 5, by providing the second selector 42 in addition to the first selector 41, the delay processing on the output data Y _c (n) becomes possible. That is, the input data X (n) is input to the RAM 31 input side.
And a first selector 41 for switching between data output from the adder / subtractor 39 and a second selector for switching data read from the RAM 31 and data output from the adder / subtractor 39 at the input side of the fourth register 40. Selector 42 is provided. Thereby, the adder / subtractor 39
The output data Y _c (n) output from the RAM 31 is temporarily stored in the RAM 31, read out from the RAM 31 at a predetermined timing, and taken in from the second selector 42 to the fourth register 40. Therefore, the RAM 31 functions as a delay circuit, and the output data Y _a (n) and Y _b (n) obtained by the second operation are output data Y _c (n) obtained by the one operation. Are output at the same timing.

For the above separation filter, the number of taps N
= 2 will be described with reference to the timing chart of FIG. In FIG. 9, input data X (0) to X (7)
And the input of output data Z (1) to Z (3) is omitted, but RA is input in the same manner as input data X (8) and X (9).
It is stored in M31. The arithmetic processing itself executed here is the same as the arithmetic processing shown in FIG.
They follow the above-mentioned equations (19) and (20), respectively.

When m = 4, the input data X
(8) and X (6) are sequentially read out, and simultaneously when the filter coefficients h (0) and h (2) are read out from the ROM 32, they are multiplied by the multiplier 33, and the multiplication result is stored in the accumulator 34.
Supplied to In the accumulator 34, the multiplication results of the multiplier 33 are cumulatively added, and finally, A2 = h (2) .X (6) + A1 = h (2) .X (6) + h (0) .X (8) Data is stored in the first register 36, output from the accumulator 34, and stored in the second register 37. Similarly, input data X (7), X (5)
Are read out sequentially, and when the filter coefficients h (1) and h (3) are read out from the ROM 32, they are multiplied by the multiplier 33, and the multiplication result is supplied to the accumulator. In the accumulator 34 which has been reset, the multiplication results of the multiplier 33 are cumulatively added, and finally, B2 = h (3) .X (5) + B1 = h (3) .X (5) + h (1) .X ( 7) is stored in the first register 36, output from the accumulator 34, and stored in the third register 38.

After that, the output data Y _c (2) stored in the past is read from the RAM 31 and the second selector 4
2 and stored in the fourth register 40. And
Data A2 and data B2 are input to the adder / subtractor 39 from the second register 37 and the third register 38, and the data A2
After adding 2 and data B2, data B2 is subtracted from data A2. The addition result of the adder / subtractor 39, that is, the data of A2 + B2 = h (2) .X (6) + h (0) .X (8) + h (3) .X (5) + h (1) .X (7) , Output data Y _c (4) from the first selector 41 to the RAM 31 once. The output data Y _c (4) stored here is read out after a predetermined period, and stored in the fourth register 40 through the second selector 42. Also, the subtraction result of the adder / subtractor 39, that is, A2-B2 = h (2) .X (6) + h (0) .X (8) -h (3) .X (5) -h (1) .X (7) is also stored in the RAM 31 from the selector 41 as new input data Z (4).

Further, the input data Z
(4) and Z (2) are sequentially read out, and at the same time, when the filter coefficients are read out from the ROM 32 in the order of h (0) and h (2), the multiplier 3
The result is supplied to the accumulator 34. In the accumulator 34, the multiplication results of the multiplier 33 are cumulatively added, and data of C2 = h (2) · Z (2) + C1 = h (2) · Z (2) + h (0) · X (4) The data is stored in the first register 36, output from the accumulator 34, and stored in the second register 37. Similarly, input data Z (3), Z (1)
Are sequentially read out, and when the filter coefficients h (1) and h (3) are read out from the ROM 32 in response thereto, they are multiplied by each other in a multiplier 33, and the multiplication result is supplied to an accumulator. At this time, the data is cleared in the accumulator 34, and the multiplication results of the multiplier 33 are cumulatively added, and D2 = h (3) · Z (1) + D1 = h (3) · Z (1) + h (1 ) .Z (3) is stored in the first register 36, output from the accumulator 34, and stored in the third register 38.

Then, the data C 2 and the data D 2 are supplied from the second register 37 and the third register 38 to the adder / subtractor 39.
After the data C2 and the data D2 are added,
Data D2 is subtracted from data C2. The operation result of the adder / subtractor 39 is stored in the fourth register 40, and the addition result,
That, C2 + D2 = h (2 ) · Z (2) + h (0) · Z (4) + h (3) · Z (1) + h (1) · Z (3) is output data Y _b (2) as an output Similarly, the subtraction result, that is, C2-D2 = h (2) .Z (2) + h (0) .Z (4) -h (3) .Z (1) -h (1) .Z ( 3) is output as the output data Y _a (2). Here, in the fourth register 40, the output data Y _c (4) obtained by the previous operation processing is stored first, and the output data Y _c
a (2), to be output together with Y _b (2).

In the multiplexed separation filter to which the delay function is added as described above, only two selectors 41 and 42 are added as compared with the separation filter shown in FIG. Is very small. In the above embodiment, one input data X (n)
Two or three output data _{Y a (n), Y b} (n), Y
_{Although the} case where _c (n) is obtained has been exemplified, the data output from the adder / subtractor 39 is repeatedly stored in the RAM 31 and multiplied by the filter coefficient h (n), so that the input data X (n) becomes 4 It is also possible to separate them into more than one component.

[0070]

According to the present invention, even when the number of taps is increased, the arithmetic processing can be performed without increasing the circuit scale. Further, even when filters are multiplexed and three or more output data are obtained from one input data, it is possible to cope by adding a selector, so that an increase in circuit scale can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a digital filter according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of an address generation circuit.

FIG. 4 is a block diagram showing a configuration for multiplexing QMF.

FIG. 5 is a block diagram showing a second embodiment of the digital filter of the present invention.

FIG. 6 is a timing chart for explaining the operation of the second embodiment.

FIG. 7 is a block diagram showing a configuration in which a QMF is multiplexed and a delay circuit is added.

FIG. 8 is a block diagram showing a third embodiment of the digital filter of the present invention.

FIG. 9 is a timing chart illustrating the operation of the third embodiment.

FIG. 10 is a configuration diagram of an FIR digital filter.

FIG. 11 is a block diagram showing a conventional digital filter.

FIG. 12 is a configuration diagram of a separation filter using QMF.

[Explanation of symbols]

 1,21 delay element 2,22,24 multiplier 3,23,25 sum adder 26 subtractor 27 adder 11,31 RAM 12,32 ROM 13,33 multiplier 14,34 accumulator 15,35 adder 16, 36 first register 17, 37 second register 38 third register 39 adder / subtractor 40 fourth register 41 first selector 42 second selector 51 preset counter 52, 53 loop counter

Continuation of the front page (56) References JP-A-3-262206 (JP, A) JP-A-4-287413 (JP, A) JP-A-62-34412 (JP, A) JP-A-5-35774 (JP, A) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03H 17/00-17/08

Claims (3)

(57) [Claims] A memory for storing input time-series data;
A multiplier for multiplying the input time-series data read from the memory by a predetermined filter coefficient, an accumulator for sequentially accumulating the multiplication result of the multiplier, and a pair of registers for alternately receiving the accumulation result of the accumulator; An adder / subtractor for adding or subtracting two accumulated addition results obtained from the pair of registers, and outputting the operation value as two output time-series data serving as separated data of the input time-series data. And a digital filter. 2. A memory for storing input time-series data,
A multiplier for multiplying the input time-series data read from the memory by a predetermined filter coefficient, an accumulator for sequentially accumulating the multiplication result of the multiplier, and a pair of registers for alternately receiving the accumulation result of the accumulator; An adder / subtracter for adding or subtracting two accumulative addition results taken out from the pair of registers, and outputting the operation value as two output time-series data serving as separated data of the input time-series data, and an output from the adder / subtractor. A selector for replacing output time-series data with input time-series data and inputting the input time-series data to the memory. 3. A memory for storing input time-series data,
A multiplier for multiplying the input time-series data read from the memory by a predetermined filter coefficient, an accumulator for sequentially accumulating the multiplication result of the multiplier, and a pair of registers for alternately receiving the accumulation result of the accumulator; An adder / subtracter for adding or subtracting two accumulative addition results taken out from the pair of registers, and outputting the operation value as two output time-series data serving as separated data of the input time-series data, and an output from the adder / subtractor. A first selector that replaces the output time-series data with input time-series data and inputs the time-series data to the memory; and a time-series output data that is input to the memory from the first selector and read after a predetermined period has elapsed. A second selector that replaces and outputs time-series output data output from the adder / subtracter,
A digital filter comprising: