JP2864827B2 - Wavelet converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wavelet converter.

[0002]

2. Description of the Related Art When a wavelet transform is applied to a one-dimensional signal such as an audio signal, the wavelet transform separates an input signal into a low-frequency component and a high-frequency component and further reduces the frequency by a factor of two. This is performed by recursively connecting the two-divided sub-band filters to the low-band signal output side in a recursive manner, using a two-divided sub-band filter that outputs a low-frequency signal and a high-frequency signal as a basic unit. The two-divided sub-band filter can be realized by connecting a low-pass downsampling filter and a high-pass downsampling filter in common.
FIG. 6 shows a configuration example in which a frequency band of an input signal of a conventional wavelet transform device is divided into four, and is realized by connecting two-stage sub-band filter devices 601, 602, and 603 in three stages. Each of the two-divided sub-band filters includes low-pass down-sampling filters 611 to 613 and high-pass down-sampling filters 621 to 623, respectively. FIG. 7 is a diagram illustrating an example of a two-divided sub-band filter device.
Two R-type filters are used, one is used as a low-pass filter, and the other is used as a high-pass filter, and the output of each is down-sampled by half by down-samplers 741 and 742. One of the low-pass filters includes delay units 711 to 713, multipliers 721 to 724, and an adder 731. The other high-pass filter includes delay units 714 to 716 and multipliers 725 to 715.
28 and an adder 732. In FIG. 7, reference numeral 701 denotes an input terminal; 751, a low-frequency signal output terminal; and 752, a high-frequency signal output terminal.

[0003]

In the conventional system, a wavelet transform device is realized by connecting a plurality of two-divided sub-band filter devices in a plurality of stages, so that the input interval of input data to the subsequent two-divided sub-band filter device is reduced. However, there is a problem that utilization efficiency of the two-divided sub-band filter device is poor because the latter two-stage sub-band filter device is idle.

SUMMARY OF THE INVENTION It is an object of the present invention to increase the utilization efficiency of the two-divided sub-band filter device by multiplexing the two-divided sub-band filter device while maintaining the function of the wavelet transform. It is an object of the present invention to provide a wavelet conversion device in which the circuit size is reduced.

[0005]

According to a first aspect of the present invention, an input signal is separated into a low-frequency component and a high-frequency component and further divided into two components.
A two-divided sub-band filter that down-samples by one and outputs a low-band signal and a high-band signal, respectively, is used as one stage, and an external input signal is input to a first-stage two-divided sub-band filter to perform a filter operation. , The low-pass signal output from the first-stage two-division sub-band filter is input to the second two-division sub-band filter, and a filter operation is performed. N is an integer of 1 or more)
High frequency signal outputs from the first stage to the (N-1) th stage;
A first sub-band filter operation circuit for performing a first-stage two-division sub-band filter operation in a wavelet conversion device that performs wavelet conversion by using an Nth-stage low band and high band signal as an output signal And a second two-divided sub-band filter circuit for performing a second to N-th two-divided sub-band filter operation, wherein the first sub-band filter operation circuit is input from an input terminal. A first delay line composed of M (M is an integer equal to or greater than 1) delay units to which signals are input, and output signals of the respective delay units of the first delay line are input and a filter coefficient is input. And a first convolution operation circuit that outputs a low-frequency signal and a high-frequency signal by executing a convolution operation with the first, second, and second sub-band filter circuits.
.. a second delay line including M-th (M is an integer of 1 or more) M delay devices, to which a low-pass signal output from the first two-divided sub-band filter circuit is input , And the third, fourth,..., Into which low-frequency signals output from the low-frequency signal output terminal, which are composed of M delay devices in the same manner as the second delay line, are distributed and input. An Nth delay train;
The first and second output signals of the first, second, third,..., Mth delay units of the second, third,. .., (N−
1) and the first, second,..., (N−
It is characterized by comprising a second convolution operation circuit that receives the output signal of the selector of 1), executes a convolution operation with a filter coefficient, and outputs a low-frequency signal and a high-frequency signal.

According to a second aspect of the invention, the input signal is divided into a low-frequency component and a high-frequency component, down-sampled by a factor of two, and output as a low-frequency signal and a high-frequency signal, respectively. Using the filter as one stage, an input signal from the outside is input to the first-stage two-division sub-band filter to perform a filter operation, and the low-frequency signal output from the first-stage two-division sub-band filter is output to the first stage. 2 and performs a filter operation by recursively repeating N stages (N is an integer equal to or greater than 1) of a two-stage sub-band filter to execute a first-stage two-stage sub-band filter operation. In the wavelet transform device that performs wavelet transform by using the high-band signal output from the Nth stage to the (N-1) th stage and the low-band and high-band signals in the N-th stage as output signals, 2, ..., A first delay line including M (M is an integer of 1 or more) M delay units to which an input signal is inputted, and M delay units similarly to the first delay line sequence .., Nth delay trains to which the low-frequency signal output from the low-frequency signal output terminal is distributed and input, and the first, second,. , Nth, Nth,..., Nth selecting and outputting the output signals of the first, second, third,...
, And a convolution operation circuit that receives the output signals of the first, second,..., And Nth selectors, performs convolution operation with filter coefficients, and outputs a low-frequency signal and a high-frequency signal. And characterized by the following.

In the first or second invention, the convolution operation circuit comprises M input terminals, M first multipliers connected to the respective input terminals, and output signals of the multipliers. , And a first adder that outputs the result to a first output terminal, and M connected to each of the input terminals.
It is characterized by comprising a plurality of second multipliers and a second adder for adding output signals of these multipliers and outputting to a second output terminal.

In the first or second invention, the convolution operation circuit inputs a set of first, second,..., Mth input terminals and the first and second input terminals. In the same manner, a first selection circuit that selects and outputs one of them, and a second selection circuit that receives a set of the second and third input terminals as an input and selects and outputs one of them. A third, fourth,..., And (M−1) -th selector for selecting one of the two input terminals adjacent to each other as an input and outputting one of the two input terminals; .., (M-1) multipliers connected to each of the (M-1) th selectors and capable of switching two multiplication coefficients, and an adder for adding output signals of these multipliers And a switch for distributing the output signal of the adder and outputting it to a first output terminal and a second output terminal. The features.

In the first or second invention, the convolution operation circuit inputs a first, second,..., Mth input terminal and a set of the first and Mth input terminals. A first selection circuit that selects and outputs one of them, and a second selection circuit that receives the set of the second and (M−1) input terminals as inputs and selects and outputs one of them. Similarly, the third, fourth,..., (M−) outputs a set of input terminals located at symmetrical positions and selects and outputs one of them.
1) and the first, second,..., (M−
(M-1) multipliers connected to each of the selectors of 1), an adder for adding the output signals of the multipliers, a first output terminal for distributing the output signals of the adders, It is characterized by comprising a switch for outputting to the second output terminal.

[0010]

In order to use the two-stage sub-band filters connected in cascade without being idle, the first two-stage sub-band filter circuit is assigned to the first-stage two-stage sub-band filter operation, and the second and subsequent stages are used. May be assigned to the second two-divided sub-band filter circuit. A low-pass filter and a high-pass filter used in a two-divided sub-band filter employ a direct configuration type FIR filter circuit in which a delay device is arranged on the input side of the filter. The second two-divided sub-band filter circuit must perform (N-1) two-divided sub-band filter operations. In this case, (N-1) delayer trains are prepared corresponding to the (N-1) input signals, and a signal to be input to a convolution operation circuit for executing a convolution operation of a filter coefficient and an input signal is first processed. In this case, any one of the (N-1) delayer arrays may be selected and sequentially input. With this configuration, the convolution operation circuit can be effectively used without being idle, and the number of convolution operation circuits can be reduced, so that the circuit scale can be reduced.

[0011] The convolution operation circuit executes a convolution operation of the input signal and the filter coefficient. Change the input signal to (x
₀ , x ₁ ,..., X _Q ) and the filter coefficients are (c ₀ , c ₁ ,..., C _Q ), the convolution operation result y is

[0012]

(Equation 1)

## EQU1 ## The convolution operation circuit may calculate the low-pass signal and the high-pass signal output by switching the coefficient between two kinds of coefficients, that is, a low-pass filter and a high-pass filter.

In the simplest configuration of the convolution operation circuit, two multipliers, one for a low-pass filter and one for a high-pass filter, are provided with a multiplier for multiplying an input signal and a filter coefficient and an adder for obtaining the sum of the multiplication results. Then, the low-frequency signal and the high-frequency signal output are calculated simultaneously.

In order to reduce the number of multipliers, the coefficients of the multipliers can be switched between those for the low-pass filter and those for the high-pass filter, so that the low-pass signal and the high-pass signal output are alternately changed. Is to calculate

Furthermore, during the (Q + 1) coefficients b _i of the coefficient a _i and M order high-pass type filter of the next low-pass type filter,

[0017]

(Equation 2)

In such a case, the input of the multiplier and the output of the delay unit corresponding to the coefficient are used when calculating the low-band signal output and when calculating the high-band signal output. By switching to a signal, a fixed coefficient multiplier can be used as a multiplier of the convolution operation circuit. However,
When obtaining the high-frequency signal output, the signal multiplied by the even-numbered coefficient must be added, and the signal multiplied by the odd-numbered coefficient must be subtracted. In this configuration, it is sufficient to prepare a number of fixed coefficient multipliers corresponding to the order of the filter.
Equipment size can be reduced.

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the first invention.
9 is a configuration example of a wavelet transform device that performs a two-stage sub-band filter operation of a stage and divides a frequency band of a signal into four. The input signal is divided into two sub-band filter devices 1
00 is input to the input terminal 110. In the two-divided sub-band filter device 100, the first-stage two-divided sub-band filter operation is performed. The input signal is input to the input terminal 110 in synchronization with the clock signal having the period T, and sequentially moves the delay units 111, 112, 113, 114,. Delay devices 111, 112, 113, 11
The output signals of 4,... Are input to the convolution operation circuit 116. Each time the input signal changes, the convolution operation circuit 116 performs a convolution operation on the input signal and the coefficients of the low-pass filter or the coefficients of the high-pass filter, or both operations, and executes the result. The signals are output to output terminals 117 and 118 as a low-frequency signal and a high-frequency signal, respectively.
At this time, the period at which these signals are output is 2T. The two-divided sub-band filter device 101 executes the second-stage and third-stage two-divided sub-band filter calculations. The low-frequency signal output from the low-frequency signal output terminal 117 of the two-divided sub-band filter device 100 is input to the input terminal 120 in synchronization with the clock signal having a period of 2T, and the cascade-connected delay devices 121, 122, 123, 124,
.. Are sequentially moved. Delay devices 121, 122, 12
The output signals of 3, 124,.
Are input to the convolution operation circuit 140. Selectors 131, 13
, 2, 133, 134,...
And 1 once. Each time the input signal changes, the convolution operation circuit 140 performs a convolution operation on the input signal and the coefficient of the low-pass filter or the coefficient of the high-pass filter, or both operations, and executes the result. Output terminals 141 and 14 as a low band signal and a high band signal, respectively.
Output to 2. At this time, the period at which these signals are output is 4T. The signal corresponding to the low-pass signal as the result of the second-stage sub-band filter operation at the second stage is composed of delay units 151 and 15 cascaded in synchronization with a clock signal having a period of 4T.
, 153, 154,... Are sequentially moved. Delay device 1
The output signals of 51, 152, 153, 154,.
Selectors 131, 132, 133, 134,.
And is input to the convolution operation circuit 140. The result of the wavelet conversion is output to output terminals 118 and 14.
1,142.

FIG. 2 shows an embodiment of the second invention.
9 is a configuration example of a wavelet transform device that performs a two-stage sub-band filter operation of a stage and divides a frequency band of a signal into four. The input signal is divided into two sub-band filter devices 2
00 input terminal 210. The two-divided sub-band filter device 200 executes the first-stage, second-stage, and third-stage two-divided sub-band filter calculations. The input signal is synchronized with the clock signal having the cycle T by the input terminal 21.
0, and cascaded delay units 211, 212,
, 214,... Are sequentially moved. Selector 23
Are input to the convolution operation circuit 240 through 1,232,233,234,. Selectors 231 and 23
2, 233, 234,... Switch the input, for example, 0, 1, 0, 2, 0, 1, 0, * during the period 4T (here, “*” does not select anything) Represents that).
Each time the input signal changes, the convolution operation circuit 240 executes a convolution operation of the input signal and the coefficient of the low-pass filter or the coefficient of the high-pass filter, or both operations, and executes the result. The signals are output to output terminals 241 and 242 as a low-frequency signal and a high-frequency signal, respectively. At this time, the period at which these signals are output is T. The signal corresponding to the low-pass signal as the result of the second-stage sub-band filter operation in the second stage is composed of delay units 251, 252, 253, 254,.
・ Move sequentially. Delay units 251, 252, 253, 2
Are output from selectors 231 and 231 respectively.
32, 233, 234,... Are input to the convolution operation circuit 140. The signal corresponding to the low-pass signal as the result of the second-stage sub-band filter operation at the third stage has a period of 4T.
Delay unit 26 cascaded in synchronization with the clock signal of
, 262, 263, 264,... Are sequentially moved.
The output signals of the delay units 261, 262, 263, 264,.
, And are input to the convolution operation circuit 140. The result of the wavelet conversion is output to output terminal 24.
1,242.

FIG. 3 is a diagram showing a first configuration example of the convolution operation circuit used in the first or second invention. A configuration example in which the order of the filter used in the two-divided subband filter is the fourth order It is. The input signal input to the convolution operation circuit is input to the input terminals 301, 302, 303, and 304 in order from the one closer to the input side of the delay unit in FIG. 1 or FIG. Multipliers 311, 312, 313, and 314 have low-pass filter coefficients (cl0, cl1, cl2,
cl3) is set. Multipliers 311, 312, 3
13 and 314 each multiply the input signal by a coefficient, and the multiplication result is added in an adder 315. The addition result is output from the low band signal output terminal 316 as a low band signal. The multipliers 321.322, 323, and 324 have coefficients (ch0, ch1, ch2, and ch) of the high-pass filter.
3) is set. Multipliers 321, 322, 32
3, 324 each multiply the input signal by a coefficient, and the multiplication result is added in the adder 325. The addition result is
It is output from the high frequency signal output terminal 326 as a high frequency signal.

FIG. 4 is a diagram showing a second configuration example of the convolution operation circuit used in the first or second aspect of the present invention. The configuration example in the case where the order of the filter used in the two-divided subband filter is the fourth order It is. The input signals input to the convolution operation circuit are input terminal 401, 402, 403, 404, and 4 in order from the one closer to the input side of the delay unit in FIG.
05 is input. Selectors 411, 412, 413, 4
14 is an input terminal 401, 402, 403, 404, 4
Each time the signal input to 05 changes, inputs 0 and 1 of the selector
Switch. Multipliers 421, 422, 423, 424
Are respectively set as the coefficients of the low-pass filter and the coefficients of the high-pass filter as multiplication coefficients, and when the selectors 411, 412, 413, and 414 select the input 0, the low-pass filter Shape coefficients (cl0, cl1, cl2,
cl3), the high-pass coefficients (ch0, ch1, ch2, ch3) are adopted when the input 1 is selected. The multipliers 421, 422, 423, and 424 multiply the input signal by the coefficient, respectively, and the result of the multiplication is added by the adder 425. When the convolution operation with the low-pass filter coefficient is performed via the switch 428, the addition result is output from the low-band signal output terminal 426 as a low-band signal,
When the convolution operation with the high-pass filter coefficient is performed, the signal is output from the high-band signal output terminal 427 as a high-band signal.

FIG. 5 is a diagram showing a third configuration example of the convolution operation circuit used in the first or second aspect of the present invention. The configuration example in the case where the order of the filter used in the two-divided subband filter is the fourth order It is. The input signal input to the convolution operation circuit is input to the input terminals 501, 502, 503, and 504 in order from the one closer to the input side of the delay unit in FIG. 1 or FIG. The input terminals 0 of the selectors 511, 512, 513, 514 are input terminals 501, 502, 50, respectively.
3, 504, and are connected to the input terminal 1 as input terminals 505, 504, 503, and 502, respectively. The selectors 511, 512, 513, and 514 switch between inputs 0 and 1 of the selector each time a signal input to the input terminals 501, 502, 503, 504, and 505 changes. The multipliers 521, 522, 523, and 524 respectively provide filter coefficients (c0, c1, c
2, c3) are set. Multipliers 521, 522,
523 and 524 respectively multiply the input signal by a coefficient,
The multiplication result is added in the adder 525. When the convolution operation with the low-pass filter coefficient is executed via the switch 528, the addition result is output from the low-pass signal output terminal 526 as a low-pass signal, and the convolution operation with the high-pass filter coefficient is executed. In this case, the signal is output from the high frequency signal output terminal 527 as a high frequency signal.

[0025]

According to the wavelet transform device of the first invention, the wavelet transform device can be constituted by two two-divided subband filter devices, so that the circuit scale can be reduced.

A wavelet conversion device according to a second aspect of the present invention
Since the wavelet transform device can be constituted by two two-divided subband filter devices, the circuit scale can be significantly reduced.

The convolution operation circuit used in the wavelet conversion device according to the first or second aspect of the invention has a simple circuit configuration and can be easily realized.

The convolution operation circuit used in the wavelet transform device according to the first or second aspect of the invention switches the operation circuit between low-pass filter operation and high-pass filter operation by switching the coefficient of the multiplier. Since it can be used for both, the circuit scale can be reduced.

The convolution operation circuit used in the wavelet transform device of the first or second invention uses a fixed coefficient multiplier, so that the multiplication circuit can be simplified and the size can be reduced. A reduction in scale can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a wavelet conversion device according to the first invention.

FIG. 2 is a block diagram showing one embodiment of a wavelet conversion device according to the second invention.

FIG. 3 is a block diagram illustrating a configuration example of a convolution operation circuit.

FIG. 4 is a block diagram illustrating a configuration example of a convolution operation circuit.

FIG. 5 is a block diagram illustrating a configuration example of a convolution operation circuit.

FIG. 6 is a diagram showing a configuration of a conventional wavelet conversion device.

FIG. 7 is a block diagram illustrating an example of a conventional two-divided sub-band filter.

[Explanation of symbols]

100, 101, 200, 601-603 Two-divided sub-band filters 110, 210, 301-304, 401-405, 5
01 to 505 Input terminals 111 to 114, 121 to 124, 151 to 154, 2
11-214, 251-254, 261-264, 71
1-716 Delay device 117, 141, 241, 316, 426, 526, 7
51 Low frequency signal output terminals 118, 142, 242, 326, 427, 527, 7
52 High frequency signal output terminals 311 to 314, 321 to 324, 421 to 424, 5
21 to 524, 721 to 728 Multipliers 315, 325, 425, 525, 731, 742 Adders 421 to 424, 511 to 514 Selectors 428, 528 Switches 611 to 613 Low-pass downsampling filters 621 to 623 High frequencies Pass-type down sampling filter 741,742 Down sampler

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-298125 (JP, A) JP-A-63-254812 (JP, A) JP-A-54-126444 (JP, A) IEEE TRANSACTIONS ON ASSP, 37 [12] (1989) p. 2091-2110 IEEE TRANSACTIONS ON PATTERN ANALYSIS IS AND MACHINE INT ELLIGENCE, 11 [7] (1989) p. 674-693 (58) Field surveyed (Int.Cl. ⁶ , DB name) H03H 15/00-21/00

Claims (5)

(57) [Claims] An input signal is divided into a low-frequency component and a high-frequency component, further down-sampled by a factor of two, and a two-divided sub-band filter for outputting a low-frequency signal and a high-frequency signal, respectively, as one stage. , An external input signal is input to a first-stage two-division sub-band filter to perform a filter operation, and a low-pass signal output from the first-stage two-division sub-band filter is divided into a second two-division sub-band. The input to the sub-band filter, the filter operation is executed, and this is recursively repeated to execute N-stage (N is an integer of 1 or more) 2-divided sub-band filter operation. -1) In a wavelet transform apparatus that performs wavelet transform by using the high-frequency signal output up to the stage and the low- and high-frequency signals in the N-th stage as output signals, Band filter A first sub-band filter operation circuit for performing an operation, and a second two-part sub-band filter circuit for performing a second to N-th two-part sub-band filter operation; M where the signal input from the input terminal is input to the filter operation circuit (M is an integer of 1 or more)
A first delay line composed of a plurality of delay units;
A first convolution operation circuit that receives the output signal of each of the delay units in the series of delay units, executes a convolution operation with a filter coefficient, and outputs a low-frequency signal and a high-frequency signal, The sub-band filter circuit is composed of M first, second,..., M-th (M is an integer equal to or greater than 1) delay units, and is output from the first two-divided sub-band filter circuit. A second low-frequency signal to which a low-frequency signal is input, and a low-frequency signal output from a low-frequency signal output terminal, which is composed of M delay units similarly to the second low-frequency signal train, is distributed. .., N-th delay line, and the first, second, third and third lines of the second, third,. .., The first, second, third,..., (N−1) th selectors for selecting and outputting the output signal of the Mth delay unit , The output signals of the first, second,..., (N−1) th selectors are input, and a convolution operation with filter coefficients is performed to output a low-frequency signal and a high-frequency signal. A wavelet transform device comprising a convolution operation circuit of 2. A two-stage sub-band filter, which separates an input signal into a low-frequency component and a high-frequency component, down-samples the signal by half, and outputs the low-frequency signal and the high-frequency signal, respectively. , An external input signal is input to a first-stage two-division sub-band filter to perform a filter operation, and a low-pass signal output from the first-stage two-division sub-band filter is divided into a second two-division sub-band. The input to the sub-band filter, the filter operation is executed, and this is recursively repeated to execute N-stage (N is an integer of 1 or more) 2-divided sub-band filter operation. -1) In a wavelet transform apparatus that performs wavelet transform by using a high-band signal output up to the stage and an N-th low-band and high-band signal as an output signal, the first, second,.・, Mth (M is 1 or more (The above integer), a first delay line including M delay units to which an input signal is input, and a low-band signal output to be described later including M delay units similarly to the first delay line sequence. .., Nth delay line, into which the low-frequency signal output from the terminal is distributed and input, and the first, second,. The first, second, third,..., And N-th selectors select and output the output signals of the first, second, third,. A convolution operation circuit that receives the output signals of the first, second,..., Nth selectors, performs convolution operation with filter coefficients, and outputs a low-frequency signal and a high-frequency signal. Wavelet conversion device characterized by the above-mentioned. 3. The convolution operation circuit comprises: M input terminals; and M first terminals connected to each of the input terminals.
, A first adder that adds the output signals of these multipliers and outputs the result to a first output terminal, M second multipliers connected to each of the input terminals, A second output for adding the output signals of the multipliers and outputting the sum to a second output terminal
3. The wavelet transform device according to claim 1, wherein the wavelet transform device comprises an adder. 4. The convolution operation circuit according to claim 1, wherein:
.. a M-th input terminal, a first selection circuit that receives a set of the first and second input terminals and selects and outputs one of them, and a second one of the second and third input terminals Similarly, a second selection circuit that takes a set as an input and selects and outputs one of them, and a third and fourth output circuit that takes a set of two adjacent input terminals as an input and selects and outputs either one , ..., (M
-1) and the first, second,..., (M−
(M-1) multipliers connected to each of the selectors of 1) and capable of switching two multiplication coefficients, an adder for adding output signals of these multipliers, and an output signal of the adder 3. The wavelet conversion device according to claim 1, further comprising a switch for distributing the signals and outputting the signals to a first output terminal and a second output terminal. 5. The convolution operation circuit according to claim 1, wherein:
.. an M-th input terminal, a first selection circuit that receives a set of the first and M-th input terminals and selects and outputs one of the sets, and a second and (M-1) th selection circuit. And a second selection circuit for selecting and outputting either one of the input terminal sets and inputting and selecting one of the input terminal sets at symmetrical positions. 3,4th, ...
., The (M-1) th selector, the first, second,.
., (M- 1)
1) Multipliers, an adder for adding the output signals of the multipliers, and a switch for distributing the output signal of the adder and outputting to the first output terminal and the second output terminal The wavelet conversion device according to claim 1 or 2, wherein: