JPH01289310A - Acyclic down-sampling filter - Google Patents

Abstract

PURPOSE:To decrease number of multipliers in use and quantity of operation and to reduce the circuit scale by constituting the filter with at least one product sum arithmetic circuit applying product sum operation of M sets of filter coefficients, outputting total sum of outputs of delay elements at down-sampling period and being initialized and a multi-input adder obtaining the total sum of the outputs of the delay elements. CONSTITUTION:Product sum arithmetic circuits 110, 111,... are realized by multipliers multiplying M-set of coefficients with an input signal 100 while switching the coefficients sequentially, an adder 130 applying accumulation and an accumulator storing the result of accumulation and the circuits have only to be constituted such that the result of accumulation is outputted for M-set of input signals 100 and the product sum arithmetic circuits 110, 111,... are initialized. Thus, since one multiplier is enough to multiplier M-set of filter coefficients, the number of multipliers is reduced to N/M as the entire FIR down-sampling filter. Then the number of multipliers is reduced to 1/M of that of a conventional system and number of inputs to the adder 130 is reduced to 1/M, then the circuit scale is reduced.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to an acyclic downsampling filter having a downsampling function that reduces the sampling frequency of an output signal to an integer fraction of the sampling frequency of a human signal. It is something.

(Prior Art) Conventionally, when a one-minute downsampling filter is implemented using an acyclic (rFIR type) filter, for example, an FIR type filter 110G is used as shown in FIG.
A configuration is used in which a one-minute down sampler ttto is connected to the output of the .

FIR type filter! The filter length of 100 is N (integer)
, the filter coefficients are h(0), h(1),..., h(N
-1), and the input signal is transmitted through (l) delay devices 1120, 1121 . ...
are moved according to the sampling clock of the input signal, and the multipliers 1130, 1131 . . . , delay devices 112G, 1121 . . . are provided for each sampling clock. ...
A multiplication of the input delayed signal moving through the filter coefficients is performed. Multi-input adder 1140 includes multipliers 113G, 113
1. . . , and outputs the output signal of the FIR type filter. 1/X down sampler 1110
realizes a 1/M down-sampling filter by outputting one sample for each sample of the output signal of the FIR type filter 1100.

(Problem to be Solved by the Invention) However, in the conventional method, the FIR type filter outputs a signal at the same sampling period as the input, so the output signal of the FfR type filter, which is not required for downsampling output, is always The drawback is that it requires a large number of arithmetic units because it performs filter calculations.

The purpose of the present invention is to overcome these drawbacks of the prior art and to
FIR type down that is suitable for LSI, reduces the number of required multipliers by using multiple multipliers, and reduces the circuit size by reducing the amount of calculations by omitting unnecessary calculations while maintaining the function of the digital filter. The purpose of this invention is to provide a sampling filter.

(Means for Solving the Problem) The present invention provides an FIR type downsampling filter having a 1/M downsampling function that lowers the sampling frequency of an output signal to 1/M with respect to the sampling frequency of an input signal. at least one product-sum calculation circuit connected to the terminal and initialized by performing a product-sum calculation of the filter coefficients on the input signal and outputting the result of the product-sum calculation in a downsampling period; and the product-sum calculation circuit; This is an FIR type downsampling filter that includes a delay element that delays the result of a product-sum operation in a circuit, and a multi-input adder that calculates the sum of the outputs of the delay element.

(Operation) In order to explain the present invention in detail, each circuit will be expressed using the signal flow graph notation shown in FIG. In FIG. 5, the operation name represents the name of the skill operation. The notation represents the signal 70 of each technique operation - the symbol in the graph, and the input signal x(n) moves in the direction of the arrow in response to the technique operation,
The output signal becomes y(n). Here, n (integer) represents the n-th sampling time, n-1 represents the time before the sampling period of time n, and x(nL y(n) are the input and output signals at time n, respectively. Time The area expression represents the relationship between the input and output signals of each technique operation.The unit delay represents a delay of 1 sample period z-1, and the gain represents multiplication by a coefficient C.Downsampling by 1/M is It represents that the input signal is output at a rate of one sample to the image side, and in the time domain expression, x (Ma+) is the input signal at the n-th sampling time, and y (++) is the output signal at the first down-sampling time. Addition means summing multiple inputs, branching means branching of an input signal, input branch means an input terminal of a signal, and output branch means an output terminal of a signal.

FIG. 6 is an explanatory diagram of the equivalent transformation of the basic technique of the signal flow graph used in this text. In Figure 6, (a
) is an example of mutually possible equivalent conversion of unit delay,
(b) is an example where the equivalent conversion of 1/M downsampling is mutually possible, (C) is an example where the equivalent conversion of gain and 1/M downsampling is mutually possible, (
d) shows an example of equivalent conversion with unit delay and 1/M downsampling. However, the amount of M in (d)! The unit delay on the input side of downsampling represents the delay in the sampling period of the input signal, and the unit delay on the output side of downsampling by M in (d) represents the delay in the downsampling period of the output signal.

The signal flow graph of the FIR type downsampling filter shown in FIG. 11 becomes as shown in FIG. 7 using the notation shown in FIG.

Here, the filter length of the FIR type filter is N (integer),
If the filter coefficients are h(0), h(1), ..., h(N-
1), then (K-1)M≦N(KM (K is a positive integer) (1), then again N:KM (2)
Then, h(N):h(N+1)=・・・・・・:h(KM-1
):0 (3), the expanded F
Since the IR filter is equivalent to the original FIR filter, in the following explanation it is assumed that N is an integer multiple of A.

For the signal flow graph in Fig. 7, perform the equivalent conversion of the technique shown in Fig. 6(a) using N units of unit delay as one set from the input terminal side, and convert the 1/K down sampler into 6 FIG. 8 is obtained by performing equivalent transformation of the branches shown in FIGS. (b) and (c). Furthermore, by performing equivalent transformation of the branches shown in FIG. 6(d), the signal flow graph shown in FIG. 9 is obtained.

According to FIG. 9, the FIR type downsampling filter has filter coefficients h(KM), h(KM+1), . . .
, h(Kg+(M-t)) (0≦K (K, K is an integer).
. . , 900-, and delay strings 91G-〇, . It can be seen that it is composed of addition.

FIG. 1θ is a signal flow graph showing the second partial circuit of FIG. 9 in more detail. In Figure 1θ,
The input signal at time n is xx(n), and the output signal is y
K(m), the input/output relationship is expressed by equation (4), where the input signal sequence of the partial circuit is XK(Mll-(M-1)), xK(M
m-(M-2)), sea xK(Mm-1)+xK
(Mm), and the filter coefficient b(kM+
(M-1)), h(kM+(M-2)),...

This shows that h(kM+1) is multiplied by h(kM) and N multiplication results are accumulated. In other words, the coefficient of the multiplier for each input signal is h(kM+(jl-J)), h(kN÷
(M-2)), ..., b(kM+1), h(kM) and multiply them by the input signal, perform a product-sum operation to accumulate and output the multiplication results on the image side, and perform N This indicates that when the product-sum calculation of the input signals of 1 is completed, the product-sum calculation of the input signals of the next image side can be performed again in the same manner. Therefore, the product-sum operation circuit has N coefficients h(kM+(M-1))
, h(kM+(M-2)).

..., a multiplier that sequentially switches h(kM+1) and h(km) and multiplies the input signal, and an adder that performs accumulation,
It can be realized by an accumulator that holds the accumulated results, and any configuration that outputs the accumulated results every time the input signal is input and initializes the product-sum calculation circuit is sufficient. If you do this,
By using a product-sum calculation circuit, it is possible to multiply filter coefficients with one multiplier, so F
In the entire IR type downsampling filter, the number of multipliers can be reduced to HIM.

From the above, the FIR type downsampling filter circuit of the present invention has 0 product-sum calculation circuits connected to the input terminal and 0 product-sum calculation circuits connected in series to the output terminal of the product-sum calculation circuit.
0 in order from the th product-sum calculation circuit. ! ,..., (K-1
) down-sampling periods and a circuit that calculates the sum of delay signal outputs of delay elements. The order in which each product-sum operation circuit multiplies the filter coefficients in charge is h(M-1) in order from the input end.
, h(M-2), ..., h(0), the second is h(M+
(M-1)), h(M+(■-2)), ..., h(N
), ..., Kth is h((k-1)M+(M-
1)), h((K-1)M+(■-2)).

..., h((K-1)M), when the unpacking multiplication is completed, output the product-sum calculation result, initialize the product-sum calculation circuit, and repeat the next product-sum calculation in the same way. By performing calculations,
An FIR type downsampling filter that performs a downsampling operation by a factor of N is realized.

(Embodiment) FIG. 1 shows an embodiment for realizing the present invention. The input signals are input to the product-sum calculation circuits 11G, I'll, . k delay elements 120, 121. ... gives a delay to the product-sum circuit output signals of the product-sum calculation circuits 110°tti, . The multi-input adder circuit 13G has delay elements 120, 1
21. It receives the delayed output of... and calculates the sum and outputs it.

FIG. 2 is a diagram showing an example of the configuration of a delay element connected to the product-sum calculation circuit. Unit delay element 200, 20
1. ... are connected in series, and the signal moves according to the output downsampling clock.

FIG. 3(a) shows the product-sum circuits 120, 121 .・
In the first embodiment, FIG. 3(b) is a time chart of the main signals in FIG. 3(a). From the input side in Figure 1, k (k: 0, l, 2,..., (K-1)
)-th product-sum calculation circuit will be explained. Multiplier 300 multiplies the input signal by a coefficient. Coefficient selection circuit 3
30 is h(kM+(M-1)), h(kM+(M-2)
), ......, h (kM+1), h (kg) in the order of one coefficient 320 for one input signal,
When the output of the coefficients on the same side is completed, one product-sum calculation is completed, and the same process is repeated again. Adder 340
adds the multiplication result and the contents of the accumulator 350 and outputs the result to the accumulator 350.

When the downsampler 360 completes the product-sum operation of the input signals, it downsamples and outputs the product-sum operation result in accordance with the downsampling clock CLK3. The accumulator 340 is reset to O by the reset clock CLK2, and the coefficient selection circuit 330 is initialized to select the first coefficient. FIG. 3(a) is a time chart of each signal when operating at the rising edge of the clock. CLKl is the input signal sampling clock, CLK2 is the reset clock, CL
K3 is a down sample clock. Coefficient indicates the coefficient to be selected.

FIG. 4(a) is a second embodiment of the product-sum calculation circuit, and FIG. 3(b) is a time chart of the main signals in FIG. 3(a). The operations of multiplier 400, coefficient selection circuit 430, and adder 440 are similar to those shown in FIG.

The operation is otherwise similar to that of FIG. 3, except that accurator 450 is not reset. multiplexer 470
switches the output signal from the output signal of the accurator 450 to 0 when the reset clock CLK2 is at the old level. Downsampler 460 operates according to downsampling clock CLK3.

(Effects of the Invention) According to the configuration of the FIR type downsampling filter for 1/2 downsampling of the present invention, the multiplication circuit that multiplies the filter coefficients on the image side can be realized with one product-sum calculation circuit. The number of devices can be reduced to 1/M of that of the conventional system, and the input of the total adder circuit can also be reduced to 1/M.

As described above, according to the present invention, it is possible to easily downsize and simplify the FIR type downsampling filter, and its effects are extremely large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the FIR type downsampling filter of the present invention, FIG. 2 is an explanatory diagram of a delay element, FIG. b
) is a time chart of the product-sum calculation circuit in FIG. 3(a), FIG. 4(a) is a configuration diagram of the second product-sum calculation circuit, and FIG. 4(b)
) is a time chart of the product-sum operation circuit in Figure 4 (a), Figure 5 is an explanatory diagram of the signal flow graph technique mentioned in the text, and Figures 6 (a) to (d) are equivalent transformations of the signal flow graph. 7 is a signal flow diagram of the conventional circuit, FIG. 8 is a signal flow graph explaining the conversion process of FIG. 7, and FIG. 9 is a signal flow diagram of the circuit of the present invention.
FIG. 1θ is a signal flow diagram of the product-sum calculation circuit, and FIG. 11 is an explanatory diagram of the conventional circuit configuration. In the figure, Ioo is an input terminal, 10I is an output terminal, 1
10. III, . . . are product-sum calculation circuits, +20. I21
．． ... is a delay element, 130 is a multi-input adder, 200
, 201. ... is a unit delay element with a downsampling period of 1.300 is a multiplier, 310 is an input signal, 320 is a coefficient, and 330 is a coefficient selection! , 340 is an adder, 350 is an accumulator with reset capability, 360 is a 1/M down sampler, 400 is a multiplier, 410 is an input signal,
420 is a coefficient, 430 is a coefficient selector, 440 is an adder,
450 is an accumulator, 460 is a 1/M down sampler, 470 is a multiplexer, 480 is an O input device, 1
100 is an FIR type filter, ■20.1+21. ...
are unit delay elements, 1130, 1131. ...is a multiplier! +40 is multi-input addition 3.1110 is a 1/M down sampler.

Claims (1)

[Claims] In an acyclic downsampling filter having a 1/M downsampling function that lowers the sampling frequency of an output signal to an integer (this is used as a wing) with respect to the sampling frequency of an input signal, an input signal connected to an input terminal is used. at least one product-sum calculation circuit that performs a product-sum calculation of a signal and M filter coefficients and is initialized by outputting the result of the product-sum calculation in a downsampling period; and a product-sum calculation circuit of the product-sum calculation circuit. 1. An acyclic downsampling filter comprising: a delay element that delays the result of the delay element; and a multi-input adder that calculates the sum of the outputs of the delay element.