KR19980047256A - Discrete Wavelet Transducer and Its Driving Method - Google Patents

Abstract

The present invention can use the characteristics of the discrete wavelet transform to make the operation speed faster than that of the conventional wavelet transducer, and to reduce the area of the VLSI by reducing the number of registers used when the number of coefficients of the low pass filter and the high pass filter is different. Discrete wavelet transducers and methods for driving the same are presented.

Description

Discrete Wavelet Transducer and Its Driving Method

The present invention relates to the structure of the VLSI, and more particularly, to a discrete wavelet converter and a driving method thereof using the characteristics of the wavelet transform.

When transmitting a video signal in a communication network, data compression becomes essential due to the enormous amount of data processing, and various compression techniques have been developed and studied for this purpose. Among them, the discrete wavelet transform has gained considerable attention in the field of signal processing because of its superiority in the field of image compression. However, due to the complexity of the conversion method, the discrete wavelet transform has difficulty in considering various points in the hardware implementation. In addition, for the real-time processing of the image, the operating speed of the hardware must be high, and in order to reduce the manufacturing cost of the hardware, a small-scale VLSI structure is required.

To implement wavelet transformation in hardware, many considerations must be taken into account: the speed of the operation clock, the number of multipliers and adders used, the number of registers to store intermediate values, and the complexity of the interconnections within the circuit.

The prior art in the field of designing the VLSI structure of the discrete wavelet converter is as follows.

(1) Structure using folding technique.

(2) Structure using digit-serial technique.

(3) Structure using Systolic array.

The structure using the folding technique has excellent latency but the interconnection of the circuit is complicated, so the design chip size is large and it cannot be easily expanded according to the filter size and the number of octaves.

The digit-serial structure has a simple circuit connection, but has long latency, limited data words, and requires more specific circuits.

The structure using the systolic array is regular but has the disadvantage of using a large number of registers.

Accordingly, an object of the present invention is to provide a discrete wavelet converter and a driving method thereof capable of improving the number of registers and the operation clock speed while maintaining a short latency, which is an advantage of the folding technique.

The ideal wavelet converter according to the present invention for achieving the above object is an input interface for inputting an external signal and a signal output from the rearrangement block and outputting simultaneously to a high pass and a low pass filter, and a signal input to the input interface. And a low pass filter for outputting a signal generated by performing any one of ibn filtering and odd filtering according to the reordering block, and one of ibn filtering and odd filtering according to the signal input from the input interface. A high pass filter for outputting a signal, a rearrangement block for inputting a signal output from the low pass filter, rearranging the signal in a desired order, and outputting the signal to an input interface; Inputs a control signal block for controlling and an output signal of the high pass filter; That consisting of the output switch for selecting the filter output in accordance with the operation order of the filter is characterized.

In addition, the driving method of the discrete wavelet converter according to the present invention for achieving the above object is the step of simultaneously outputting the external signal and the signal output from the rearrangement circuit from the input interface to the high pass and low pass filter, Outputting a signal generated by performing any one of even filtering and odd filtering in the low pass filter inputting the signal of the input interface to the rearrangement block, and even filtering in the high pass filter inputting the signal of the input interface And outputting a signal generated by performing any one of an odd filtering to an output switch, and rearranging the signal in a desired order according to a control signal of a control signal block in a rearrangement block in which the signal of the low pass filter is input. Outputting the signal to the input interface; And selectively outputting the output switch according to the filter operation order.

1 is a general functional structural diagram of a discrete wavelet transform to which the present invention is applied.

2 is a structural diagram of a discrete wavelet converter according to the present invention;

3 is an input / output table of a discrete wavelet converter according to the present invention.

4 is a structural diagram of a rearrange circuit in a discrete wavelet converter according to the present invention;

5 is a table illustrating the data flow of the rearrange circuit in a discrete wavelet converter according to the present invention.

6 is a structural diagram of a filtering circuit in a discrete wavelet converter according to the present invention;

7 is a table illustrating a data flow of a filtering circuit in a discrete wavelet converter according to the present invention.

* Description of the symbols for the main parts of the drawings *

21: first even filter 22: first odd filter

23: second even filter 24: second odd filter

25: rearrangement block 26: input interface

27: control signal block 28: output switch

The present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a general function of a discrete wavelet transform to which the present invention is applied, and shows a function of a wavelet transform having a depth of 3 octaves. The wavelet converter has a dyadic structure of subband coding as shown. Wavelet transform is performed through the filter operation of three highpass filter blocks 11, 13, and 15 and three lowpass filter blocks 12, 14, and 15. The sample value of the upper octave is passed through the first high pass filter 11 and the first low pass filter 12, and the output of the first high pass filter 11 is equal to the output value of the wavelet converter. The output of the first low pass filter 12 is down-sampled to be the input of the next octave.

In Equations 1 and 2, G (z) is a transfer function of the high pass filter, and H (z) is a transfer function of the low pass filter.

[Equation 1]

G (z) = g ₀ + g ₁ z ^-1 + g ₂ z ^-2 + g ₃ z ^-3

[Equation 2]

H (z) = h ₀ + h ₁ z ^-1 + h ₂ z ^-2 + h ₃ z ^-3

The operation of the first high pass filter in octave 1 is represented by Equations 3 to 6, and the operation of the first low pass filter is represented by Equations 7 to 10.

[Equation 3]

b (0) = g ₀ a (0) + g ₁ a (-1) + g ₂ a (-2) + g ₃ a (-3)

[Equation 4]

b (1) = g ₀ a (2) + g ₁ a (1) + g ₂ a (0) + g ₃ a (-1)

[Equation 5]

b (2) = g ₀ a (4) + g ₁ a (3) + g ₂ a (2) + g ₃ a (1)

[Equation 6]

b (3) = g ₀ a (6) + g ₁ a (5) + g ₂ a (4) + g ₃ a (3)

[Equation 7]

c (0) = h ₀ a (0) + h ₁ a (-1) + h ₂ a (-2) + h ₃ a (-3)

[Equation 8]

c (1) = h ₀ a (2) + h ₁ a (1) + h ₂ a (0) + h ₃ a (-1)

[Equation 9]

c (2) = h ₀ a (4) + h ₁ a (3) + h ₂ a (2) + h ₃ a (1)

[Equation 10]

c (3) = h ₀ a (6) + h ₁ a (5) + h ₂ a (4) + h ₃ a (3)

The operation of the second high pass filter in octave 2 is represented by Equations 11 and 12, and the operation of the second low pass filter is represented by Equations 13 and 14.

[Equation 11]

d (0) = g ₀ c (0) + g ₁ c (-1) + g ₂ c (-2) + g ₃ c (-3)

[Equation 12]

d (1) = g ₀ c (2) + g ₁ c (1) + g ₂ c (0) + g ₃ c (-1)

[Equation 13]

e (0) = h ₀ c (0) + h ₁ c (-1) + h ₂ c (-2) + h ₃ c (-3)

[Equation 14]

e (1) = h ₀ c (2) + h ₁ c (1) + h ₂ c (0) + h ₃ c (-1)

Similarly, the operation of the third high pass filter in octave 3 is expressed by Equation 15, and the operation of the third low pass filter is expressed by Equation 16.

[Equation 15]

f (0) = g ₀ e (0) + g ₁ e (-1) + g ₂ e (-2) + g ₃ e (-3)

[Equation 16]

f '(0) = h ₀ e (0) + h ₁ e (-1) + h ₂ e (-2) + h ₃ e (-3)

Looking at the filter operations of Equations 3 to 16, the even samples are calculated with the coefficients of the even filter, the odd samples are calculated with the coefficients of the odd filter, and the even samples are input. Only when the output of the wavelet converter is generated. Therefore, it can be seen that the upper octave can be filtered using the time between the first octave filtering, that is, the time when the odd numbered sample is input. It is a basic idea of the present invention to utilize the characteristics of such filter operations and the similarity of the filter operations performed in each octave.

In the structure design of implementing the wavelet converter of FIG. 1, in the conventional structure, since the input value is directly processed without delay, the processing time of the critical path that determines the speed of the operation clock is Tm + (N− 1) × Ta, the processing time of the critical path becomes Tm + Ta in the structure proposed in the present invention. Therefore, the operation clock can be made faster. Where Tm is the time it takes for the multiplier to process, Ta is the time it takes for the adder to work, and N is the length of the filter coefficients. In the present invention, since the filter is divided into even and odd, the number of registers used can be used independently, so that the coefficient lengths of the even and odd filters are different from each other. The number of registers is reduced compared to other structures.

I. Overall Structure

2 is a block diagram illustrating a structure of a discrete wavelet converter according to the present invention. As shown, first and second even filters 21 and 23, first and second odd filters 22 and 24, rearrange block 25, and input interface 26. ), A control signal block 27, and an output switch 28.

The overall operation is as follows. The filter is divided into an even part and an odd part. When the filter input of the first octave is an even number, the filter input of the upper octave becomes an odd number of samples, and the first octave is an even. Filtering is performed at the upper octave and odd filtering is performed simultaneously. In addition, if the sample input of the first octave is an odd number, the upper octave selects an even value, the first octave performs odd filtering, and the upper octave performs even filtering.

In order to implement three octave filtering using two pairs of even and odd filters as shown in FIG. 1, it is very important to adjust the operation time of the filter and the order of input data. Interface 26 and rearrange block 25 perform. In addition, the operation of selecting the filter output in accordance with the operation order of the filter is performed by the output switch 28, and the control signal block 27 is performed to generate a signal for controlling each block.

II. Input interface

In the input section, inputs from external and rearrange circuits are simultaneously input to two filters (low pass and high pass filters). If the external input is even-numbered, this input is sent to the even filter by a software switch, where the output value of the rearrange circuit (the output of the upper octave) is an odd-numbered index. ), Which is sent to the odd filter by the software switch. Also, if the external input is odd, this input is sent to the odd filter by the software switch, and the output value of the rearrange circuit is sent to the even filter with an even numbered index. .

[Equation 3] to [Equation 16], the input is [a (-3), a (-2), a (-1), a (0), a (1), a (2), a (3),. ], The output of the high pass filter is [b (0), b (1), b (2), b (3),... ], [b (0), d (1),... ], [f (0), f (1),... ], And the final output by the output switch 28 is [b (0), d (0), b (1), f (0), b (2), d (1), b (3), f '(0),... ]. 3 is a diagram illustrating this data flow.

3 is an input / output table in a discrete wavelet structure according to the present invention. This is a table where both the low pass and high pass filters are four taps and three octaves. When Index is 4, input a (4) is even-numbered data, so it is input to an even filter so that output b (2) of the high pass filter becomes the final output. At this time, the input of the odd filter is c (1) which is the output of the rearrangement block, and the output c (2) of the low pass filter is again the input of the rearrangement block.

When Index is 5, input a (5) is odd-numbered data, so it is input to an odd filter, and e (1), which is the output of the low pass filter, becomes an input of a rearrange block again. At this time, the input of the even filter becomes c (2) which is the output of the rearranged block, and the output d (1) of the high pass filter becomes the final output.

When Index is 6, input a (6) is even-numbered data, so it is input to an even filter so that b (3), which is the output of the high pass filter, becomes the final output. At this time, the output of the rearranged block as the input of the odd filter is ignored, and the output c (3) of the low pass filter becomes the input of the rearranged block again.

When Index is 7, input a (7) is odd-numbered data and therefore is input to an odd filter. At this time, the output of the rearrange block becomes the final output as f '(0), and the outputs of the low pass and high pass filters are ignored.

As shown in FIG. 3, the filter operation of the wavelet transform is irregular and arbitrary, but repeats continuously in one cycle of the process of FIG. 3. Rearrange blocks are needed for these irregular and arbitrary filter operations.

III. Rearrange blocks

The output value of the low pass filter is re-entered for the calculation of the next octave. The rearrange block is a circuit that rearranges the output values of the low pass filter in the desired order and sends them to the input interface. That is, if the input of octave 1 is an even numbered sample, the output value of the filter having an odd numbered index is output. If the input of octave 1 is an odd numbered sample, it outputs an output value of the filter having an even numbered index. do.

4 is a block diagram illustrating the structure of a rearrange circuit in a discrete wavelet converter structure according to the present invention, and FIG. 5 is a table illustrating a data flow of a rearrange circuit. In the notation 8 × I + n in FIG. 4, I is an integer value greater than or equal to 0 indicating a period of an index, and {0, 1, 2, 3,... }, And n is an index value, and has 8 values of {0, 1, 2, 3, 4, 5, 6, 7} within one period.

4 is a rearrangement register composed of a three-stage shift register. The first rearrangement register 41 for the operation of the octave 1 stores all the outputs of the low pass filter in the first register 41 except for the last operation (when the index is 7) of the period shown in FIG. do. The second rearrangement register 42 for the operation of the octave 2 outputs the output of the first rearrangement register 41 when the index is {2, 3, 4, 6} in one period shown in FIG. Stored in the second rearrangement register 42. The third rearrangement register 43 for the operation of the octave 3 outputs the output of the second rearrangement register 42 when the index is 5 in one period shown in FIG. 3. This value is the final output of the wavelet converter when the index is 7.

5 is a table illustrating the data flow in the rearrangement register described above.

IV. Filtering circuit

This is the part that actually performs the filtering. In FIG. 1, a filter is divided into two high pass filters and a low pass filter, and each filter may be divided into an even index coefficient and an odd index coefficient.

6 is a structural diagram of a filtering circuit in the structure of a discrete wavelet converter according to the present invention, showing filtering of a lowpass filter. The parts of the highpass filter have the same structure and differ only in the values of the coefficients multiplied by the multiplier. Referring to (61) and (62) of Figure 6 it can be seen that the critical path (critical path) is one multiplier and one adder, it is possible to improve the speed of the operation clock compared to other structures. The second register (63) of FIG. 6 is used to store the operation result for the output of the rearrange block when the input data is odd.

If the number of taps of the filter used is different, the high pass filtering part and the low pass filtering part can be made differently to match each tap number. The number of registers can be reduced compared to the structure.

7 is a table showing the data flow of the filtering circuit. When a (2) which is an even-numbered input is input in (72) of FIG. 7, the sum of the output of R4 and a (2) x h ₀ of (71) of FIG. There is also the output of the register R3 of the portion 71 of 7 and e (-1) × h and the sum of the storage _1, R3 is 71 in Fig. 7 the sum of the output and a ₍₂₎ × h 2 of the R1 register in Is stored, and the value of the R2 register in FIG. In R1, the product of e (-1), which is the output of the rearrange block, and h ₃ is stored.

When the odd numbered input a (3) is input in (73) of FIG. 7, the product of e (0) and h ₀ , which is the output of the rearrange block, the sum and the output of the low pass filter, R4 is the output of the R3 register in 72 of 7 and a (3) is the sum of × h ₁ stores, R3, the output of the R2 register (72) in FIG. 7 This shift is stored, and the sum of the output of the register R1 in Fig. 7 (71) and e (0) x h ₂ is stored in R2. R1 stores the product of a (3) and h ₃ .

As described above, according to the present invention, it is possible to process a video signal at a high speed by improving the operation speed of a circuit, and when the number of coefficients of the Even and odd filters is different, the number of registers used is different than that of other structures. It has a small effect which can reduce the area of the circuit.

Claims (5)

An input interface that inputs an external signal and a signal output from the rearrangement block and simultaneously outputs the signals to the high pass and low pass filters; A low pass filter for outputting a signal generated by performing even filtering or odd filtering according to the signal input to the input interface to the rearrangement block; A high pass filter configured to output a signal generated by performing any one of even filtering and odd filtering according to a signal input from the input interface; A rearrangement block for inputting a signal output from the low pass filter and rearranging the signal in a desired order and outputting the result to an input interface; A control signal block for controlling a rearrangement operation by inputting a control signal to the rearrangement block; A discrete wavelet converter comprising an output switch for inputting the output signal of the high pass filter and selecting the filter output according to the operation order of the filter. The method of claim 1, The rearrangement block may include a first rearrangement register configured to input an output signal of a low pass filter to perform a first octave operation, and to store or output the signal according to a result of the operation; A second rearrangement register for inputting an output signal of the first rearrangement register to perform a second octave operation, and storing or outputting a signal according to a result of the operation; And a third rearrangement register configured to input an output signal of the second rearrangement register to perform a third octave operation, and to store the signal or output the signal to an input interface according to a result of the operation. A first step of inputting an external signal and a signal output from the rearrangement circuit at the input interface and simultaneously outputting them to the high pass and low pass filters; A second step of outputting a signal generated by performing any one of even filtering and odd filtering in the low pass filter inputting the signal of the input interface to the rearrangement block; A third step of outputting a signal generated by performing any one of even filtering and odd filtering in the high pass filter inputting the signal of the input interface to an output switch; A fourth step of rearranging the signals in a desired order in the rearrangement block in which the signals of the low pass filter are input and outputting them to an input interface according to a control signal of a control signal block; And a fifth step of selectively outputting the signal of the high pass filter in accordance with the operation order of the filter. The method of claim 3, wherein In the second step, the odd-numbered signal may be input to perform an odd coefficient and an OR operation, and then stored in a first register. Performing an OR operation on a value stored in the first register with a result value of an AND operation of an even signal and an even coefficient; Storing the result of performing the OR operation in an odd second register; Storing the result of performing the OR operation in an even numbered register; Performing a logical sum of the value stored in the third register with the logical product result of the odd numbered signal and the odd coefficient; Storing a result value of the OR operation in a fourth register; And performing a logical sum of a value stored in the fourth register with a logical product result value of an even-numbered signal and an even coefficient. The method of claim 3, wherein The fourth step includes performing a first octave operation on a first rearrangement register inputting an output signal of a low pass filter; Storing or outputting a signal to a second rearrangement register according to the operation result of the first octave; Performing a second octave operation on a second rearrangement register inputting an output signal of the first rearrangement register; Storing or outputting a signal to a third rearrangement register according to the operation result of the second octave; Performing a third octave operation on a third rearrangement register inputting an output signal of the second rearrangement register; And storing the signal or outputting the signal to the input interface according to the operation result of the third octave.