KR100395614B1 - Two dimensional discrete wavelet transformation apparatus - Google Patents

Abstract

The present invention relates to a two-dimensional discrete wavelet transform apparatus. The 2D discrete wavelet converting apparatus includes: a register array configured to receive and store a digital signal inputted from an external source and a wavelet transformed intermediate result value; A low pass filter performing low pass filtering on the data output from the register array and outputting the intermediate result to the register array if necessary; A high pass filter for performing high pass filtering on the data output from the register array; A low pass filter line buffer for storing data output from the low pass filter; A line buffer for a high pass filter for storing data output from the high pass filter; And a multiplexer for selecting one of output data of the low pass filter line buffer and output data of the high pass filter line buffer and outputting the intermediate result to the register array. According to the present invention, the size of the hardware is reduced by not using longitudinal division for the highest frequency band, and by using a constant multiplier while using LPF and HPF separately, and lateral filtering and longitudinal filtering are performed in the order of completion of the calculation. Alternately, very effective image compression is performed.

Description

Two-dimensional Discrete Wavelet Transformation Device {TWO DIMENSIONAL DISCRETE WAVELET TRANSFORMATION APPARATUS}

The present invention relates to a discrete wavelet transformation apparatus. In particular, a low pass filter (LPF) and a high pass filter (HPF) are used separately, and the size of hardware is reduced by using a constant multiplier. A dimensional discrete wavelet transform apparatus.

Transform coding schemes such as Discrete Cosine Transformation (DCT) among the image compression methods have excellent compression ratios, but block effects occur in reproduction operations because the basis used is discontinuous between blocks. Discrete wavelet transforms have recently been proposed to reduce this block effect.

1 is a block diagram illustrating a basic concept of discrete wavelet transform.

As shown in FIG. 1, the input signal is filtered while passing through the high pass filter (HPF, 1) and the low pass filter (LPF, 2), respectively, and then each half down-sampler (3, 4). The wavelet transform is performed by half downsampling by.

When the original signal is to be restored using the wavelet transformed data as described above, the wavelet transform process may be reversed. That is, the wavelet transformed data is subjected to two upsampling using two upsamplers 5 and 6, and then the original signal is restored by passing through the LPF 7 and the HPF 8, respectively.

On the other hand, since the video signal has a two-dimensional characteristic, the discrete wavelet transform must also be two-dimensional.

2 is a block diagram illustrating the concept of two-dimensional discrete wavelet transform.

As shown in FIG. 2, the input video signal is filtered through the HPF 11 and the LPF 12 in the primary transverse direction and then downsampled by the half downsamplers 13 and 14.

Each result is then filtered back through the HPF (15, 17) and LPF (16, 18) in the secondary longitudinal direction and then downsampled by the half downsampler (19, 20, 21, 22). do.

When this operation is performed, the final image is divided into four subbands, that is, an HH band, an HL band, an LH band, and an LL band.

The HH band mainly contains data of a diagonal image boundary (high frequency component), the HL band mainly contains data of a horizontal image boundary, and the LH band mainly contains data of a vertical image boundary.

The LL band, on the other hand, contains low frequency components that are sensitive to human vision. Thus, since important data components are concentrated in the LL band, data in the high frequency band which is less sensitive to human vision is compressed, and data in the low frequency band which is sensitive to vision is low compressed, so that the two-dimensional discrete wavelet transform compresses the image. It can be applied to.

There are various ways to divide the subbands of the 2D discrete wavelet transform, but in general, the method proposed by Malalat is widely used.

3 is a diagram illustrating the concept of a subband coding method proposed by Mala in discrete wavelet transform.

As shown in FIG. 3, the subband coding method proposed by Mala is a method of intensively coding a low frequency band.

That is, the LL band is further compressed by two levels of the final image generated as a result of the 2D discrete wavelet transform to further form a subband having two levels of depth.

In general, in video compression, subband coding of about 4 to 5 levels results in almost saturation of compression efficiency. Therefore, 4 to 5 levels of subband coding are applied.

FIG. 4 is a diagram illustrating a 2D discrete wavelet transform structure for configuring the subband of FIG. 3.

The two-dimensional discrete wavelet transform structure shown in FIG. 4 is a structure for configuring subbands having three levels of depth, and two wavelet transform structures for forming a subband with one level depths shown in FIG. It is further configured using.

For efficient compression, the filter coefficients of HPF and LPF have been studied by many people. Among them, the Daubechies 9-7 filter is a filter that uses a coefficient of 9 taps with LPF and 7 taps with HPF. There are five types of filter coefficients in LPF and four in HPF. If the coefficient of LPF is g _i and the coefficient of HPF is h _j , the coefficient of each filter is as follows.

g ₀ = 0.602949, g ₁ = 0.266864, g ₂ = 0.078223, g ₃ = 0.016864, g ₄ = 0.026749

--------------------(One)

h ₀ = 0.557543, h ₁ = 0.295636, h ₂ = 0.028772, h ₃ = 0.045636 -------- (2)

When the data of the reference time is d _t based on the time t, the result L _i of the LPF and the result H _{i + 1} of the HPF can be expressed by the following equation.

L _i = g ₀ * d _i + g ₁ * (d _{i + 1} + d _i-1 )-g ₂ * (d _{i + 2} + d _i-2 )-g ₃ * (d _{i + 3} + d _{i -3} ) + g ₄ * (d _{i + 4} + d _i-4 ) -------------------------------- ---- (3)

H _{i + 1} = h ₀ * d _{i + 1} -h ₁ * (d _{i + 2} + d _i )-h ₂ * (d _{i + 3} + d _i-1 ) + h ₃ * (d _{i + 4} + d _i-2 ) ------ (4)

Here, the reason why L _i and H _{i + 1} are alternately calculated is that each filtering result is half-sampled.

Discrete wavelet transforms as described above can represent signals with locality over time and frequency, which is generally advantageous for interpreting video signals with non-identical signals, no blocking effect, high speed, high compression ratio, The transformed region is expressed in multiple resolutions similar to human visual characteristics and can be applied to image compression.

However, since the above-described conventional technology handles both high-band and low-band filtering in one filter, a multiplexer is used for a constant input part of the two inputs of the multiplier, and therefore, a constant multiplier cannot be used. There is a problem that the size is large.

In addition, by using two filters capable of both high-band filtering and low-band filtering, one processes only the transverse direction and the other processes only the longitudinal direction.

In addition, the discrete wavelet transform has a difficulty in considering various aspects in hardware implementation due to the complexity of the conversion scheme. In addition, in order to process an image in real time, the operation speed of hardware must be high, and in order to reduce the manufacturing cost of hardware, a small area VLSI structure is required.

To implement wavelet transformation in hardware, many considerations must be taken into account: the speed of the operating clock, the number of multipliers and adders used, the number of registers to store intermediate values, and the complexity of the interconnects within the circuit.

Accordingly, an object of the present invention is to provide a two-dimensional discrete wavelet transform apparatus that uses LPF and HPF separately and uses a constant multiplier, and alternately processes transverse filtering and longitudinal filtering in the order of completion of the operation. have.

1 is a block diagram illustrating a basic concept of discrete wavelet transform.

2 is a block diagram illustrating the concept of two-dimensional discrete wavelet transform.

FIG. 3 is a diagram illustrating the concept of a subband coding method proposed by Malat in discrete wavelet transform.

FIG. 4 is a diagram illustrating a 2D discrete wavelet transform structure for configuring the subband of FIG. 3.

5 is a diagram illustrating a structure of a Mala block according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a two-dimensional discrete wavelet transform structure for forming the Mala block of FIG. 5.

7 is a block diagram showing the structure of a two-dimensional discrete wavelet converter according to an embodiment of the present invention.

FIG. 8 is a detailed block diagram of the two-dimensional discrete wavelet converter of FIG. 7.

9 is a detailed block diagram of one embodiment of Reg1, Reg2, Reg3, Reg4, Reg5 in the register array 200 of FIG.

FIG. 10 is a diagram illustrating a data flow when data stored in Reg1 of FIG. 9 is a start boundary of an image.

FIG. 11 is a diagram illustrating a data flow when data stored in Reg1 of FIG. 9 is an end boundary portion of an image.

12 is a detailed block diagram of another embodiment of Reg1, Reg2, Reg3, Reg4, Reg5 in the register array 200 of FIG.

FIG. 13 is a diagram illustrating a data flow when data stored in Reg1 210 is a start boundary of an image according to the embodiment of FIG. 12.

FIG. 14 is a diagram illustrating a data flow when data stored in the line buffers 510 and 610 of FIG. 8 is a boundary portion of an image.

In order to achieve the above object, the present invention includes a register array for receiving a digital signal and a wavelet transformed intermediate result value input from the outside; A low pass filter performing low pass filtering on the data output from the register array and outputting the intermediate result to the register array if necessary; A high pass filter for performing high pass filtering on the data output from the register array; A low pass filter line buffer for storing data output from the low pass filter; A line buffer for a high pass filter for storing data output from the high pass filter; And a multiplexer for selecting one of output data of the low pass filter line buffer and output data of the high pass filter line buffer and outputting the intermediate result to the register array.

The register array includes a register for receiving and storing a digital signal input from the outside; A plurality of registers for receiving data output from the low pass filter and the multiplexer and storing the data as intermediate result values; And a second multiplexer for selecting one of data stored in the plurality of registers and outputting the selected one to the low pass filter and the high pass filter.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a diagram illustrating a structure of a Mala block according to an embodiment of the present invention.

The NTSC (National Television Standards Committee) standard is based on processing an image of 720 x 486 and processing 30 frames per second.

If this is processed in field units instead of frame units, 720 x 243 images are processed at 60 fields per second.

In general, the image has a near-square characteristic, and the data component ratio is very low in the high frequency region, and the capacity of the buffer required therein can be reduced. Do not divide by direction. In addition, the subband is composed of five levels of depth.

FIG. 6 is a diagram illustrating a two-dimensional discrete wavelet transform structure for forming the Mala block of FIG. 5.

The 2D discrete wavelet transform structure according to the embodiment of the present invention shown in FIG. 6 is a structure for configuring subbands having 5 levels of depth, and the input image passed through the HPF in the 1st level transverse wavelet transform. The signal is output in the H0 band, which is the highest frequency band, and only the subbands formed by the input video signal passing through the LPF form the following subbands by conventional four-level wavelet transform, according to an embodiment of the present invention. The subbands are finally formed.

7 is a block diagram showing the structure of a two-dimensional discrete wavelet converter according to an embodiment of the present invention.

As shown in FIG. 7, the two-dimensional discrete wavelet converter according to an embodiment of the present invention includes a video signal decoder 100, a register array 200, an LPF 300, an HPF 400, and an LPF line buffer 500. , HPF line buffer 600, and a multiplexer (MUX, 700).

The video signal is converted into a digital signal through the video signal decoder 100 and input to the register array 200, but the present invention is not limited thereto, and the digital video signal output from another video device such as a frame grabber is registered. It may be input to the array 200.

The register array 200 receives the digital signal output from the image signal decoder 100 and the output of the LPF 300 and sequentially stores the data to be processed by delaying them sequentially.

The register array 200 receives the output data of the LPF 300 or the HPF 400 output through the LPF line buffer 500 or the HPF line buffer 600 through the MUX 700.

Data passing through the MUX 700 outputs 9 bytes of data in parallel using Daubechies 9-7 tap filter. The final data output is made through the output of the LPF 300 and the HPF 400, and is not output every time, but selects and outputs a valid data output.

FIG. 8 is a detailed block diagram of the two-dimensional discrete wavelet converter of FIG. 7.

As shown in FIG. 8, the image signal is converted into a digital signal through the image signal decoder 100 and input to the register array 200. In this case, the signal to be converted may be, for example, unsigned 8-bit data, which is stored in Reg1 210 of the register array 200.

Detailed block diagrams of Reg1 210, Reg2 220, Reg3 230, Reg4 240, and Reg5 250 in register array 200 may be implemented in various forms, one embodiment of which 9 is shown.

Since Reg1 (210), Reg2 (220), Reg3 (230), Reg4 (240), and Reg5 (250) all have the same structure, Reg1 (210) will be described here as a representative.

Reg1 210 consists of nine registers 211, 212, 213, 214, 215, 216, 217, 218, 219, and the number of bits in each register 211 to 219 is the input bit of Reg1 210. Same as number. That is, in the case of Reg1 210, since the number of input bits is 8 bits, all nine registers 211 to 219 are eight bit registers.

The nine registers 211 to 219 each have an ld signal which is a load signal to accept a data input. By default, whenever the ld signal occurs, the data stored in register 218 goes to register 219, the data stored in register 217 goes to register 218, and the data stored in register 216 goes to register 217. The data stored in the register 215 is the register 216, the data stored in the register 214 is the register 215, the data stored in the register 213 is the register 214, the data stored in the register 212. Is a register 213, data stored in the register 211 is input to the register 212, while the input from the video signal decoder 100 is shifted to the register 211.

Nine registers 211 to 219 store data for the number of filter taps. The data stored in the nine registers 211 to 219 at the time i + 5 are (d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + 1} , d _i , d _i-1 , d _i-2 , d _i-3 , d _i-4 ). The register values d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + 1} , d _i , d _i-1 , d _i-2 , d _i-3 , d _i-4 3 is used for low pass filtering, and the register values d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + 1} , d _i , d _i-1 , d _i-2 4) is used for high pass filtering.

Reg2 (220), Reg3 (230), Reg4 (240), and Reg5 (250) are registers that store the median value of the filtered operation. The structure is the same as that of Reg1 (210), but the input is 9.7 (bit of integer part). It is different from input in format.

The start signal is a signal for controlling a value input to four registers 216, 217, 218, and 219 of the nine registers 211 to 219, and controls the start boundary of the image.

Since there is no data corresponding to the positions d _i-1 , d _i-2 , d _i-3 , and d _i-4 at the start boundary of the image, the image should be flipped.

Accordingly, the boundary of the image is flipped using the 2x1 multiplexers 221, 222, 223, and 224 and a start signal which is a control signal thereof.

The multiplexer 221 receives the output of the register 215 and the output of the register 217, and inputs one output selected by the start signal to the register 216. The multiplexer 222 is connected to the output of the register 216. Receives the output of the register 218 and inputs one output selected by the start signal to the register 217, the multiplexer 223 receives the output of the register 217 and the output of the register 219 by the start signal The selected output is input to the register 218, and the multiplexer 224 receives the output of the register 218 and an image input and inputs one output selected by the start signal to the register 219.

FIG. 10 is a diagram illustrating a data flow when data stored in Reg1 210 is a start boundary of an image.

As shown in FIG. 10, when the data corresponding to the start of the image is d0, the start signal is kept from the register 211 and the register 219 while being held high for four times the ld signal is applied after d1 is input. Data is collected toward the center register 215.

The hatched portion, which is the point where the start signal falls to the low state, is stored in nine registers 211 to 219 for processing filtering on the boundary of the image.

On the other hand, since there is no data corresponding to d _{i + 1} , d _{i + 2} , d _{i + 3} , and d _{i + 4} , the image should also be flipped. The signal for controlling this is the last signal.

This last signal controls the 2x1 multiplexer 225, the 4x1 multiplexer 226, and the 2-bit counter 227, as shown in FIG.

The 2-bit counter 227 is initially set to "11". The 2-bit counter 227 counts and outputs the number of inputs of the ld signal when the last signal is high.

The 4x1 multiplexer 226 receives the outputs of the four registers 212, 214, 216, and 218 and outputs one output selected by the count value output from the 2-bit counter 227 to the 2x1 multiplexer 225. Will output

The 2x1 multiplexer 225 receives an image input and an output of the 4x1 multiplexer 226 and outputs one output selected by the last signal to the register 211.

FIG. 11 is a diagram illustrating a data flow when data stored in Reg1 210 is an end boundary portion of an image.

In FIG. 11, count represents the value of the two bit counter 227.

The 2-bit counter 227 counts the number of ld signals when the last signal is high, and the resulting value controls the 4x1 multiplexer 226, so that at the first hatched portion (hatched portion). The flip of the image starts, and the flip of the image is completed at the second hatched portion (the hatched portion).

Meanwhile, another embodiment of the structure of Reg1 210 is shown in FIG. 12.

Reg1 210 in this embodiment also consists of nine registers 261, 262, 263, 264, 265, 266, 267, 268, 269, and is associated with the data stored in each register 261-269. The matters described above are the same as the contents described with reference to FIG. 9 and will not be described herein.

The difference between the present embodiment and the above-described embodiment is control in the case where the data input to the Reg 210 is the start boundary portion data of the image.

In the present embodiment, the boundary of the image is flipped using the 2x1 multiplexers 271, 272, 273, 274, the counter and the peripheral circuit 278, and a start signal which is a control signal thereof.

The multiplexer 271 receives the output of the register 262 and an image input, and inputs one output selected by the counter and the peripheral circuit 278 to the register 263, and the multiplexer 272 outputs the register 264. And an output selected by the counter and peripheral circuit 278 to the register 265, and the multiplexer 273 receives the output and the image input of the register 266 to receive the counter and peripheral circuit 278 A single output selected by the register 267 is input to the register 267, and the multiplexer 274 receives an output of the register 268 and an image input and receives one output selected by the counter and the peripheral circuit 278. 269).

The multiplexers 271, 272, 273, and 274 receive control signals from the counter and the peripheral circuit 278. If the control signal is "1", the multiplexer outputs a video input signal. , 264, 266, and 268) are output respectively.

On the other hand, when the start signal is "1" and the counter value count is "11", the counter and the peripheral circuit 278 output "1" to the multiplexer 271, and the other multiplexers 272, 273, 274. When the start signal is "1" and the count value of the counter is "00", the controller outputs "1" to the multiplexer 272. The other multiplexers 271, 273, 274 output "1". 0 ", when the start signal is" 1 "and the counter value count is" 01 "," 1 "is output to the multiplexer 273, and" 0 "is output to the other multiplexers 271, 272, and 274. If the start signal is "1" and the counter value count is "10", "1" is output to the multiplexer 274, and "0" is output to the other multiplexers 271, 272, and 273. do.

FIG. 13 is a diagram illustrating a data flow when data stored in Reg1 210 is a start boundary of an image according to the embodiment of FIG. 12.

As shown in FIG. 13, when the data corresponding to the start of the image is d0, the start signal changes the value of the counter 278 while maintaining a high state for four times the ld signal is applied after d1 is input. When the value of the counter 278 is "11", the peripheral circuit 278 outputs the control signal "1" only to the multiplexer 271. Since the control signal is "1", the multiplexer 271 is an image input d1. Is output to the register 263. Other values of "00", "01", and "10" of the counter 278 operate similarly to the multiplexer 271 with respect to the multiplexers 272, 273, and 274, and thus description thereof will be omitted.

The hatched portion, which is the point where the start signal falls to the low state, is stored in nine registers 261 to 269 for processing filtering on the boundary of the image.

Starting boundary processing in the above manner results in complete boundary flipping not only in the first filtering portion of the hatched portion but also in the previous cycle.

On the other hand, the processing for the end boundary portion of the image in the present embodiment is the same as the above-described embodiment, so it will be omitted here.

Referring back to FIG. 8, the data of the nine registers 211 to 219 of Reg1 210 in which the video signal output from the video signal decoder 100 is stored is connected to the LPF 300 through the 6 × 1 multiplexer 270. Transverse filtering is input to the HPF 400.

First, the filtering by the LPF 300 will be described.

The transverse filtering-related equations performed by the LPF 300 are shown in (3) above.

Reg1 (210) outputs a total of 9 data from d _i-4 to d _{i + 4} , and these are unsigned 8.0 format, and sign '0' is added to 6x1 multiplexer 270 and 7 bits after the decimal point. 0 is added to the 9.7 format to be input to the LPF 300.

The LPF 300 performs filtering in the form of Equation (3) by using nine data output from the register array 200.

The LPF 300 may output data d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + 1} , d _i , d _i-1 , d _i-2 , d _i from the register array 200. _-3 , d _i-4 ) of the corresponding data (d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + 1} , d _i-1 , d _i-2 , d _i-3 , d _{i- Four} adders 311, 312, 313, and 314 that add and output ₄ ) and data output from the register array 200 (d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + 1} , d Pipeline register which stores corresponding data d _i and data output from adders 311, 312, 313, 314 among _i , d _i-1 , d _i-2 , d _i-3 , d _i-4 (pipe 1) 320, five multipliers (331, 332, 333, 334, 335) multiplying the corresponding data among the data stored in the pipeline register 320, multipliers (331, 332, 333, 334, 335 Pipeline register (pipe 2) 340 for storing the data output from the; and accumulator (accumulator) for performing the operation of the equation (3) on the data output from the pipeline register (340) ( 350, the saturation unit and the rounding unit (SatRnd) 360, saturation and rounding to saturate the data output from the accumulator 350 and rounding down to a decimal point The accumulator 370 outputs the data output from the unit 360 as a final result.

The adders 311, 312, 313, 314 are first composed of nine data output from the register array 200 (d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + 1} , d _i , d _{i- 1} , d _i-2 , d _i-3 , d _i-4 ) from (d _{i + 1} + d _i-1 ), (d _{i + 2} + d _i-2 ), (d _{i + 3} + d _i-3 ), (d _{i + 4} + d _i-4 ). The reason why the adders 311, 312, 313, and 314 are used is that nine multipliers are required for the filtering of nine taps, but the number of multipliers can be reduced to five by using the adder.

The format of the data output from the register array 200 is 9.7, and the adders 311, 312, 313, and 314 add two 9.7-format data, so that the format of the data is 10.7.

The resultant values of the adders 311, 312, 313, 314 and the data d _i output from the register array 200 are pipelined to the multipliers 331, 332, 333, 334, 335 through the pipeline register 320. . The resultant values of the adders 311, 312, 313, and 314 that are pipelined are input to the multipliers 331, 332, 333, and 334, respectively, to perform coefficients and operations of the LPF 300.

Since the filter coefficients of the LPF 300 are already determined by Equation (1), a constant multiplier may be used to reduce the size of the multiplier.

Herein, the coefficient of the LPF 300 is assumed to be 12 bits unsigned.

The coefficient of LPF 300 is smaller than 1 and therefore has a 0.12 format. Therefore, the format of the value output by the multipliers 331, 332, 333, and 334 is 10.19, which is an operation format of 10.7 x 0.12.

On the other hand, after the 9.7 format data is pipelined from the register array 200 by the pipeline register 320, the format of the result value multiplied by the multiplier 335 becomes 9.19, which is an operation format of 9.7 × 0.12. .

The output of multiplier 331 is g ₄ * (d _{i + 4} + d _i-4 ), the output of multiplier 332 is g ₃ * (d _{i + 3} + d _i-3 ), and multiplier 333 The output of is g ₂ * (d _{i + 2} + d _i-2 ), the output of multiplier 334 is g ₁ * (d _{i + 1} + d _i-1 ), and the output of multiplier 335 is g ₀ * d _i .

The outputs of multipliers 331, 332, 333, 334, 335 are again pipelined by pipeline register 340.

The accumulator 350 finally performs the operation of Equation (3) on the data pipelined and output by the pipeline register 340. The result is 14.19 format, and the result data is rounded down via SatRnd 360, rounded down to a decimal point, and converted into data in the final 9.7 format.

The result of SatRnd 360 is L0, which is fed back to register array 200 for two-dimensional wavelet transformation.

Next, like the LPF 300, the HPF 400 performs a calculation corresponding to Equation (4).

The HPF 400 performs filtering in the form of Equation (3) using seven data output from the register array 200.

The HPF 400 stores data output from the register array 200 (d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + 1} , d _i , d _i-1 , d _i-2 , d _{i). 3} adders 411, which adds and outputs the corresponding data (d _{i + 4} , d _{i + 3} , d _{i + 2} , d _i , d _i-1 , d _i-2 ) of _-3 , d _i-4 ) 412 and 413 and data output from the register array 200 d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + 1} , d _i , d _i-1 , d _i-2 , d _{i -3, 4-d i)} of the data (d _{i + 1)} and the adder (411, 412, a pipeline register (pipe 3) (420), a pipeline register (420 to store the data outputted from 413)) Four multipliers (431, 432, 433, 434) for multiplying the corresponding data among the data stored in the multiplier, and a pipeline register (pipe 4) 440 for storing data output from the multipliers (431, 432, 433, 434). The accumulator 450 and the accumulator 450 that perform the operation of Equation (4) on the data output from the pipeline register 440 are output from the accumulator 450. The accumulator outputs the data output from the saturation and rounding unit (SatRnd) 460 and the saturation and rounding unit 360 to saturate the data, round down to a decimal point, and convert it to the 9.7 format. 470).

The operation of the HPF 400 is similar to that of the LPF 300, and thus will be described briefly.

First, the adders 411, 412, and 413 output data d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + 1} , d _i , d _i-1 , d from the register array 200. _i-2 , d _i-3 , d _i-4 ) using (d _{i + 2} + d _i ), (d _{i + 3} + d _i-1 ), (d _{i + 4} + d _i-2 ) Compute the value, and d _{i + 1} output from register array 200 is pipelined through pipeline register 420.

The pipelined results are multiplied by multipliers 431, 432, 433, 434 and then pipelined back through pipeline register 440.

The pipelined results are finally filtered through the accumulator 450 and SatRnd 460 and output.

At this time, the output result is finally output through the accumulator 470, which corresponds to the H0 on the Mala block according to the embodiment of the present invention.

Meanwhile, L0 which is a result value filtered by the LPF 300 is input to and stored in Reg2 220 of the register array 200.

The values input to Reg2 220 are again selected through 6 × 1 multiplexer 270 and then input to LPF 300 and HPF 400 to repeat the lateral filtering as described above.

Next, the lateral filtered results by the LPF 300 and the HPF 400 should be filtered in the longitudinal direction again.

At this time, since the result values for nine lines are needed to perform the filtering in the longitudinal direction, the result values of the image are obtained by using the line buffers 500 and 600 corresponding to the LPF 300 and the HPF 400. Save it.

If the size of the image is N × M, since two filtering and two downsampling are performed, a line buffer having a size of N / 4 × 8 lines × 16 bits is required. These line buffers are required for LPF 300 and HPF 400 respectively, and L_LB1 510 and H_LB1 610 are the corresponding line buffers.

Meanwhile, since nine line data are stored in the line buffers 510 and 610 and then output to the register array 200, since the ninth line data can directly use the filtered result, the number of lines of the line buffer is eight lines. The output is 9 lines are output to the register array 200 at the same time.

The line buffers 510 and 610 also need to process image boundaries as described with respect to Reg1 210 in the register array 200.

Filtering should be processed from the moment 4 images are filled in the line buffers 510 and 610 and 5 images are input. D _i-1 , d _i-2 , d _i-3 , d _i-4 Since there is no data corresponding to the position of, processing for the starting boundary is required for this.

4x1 multiplexers 550 and 650 in line buffers 500 and 600 perform this image boundary processing.

The description of the image boundary processing described above is similar to that in Reg1 210 of the register array 200 and thus is omitted here. FIG. 14 is a diagram illustrating a change in output of the line buffers 510 and 610 at the boundary of the image, and illustrates the change in output at the start boundary and the change in output at the end boundary, respectively.

On the other hand, the longitudinal filtering should be performed twice for low pass filtering by LPF 300 and high pass filtering by HPF 400.

First, the high pass filtered result by the HPF 400 is stored in the H_LB1 610 of the HPF line buffer 600, and a total of 9 lines from the H_LB1 610 when the ninth line is input to the H_LB1 610. Output is selected through a 4x1 multiplexer 650 and input to a 2x1 multiplexer 700.

Since longitudinal filtering on the output of the current HPF 400 must be performed, the 2x1 multiplexer 700 inputs the output from the HPF line buffer 600 to Reg6 260 of the register array 200.

Reg6 260 of the register array 200 is a register that simultaneously stores nine 16-bit data.

The data of Reg6 260 is input to the LPF 300 and the HPF 400 through the 6 × 1 multiplexer 270 to perform longitudinal filtering.

As a result of performing the longitudinal filtering, the result of the LPF 300 is the actin block HL1 according to the embodiment of the present invention, and the result of the HPF 400 is the actin block HH1. The actin blocks HL1 and HH1 are output as final results through the accumulators 370 and 470.

Next, the low pass filtered result by the LPF 300 is stored in the L_LB1 510 of the LPF line buffer 500 and then the register array 200 through the 4x1 multiplexer 550 and the 2x1 multiplexer 700. ) Is input to Reg6 (260).

Data stored in Reg6 260 is input to LPF 300 and HPF 400 through 6 × 1 multiplexer 270 to perform filtering.

As a result of performing the longitudinal filtering, the result of the LPF 300 is the Mala block LL1 according to the embodiment of the present invention, and the result of the HPF 400 is the Mala block LH1. The actin block LH1 is output as the final result through the accumulator 470 of the HPF 400, but the actin block LL1 is again subjected to two-dimensional wavelet transformation to be partitioned into HH2, LH2, HL2, and LL2. The lateral and longitudinal filtering as described above is inputted to Reg3 230 of 200 and repeated.

When this type of operation is repeatedly performed, a Mala block according to an embodiment of the present invention can be obtained.

The L_LB2 520 and H_LB2 620 of the line buffers 500, 600 require a capacity of N / 8 x 8 lines x 16 bits, and the L_LB3 530 and H_LB3 630 are N / 16 x 8 lines. A capacity of 16 bits is required, and L_LB4 540 and H_LB4 640 require a capacity of 16 bits of N / 32 x 8 lines.

Thus, the total capacity of the LPF line buffer 500 and HPF line buffer 600 is 2 × (N / 4 + N / 8 + N / 16 + N / 32) × 8 lines × 16 bits = 15N / 32 × 8 Line x 16 bits are required.

In the NTSC standard, 27 MHz 8-bit pixels are input in a 4: 2: 2 format of Y, Cb, and Cr.

In the case of Y, it is entered at 13.5 MHz, which requires 13.5 / 2 MHz of operation to split the first level Mala block.

Again, splitting the 2nd level actin block requires 13.5 / 4 MHz + 2 × 13.5 / 8 MHz, and splitting the 3rd level actin block requires 13.5 / 8 MHz + 2 × 13.5 / 16 MHz. 13.5 / 16 MHz + 2 × 13.5 / 32 MHz operations are needed to split the fourth level actin blocks, and 13.5 / 32 MHz + 2 × 13.5 / 64 MHz operations are needed to divide the fifth level actin blocks. Operation is required.

Adding all these operations requires 13.5 × (1/2 + 1/2 + 1/4 +1/8 +1/16) MHz. Accordingly, the two-dimensional discrete wavelet converter according to the embodiment of the present invention enables all the above processes when operating at 27 MHz.

Similarly, since Cb and Cr are input at 6.75 MHz, the Cb and Cr can be processed simultaneously by the two-dimensional discrete wavelet converter of the present invention which also operates at 27 MHz.

Although the present invention has been described with reference to the most practical and preferred embodiments, the present invention is not limited to the above disclosed embodiments, but also includes various modifications and equivalents within the scope of the following claims.

According to the present invention, by using the LPF and HPF separately, and by using a constant multiplier, the size of the hardware is reduced, and the lateral filtering and the longitudinal filtering are alternately processed in the order in which the operation is completed, so that very effective image compression is performed.

Claims (11)

(Correct) a register array containing multiple registers, where a register array is A register for storing a digital signal input from the outside; One or more registers storing intermediate values for the next level of wavelet transform; And Register that stores the intermediate value for the longitudinal wavelet transform Comprising; A low pass filter performing low pass filtering on the data output from the register array and outputting the data of the corresponding subband, and outputting the result to the register array as an intermediate result value for the next level wavelet transform; A high pass filter configured to perform high pass filtering on the data output from the register array and output the data of the corresponding subband; A low pass filter line buffer for storing the data output from the low pass filter and outputting the data to the register array as an intermediate value for longitudinal wavelet conversion; A line buffer for storing the data output from the high pass filter and outputting the data to the register array as intermediate values for longitudinal wavelet conversion; And A multiplexer which selects one of the output data of the line buffer for the low pass filter and the output data of the line buffer for the high pass filter and outputs to the register array 2D discrete wavelet converting apparatus comprising a. (Correction) The method according to claim 1, In the register array, The register for receiving and storing the digital signal input from the outside is a first register, Registers for receiving and storing intermediate values output for the next level wavelet transform from the low pass filter are second, third, fourth and fifth registers, The register for storing the intermediate value for the longitudinal wavelet conversion is a sixth register for receiving and storing data output from the multiplexer Characterized in that, A second multiplexer, wherein the register array selects one of the data stored in the first, second, third, fourth, fifth, and sixth registers and outputs to the low pass filter and the high pass filter; Two-dimensional discrete wavelet conversion device further comprising. The method of claim 2, The first register is A plurality of registers for sequentially storing input data and outputting the data to the second multiplexer if necessary; A start boundary processor configured to flip the corresponding image when the data stored in the plurality of registers is data corresponding to a start boundary of the image; And If the data stored in the plurality of registers is the data corresponding to the end boundary of the image, the end boundary processing unit for flipping the corresponding image Including, The second register, the third register, the fourth register and the fifth register have the same structure as the first register. Two-dimensional discrete wavelet transform device. The method of claim 3, The plurality of registers are composed of nine registers, The start boundary processing unit A third multiplexer for selecting one of data output from the fifth register and the seventh register among the nine registers and outputting the selected one to the sixth register; A fourth multiplexer for selecting one of data output from the sixth register and the eighth register among the nine registers and outputting the selected one to the seventh register; A fifth multiplexer for selecting one of the seventh register and the data output from the ninth register among the nine registers and outputting the selected one to the eighth register; And A sixth multiplexer for selecting one of the data output from the eighth register and the input data among the nine registers and outputting the selected one to the ninth register 2D discrete wavelet converting apparatus comprising a. The method of claim 3, The plurality of registers are composed of nine registers, The start boundary processing unit A counter circuit unit for counting an input number of a specific signal and outputting a control value corresponding to the count value; A third multiplexer which receives data output from a second register of the nine registers and the input data, selects one of the input data according to a control value output from the counter circuit unit, and outputs the selected one to a third register; A fourth multiplexer which receives data output from a fourth register of the nine registers and the input data, selects one of the input data according to a control value output from the counter circuit unit, and outputs one of the input data to a fifth register; A fifth multiplexer which receives data output from the sixth register of the nine registers and the input data, selects one of the input data according to a control value output from the counter circuit unit, and outputs the selected one to the seventh register; And A sixth multiplexer which receives data output from an eighth register among the nine registers and the input data, selects one of the input data according to a control value output from the counter circuit unit, and outputs the selected one to the ninth register 2D discrete wavelet converting apparatus comprising a. The method according to claim 4 or 5, The end boundary processing unit A counter for counting and outputting an input number of a specific signal; A seventh multiplexer which receives data output from the second register, the fourth register, the sixth register, and the eighth register of the nine registers, and selects one of the input data according to the count value output from the counter; ; And An eighth multiplexer for selecting one of the input data and data output from the seventh multiplexer and outputting the selected one to the first register among the nine registers 2D discrete wavelet converting apparatus comprising a. The method of claim 1, The low pass filter A plurality of adders for adding and outputting specific data among data output from the register array; A first pipeline register configured to store specific data among data output from the register array and data output from the plurality of adders; A plurality of multipliers for multiplying and outputting specific data among data stored in the first pipeline register; A second pipeline register for storing data output from the plurality of multipliers; A first accumulator for performing final addition and subtraction operations on a low pass filter on data output from the second pipeline register; An saturation unit for the data output from the first accumulator, saturation of the integer part, rounding down to a decimal point, converting to a specific format, and outputting to the register array unit and the low pass filter line buffer; Rounding part; A second accumulator storing data output from the saturation and rounding unit and outputting the final result 2D discrete wavelet converting apparatus comprising a. The method of claim 1, A plurality of adders which the high pass filter adds and outputs specific data of data output from the register array; A third pipeline register configured to store specific data among data output from the register array and data output from the plurality of adders; A plurality of multipliers configured to multiply and output specific data among data stored in the third pipeline register; A fourth pipeline register for storing data output from the plurality of multipliers; A third accumulator for performing specific addition and subtraction operations on the data output from the fourth pipeline register; A saturation unit and a rounding unit for saturating the data output from the third accumulator, rounding down the decimal point, converting the data into a specific format, and outputting the result to the line buffer for the high pass filter; A fourth accumulator for storing data output from the saturation and rounding unit and outputting the final result as a final result 2D discrete wavelet converting apparatus comprising a. The method according to claim 7 or 8, And the plurality of multipliers are constant multipliers. The method of claim 1, The low pass filter line buffer A plurality of line buffers for receiving and storing data output from the low pass filter; And A ninth multiplexer for selecting one of data output from the plurality of line buffers and outputting the selected multiplexer 2D discrete wavelet converting apparatus comprising a. The method of claim 1, The high pass filter line buffer A plurality of line buffers for receiving and storing data output from the high pass filter; And A tenth multiplexer for selecting one of data output from the plurality of line buffers and outputting the selected multiplexer 2D discrete wavelet converting apparatus comprising a.