JPH05283979A - Fir type filter - Google Patents

Abstract

PURPOSE:To save necessary number of memory in a thinning filer and a rate conversion filer for which a FIR filter is used. CONSTITUTION:When the thinning of 4 (=m):1 is performed by a 12th (=n) order FIR filter, a shift register 1 shifting factors a0 to a12 is provided and an IIR section is connected respectively with every 4 taps of the shift registers 1. The output of the IIR section is successively selected by a rotary selector S and output data yk is taken out from the rotary selector S. Each IIR section is composed of multipliers multiplying input data xk by the factors alpha0, alpha1, alpha2, a memory delaying the output of the multipliers and an adder adding the output of the memory and the output of the multipliers. Further, in the IIR section, switches SW0 to SW2 selectively supplying the output from the adder and the output from the multipliers to the memory are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FIR type filter, and more particularly to an FIR type filter in which a required memory amount is reduced.

[0002]

2. Description of the Related Art As a FIR filter, a non-recursive filter shown in FIG. 1 is known. In the figure, a triangular block represents a multiplier, a rectangular block represents a memory having a delay amount of D, and a circular block represents an adder. The notation of these blocks is the same in the following description. The FIR type filter of FIG. 1 has an output y _k represented by the following equation.
Is well known to occur.

[0003]

[Equation 1]

As described above, the n-th order FIR type filter of the conventional non-recursive structure requires n memories. On the other hand, a method has been proposed in which a memory can be reduced to n / m when performing m: 1 decimation by using a cyclic configuration that stores only the intermediate result of convolution. This cyclic configuration produces an output represented by the following equation.

[0005]

[Equation 2]

The w _k can be composed of a cyclic circuit having time-varying coefficients as shown in FIG. That is, the memory is reset (cleared) at time k−n, the multiplier coefficient α is set to α = a _n , and the multiplication result a _n x _kn is taken into the memory. Thereafter, until time k, cyclic calculation is performed while changing α as follows.

From the time of k + 1, again, when α is changed from a _n to a _{0 in the same} manner as described above, w _{k + n} = a ₀ x _{k + n} + a ₁ x _{k + n-1} + a ₂ x _{k + n-2} + ... + a _n x _{k + 1} is obtained.

On the other hand, as for the output, y _k = w _k y _{k + n} = w _{k + n} y _{k + 2n} = w _{k + 2n} ... Obtained in a mold configuration.

As a FIR type filter, one having a symmetrical coefficient is known. In the conventional non-cyclic configuration, the number of multipliers can be reduced by modifying the non-cyclic configuration shown in FIG. 3 into the configuration shown in FIG.

[0010]

The previously proposed recursive configuration that saves memory changes the convolution formula, requires two multipliers, and increases the number of multiplications. was there.

Therefore, an object of the present invention is to provide a FIR type filter which can save memory with a cyclic structure and which can make the multiplier and the number of multiplications equal to those in the conventional case.

[0012]

According to a first aspect of the present invention, a shift register in which a plurality of coefficients are cyclically shifted, a plurality of IIR sections for multiplying an input digital signal by a coefficient from the shift register, and an IIR section are provided. Comprised of a rotary selector that sequentially selects the section output, and IIR
The section comprises a multiplier that multiplies the input digital signal and the coefficient from the shift register, a memory that delays the output of the multiplier, and an adder that adds the output of the memory to the output of the multiplier. Is an FIR filter including a switch that selectively supplies the output from the adder and the output from the multiplier to the memory.

According to a second aspect of the present invention, the shift register is a FIR type filter which comprises a plurality of shift registers corresponding to a plurality of IIR sections and cyclically supplies corresponding coefficients to each IIR section.

According to a third aspect of the present invention, at least one of the IIR sections has a multiplier for multiplying an input digital signal by a coefficient from a shift register, a memory for delaying an output of the multiplier, and a multiplier for multiplying an output of the memory. The output from the adder and the output from the adder and the multiplier,
A switch for selectively supplying to the memory,
The IR section is a FIR type filter including a multiplier that multiplies an input digital signal by a coefficient from a shift register, a memory that delays the output of the multiplier, and an adder that adds the output of the memory to the output of the multiplier. Is.

[0015]

When the thinning-out or the rate conversion is performed, the required memory amount can be saved, and the frame memory for the processing in the time direction or the line memory for the processing in the vertical direction can be saved. Further, the IIR section only needs to be provided with one multiplier, and the hardware can be simplified.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. With the previously proposed cyclic configuration shown in FIG. 2, every nth output is obtained. The example of the nth-order filter shown in FIG. 5 realizes the above calculation, and further,
The output y _k can be obtained, including the output between them.

In FIG. 5, reference numeral 1 is a shift register for cyclically giving a coefficient to a multiplier. This coefficient is supplied to the multipliers included in each of the n sets of IIR sections. The outputs of the n sets of IIR sections are supplied to the input terminals s0, s1, ..., Sn of the rotary selector (or multiplexer) S, respectively. The output y _k is taken out from the rotary selector S. In the configuration shown in FIG. 5, the coefficient stored in the shift register 1 is shifted every one clock, the selection of the rotary selector S is shifted every one clock, and the memory of the circuit selected by the rotary selector S is reset. Output y
_k is obtained.

[0018] Here, the output in the case of the FIR type filter (n = 4) _{is, y k = a 0 x k} + a 1 x k-1 + a 2 x k-2 + a 3 x k-3 + a 4 x k _-4 . In this example, the memory contents w _{0 to} w ₄ of the five sets of IIR sections change as shown in FIG. The contents w _{0 to} w ₄ of the memory are reset at the timing when the output is taken out.

The output sequence is as follows. y ₄ = w _0,3 + a ₀ x ₄ , w _0,4 = 0, w _0,5 = a ₄ x ₅ y ₅ = w _1,4 + a ₀ x ₅ , w _1,5 = 0, w _{1, 6 = a 4 x 6 y 6} = w 2,5 + a 0 x 6, w 2,6 = 0, w 2,7 = a 4 x 7 y 7 = w 3,6 + a 0 x 7, w 3,7 _{= 0, w 3,8 = a 4} x 8 y 8 = w 4,7 + a 0 x 8, w 4,8 = 0, w 4,9 = a 4 x 9 output y ₉ is, w ₀ is stored After the existing memory is reset, the data stored in this memory is used to give y ₉ = w _0,3 + a ₀ x ₉ ... And so on.

Further, when the symmetrical coefficient filter is constructed according to the present invention, it is possible to reduce the number of cyclic loops by devising the timing control. FIG. 7 corresponds to (a in FIG.
₀ = a ₄ , a ₁ = a ₃ ). That is,
The output y ₄ is the contents w ₀ and a ₀ of the memory at time t ₄ .
Given as the sum of x ₄ . At this time, the value stored in w ₄ is also a ₀ x ₄ , so if a ₀ x ₄ is added after reading the output of w ₀ , the memory w ₄ becomes unnecessary and a set of IIR sections can be created. It can be omitted. However, since it is necessary to read the value stored up to t ₃ and write a ₀ x _{4 at} the time t ₄ , the circuit is required to operate at twice as high speed.

More specifically, w ₀ is reset during t ₄ and then loaded after the value of a ₀ x ₄ is fixed, or, as shown in FIG. 8, switches SW _{0 to} SW.
₃ is provided and a ₀ x ₄ is loaded into the memory in the latter half of the interval of t ₄ . In FIG. 8 and the block diagrams described below, the reset signal supply path to the memory is omitted.

FIG. 9 shows a calculation process when the input data series x _k is thinned out to 4: 1 by (n = 12, 13 taps).
X ₀ , x ₄ , x ₈ , x ₁₆ , x ₂₀ , ... in the input data series
The value of the output data series y _k is formed at the timing of. That is, the output data series y _k is y _k = a ₀ x _k + a ₁ x _k-1 + ... + a ₁₂ x _k-12

As an example, the calculation when x ₁₂ is: y _k = w ₀ + a ₀ x ₁₂ w ₁ = w ₁ + a ₄ x ₁₂ w ₂ = w ₂ + a ₈ x ₁₂ w ₀ = a ₁₂ x ₁₂

The calculation at the time of x ₁₃ is: w ₁ = w ₁ + a ₃ x ₁₃ w ₂ = w ₂ + a ₇ x ₁₃ w ₀ = w ₀ + a ₁₁ x ₁₃

The calculation at the time of x ₁₄ is as follows: w ₁ = w ₁ + a ₂ x ₁₄ w ₂ = w ₂ + a ₆ x ₁₄ w ₀ = w ₀ + a ₁₀ x ₁₄

The calculation for x ₁₅ is as follows: w ₁ = w ₁ + a ₁ x ₁₅ w ₂ = w ₂ + a ₅ x ₁₅ w ₀ = w ₀ + a ₉ x ₁₅

The calculation at the time of x ₁₆ is y _{k + 1} = w ₁ + a ₀ x ₁₆ w ₂ = w ₂ + a ₀ x ₁₆ w ₀ = w ₃ + a ₈ x ₁₆ w ₁ = a ₁₂ x ₁₆

FIG. 1 shows a configuration for realizing the calculation shown in FIG.
It shows in 0. Although this is basically the same as the configuration in FIG. 8, since it is a thinning filter, an arithmetic circuit is connected to the shift register 1 in which the coefficients are stored, for every four taps.

In the case of coefficient symmetry, that is, (a ₀
= A ₁₂ , a ₁ = a ₁₁ , a ₂ = a ₁₀ , a ₃ = a ₉ , a ₄ =
In the case of _{a 8, a 5 = a 7} ), operation is performed as follows.

As described above, in the decimation filter, the circuit configuration is simpler in the recursive configuration than in the non-recursive configuration, and when the nth-order FIR filter is thinned to m: 1, the output of the filter is reduced. You can take out every m. Further, although there are various forms in the case of the cyclic structure, in any case, the symmetric coefficient filter has [n / 2] +1 multipliers, n adders, and n memories. Needed. According to the cyclic configuration, since it is sufficient to take out the output every m, it can be realized by [n / m] +1 set of cyclic circuits.

Next, some examples in which the present invention is applied to the conversion of the sampling rate will be described. The following is to convert the sampling rate to m: p, and not only (m> p) but (m <p) (however,
Even when m ≠ 1), rate conversion can be performed.

In order to convert the m: p sampling rate, first, the rate is interpolated by a factor of p, and then thinning is performed to extract every mth output. As a result, the sampling rate is p / m times the original rate. Now, n order (n
Consider the calculation order when p / m rate conversion is performed by a (+1 tap) filter. However, a coefficient symmetric filter is assumed.

More specifically, the case where the rate conversion of 3 (= m): 4 (= p) is performed by the 15 (= n) th order filter will be described. In this example, as in the calculation shown in FIG. 11, the input data series is converted to a rate four times higher and the value is taken out every three bits. This can be realized by the configuration in FIG. The number of IIR sections is determined in consideration of the number of IIR sections in the vertical direction of the shift register 1 shown in FIG. Generally, the IIR section (the number of memories to store) is represented by the following equation using n and m.

M _s = [(n-1) / m + 1] [] is a Gaussian parenthesized expression and represents the maximum integer not exceeding that number.

In the example of FIG. 11, (n = 15), and when (n = 13, 14, 15), [(n-1) / 3 + 1] = 5.

The number i of the coefficient a _i of each IIR section
Is reduced by 4 (= p) each time _k of x _k is increased. Also, as j of w _j of each IIR section increases by 1, it increases by 3 (= m).

Next, the filter order is set to n ₁ . When n ₁ = m × m _s n ₁ is larger than _n , the values of a _{n + 1 to} a _n1 are set to 0. When n is divisible by m, n ₁ and n are equal.

Now consider the coefficient α _j used in the IIR section from 0 to _{m s -1} . 0th I
The coefficients a _{i of the} IR section are x ₀ , x ₁ , x ₂ , ...
_.. , x _k , a ₀ , a _n1-p , a _n1-2p , ...
., Take values of a _n1-kp . However, when n ₁ -kp becomes 0, it is output via the switch S and a
_The value multiplied by _n1 is tilted to the side of the switch SW and stored in the memory. When n ₁ > n, it is only necessary to reset the memory.

Consider the coefficient of the non-zero jth IIR section. The coefficient of the j-th IIR section is
For x ₀ , x ₁ , x ₂ , ..., A _jm , a _jm-p , a
_It takes the value of _jm-2p . However, jm-kp is p
If it becomes smaller, it outputs through switch S and resets the memory. After that, n ₁ is added to jm-kp and p is subtracted.

The coefficient shift register 1 is set up such that when n ₁ is divisible by p, a portion of a _i circulates in each IIR section. When n ₁ is not divisible by p as in the example of FIG. 11, the order of a _i is set as shown in FIG. 12 and the shift is performed as one shift register. Then, each IIR section extracts a coefficient from the middle of the shift register 1.

In the configuration of FIG. 12, each multiplier α _j has a ₀ ,
When a ₁ , a ₂ , a ₃ come, it outputs, and when it is a ₀ , the switch SW _j is tilted sideways to store the product of a ₀ and x _kk in the memory, and the other a ₁ , a ₂ , when the a _3,
Reset the memory after outputting.

The transfer function of the nth-order FIR filter is expressed by the following equation.

[0043]

[Equation 3]

As can be seen from FIG. 11, the filter which is convolved with the non-zero actual data (indicated by an arrow) is the prototype filter of the above equation.
It is called a polyphase filter. When thinning out to m, the above equation is divided into m polyphase filters. That is, the transfer function is represented by the following equation.

[0045]

[Equation 4]

The coefficient a _{im + j} decomposed by this polyphase filter is used as the coefficient of each IIR section.

When n is divisible by m, for example (n =
12) When the (4: 3) rate conversion is performed by the next filter, the processing of FIG.
Made in the circuit. The number of IIR sections is four. The number i of the coefficient a _i of each IIR section decreases by 4 (= p) each time _k of x _k increases. In the case of (n = 12), since it is divisible by 4, a _i can be separately circulated in each IIR section. As can be seen from FIG. 14, the same fixed polyphase filter coefficient is always used for each IIR section. However, when n is not divisible by m,
As shown in FIG. 12, after output, different polyphase filter coefficients are used. Note that FIG. 15 corresponds to FIG.
4 shows the operations of the switches SW ₀ and S in FIG. This switch S operates at 4/3 of the rate of x _k .

FIG. 16 shows a circuit for general m: p rate conversion. The number of IIR sections in this circuit is expressed by the following equation. m _s = [(n-1) / m + 1]

The coefficients of each IIR section change as shown. Here, when the coefficient of the 0th polyphase filter is used, the switch SW _j after the output is laid horizontally and the product of x _k and a ₀ (= a _n ) is stored in the memory. When the coefficients of other polyphase filters are used, the memory is reset after outputting, and the convolution by the next polyphase filter is prepared.

[0050]

According to the present invention, the number of memories can be reduced by using a cyclic structure (IIR section) when performing thinning or rate conversion. In particular, in the processing in the time direction, the memory is a frame memory, and in the processing in the vertical direction, the memory is a line memory,
The effect of reducing the number of them is great, and the hardware scale can be reduced when constructing a high-order filter. Further, in the cyclic structure, only one multiplier is required, which has the advantage of simple structure.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an example of an FIR filter to which the present invention can be applied.

FIG. 2 is a block diagram of a previously proposed IIR section.

FIG. 3 is a block diagram of an example of a coefficient symmetric FIR filter.

FIG. 4 is a block diagram of an example of a coefficient symmetric FIR filter.

FIG. 5 is a block diagram of an example of an FIR filter according to the present invention.

FIG. 6 is a schematic diagram showing processing of the configuration of FIG.

FIG. 7 is a schematic diagram illustrating processing of a coefficient symmetric filter.

FIG. 8 is a block diagram of an example of a coefficient symmetrical filter.

FIG. 9 is a schematic diagram showing processing of a thinning filter according to the present invention.

FIG. 10 is a block diagram showing a configuration of a thinning filter according to the present invention.

FIG. 11 is a schematic diagram showing processing of an example of the rate conversion filter according to the present invention.

FIG. 12 is a block diagram of an example of a rate conversion filter according to the present invention.

FIG. 13 is a schematic diagram showing processing of another example of the rate conversion filter according to the present invention.

FIG. 14 is a block diagram of another example of the rate conversion filter according to the present invention.

FIG. 15 is a schematic diagram for explaining processing of another example of the rate conversion filter according to the present invention.

FIG. 16 is a block diagram showing a general configuration of a rate conversion filter according to the present invention.

[Explanation of symbols]

 Shift register that stores 1 coefficient

Claims (3)

[Claims] 1. A shift register in which a plurality of coefficients are cyclically shifted, a plurality of IIR sections for multiplying an input digital signal by a coefficient from the shift register, and a rotary circuit for sequentially selecting an output of the IIR section.
The IIR section comprises a selector, a multiplier for multiplying the input digital signal by the coefficient from the shift register, a memory for delaying the output of the multiplier, and an output of the register for output of the multiplier. And a switch for selectively supplying the output from the adder and the output from the multiplier to the memory in the FIR type filter. 2. The FIR type filter according to claim 1, wherein the shift register comprises a plurality of shift registers corresponding to the plurality of IIR sections, and a corresponding coefficient is cyclically provided for each IIR section. FIR type filter to supply. 3. The FIR type filter according to claim 2, wherein at least one of the IIR sections includes a multiplier for multiplying an input digital signal by a coefficient from the shift register, and an output of the multiplier. A memory for delaying, an adder for adding the output of the memory to the output of the multiplier, and a switch for selectively supplying the output from the adder and the output from the multiplier to the memory, The other IIR section includes a multiplier that multiplies an input digital signal and a coefficient from the shift register, a memory that delays the output of the multiplier, and an adder that adds the output of the memory to the output of the multiplier. FIR type filter consisting of a vessel.