JPH0730374A - Digital filter with delay function - Google Patents

Abstract

PURPOSE:To obtain the digital filter with the variable delay function. CONSTITUTION:While M of N taps TP1-TPN of the digital filter are assigned to the delay function, the remaining (N-M) taps are assigned to a filter function. Then a series of filter coefficients FC1-FCN-M consisting of (N-M) coefficients are applied to multipliers for the taps used for the filter function and delay coefficients DC1-DCM of 0 are applied to multipliers for the taps used for the delay function.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter, and more particularly, to an acyclic or FIR (Infini
te Impulse Response) filter.

[0002]

2. Description of the Related Art Conventionally, when different delay times are given to digital signals output from a digital filter, for example, a digital filter as disclosed in Japanese Patent Laid-Open No. 60-241314, the filter output is used. It is usual to provide a delay circuit separately from the filter. As such a delay circuit, a delay line with a tap, a shift register, or a variable delay circuit as disclosed in Japanese Patent Application Laid-Open No. 1-154619 can be used.

[0003]

In the above method, a delay element other than the digital filter element or a complicated delay circuit must be used. Therefore, it is an object of the present invention to provide a method and apparatus that realizes both a filter function and a variable delay function more easily. Another object of the present invention is to provide a digital filter having a variable delay function.

[0004]

To achieve the above object, in the non-recursive digital filter having a predetermined number of taps for receiving a digital signal and outputting a filtered digital signal according to the present invention, a) the predetermined A second number of taps that is less than the first number by a number for the filter function, b) the first number of taps for a delay function, and c) the second number. A series of filter coefficients to be applied to each of the taps adjacent to each other and a zero coefficient to be applied to the remaining first number of taps, d) said series of coefficients By applying each of these to the corresponding tap, both the filter function and the delay function are realized.

In a non-recursive digital filter having a predetermined number of taps for receiving a digital signal and outputting a filtered digital signal, the method of realizing both the filter function and the delay function according to the present invention is a) Apply a corresponding one of a series of filter coefficients for a given filter function to a second number of said taps adjacent to each other that is a first number less than said given number; For a number of said taps, a zero coefficient for the delay function is applied.

According to the present invention, the coefficient can be selected from a plurality of series of coefficients that give different delays from each other. Also, the first number of taps may be the number required to provide the maximum of the delays provided by the series of coefficients. Further, the series of filter coefficients can be selected because they give desired filter characteristics.

Further, a digital filter of a predetermined number of taps for receiving an input data word of a predetermined number of bits and generating a filtered output data word provided by the present invention is: a) to receive the input data word Input data shift register means comprising connected one cell having a width of the predetermined number of bits, the input data shift register outputting the held input data word as a first input data word; ) A second number of a series of filter coefficient data words, each word having the same number of bits as the predetermined number of bits, and a second number smaller than the predetermined number of taps by a first number, for use in the filter function, and a delay function. , Each word having the same number of bits as the predetermined number of bits and at least one delay factor of the first number. A coefficient data generating means for sequentially generating one coefficient data word from a series of coefficient data words, and c) coefficient data shift register means connected to receive the coefficient data word generated by the coefficient generating means. A coefficient data shift register means having a width of the predetermined number of bits and having the same number of cells as the predetermined number of taps, the shift operation being in synchronization with the input data shift register means; Each of the cells holds and outputs the predetermined number of bits of the first coefficient data word representing a coefficient to be applied to the first input data word, and d) the predetermined number of taps, and A plurality of multiplication and addition means of the same number, each of the plurality of multiplication and addition means comprising: a first input data word; A coefficient data shift register for receiving the first coefficient data word generated by a corresponding cell of the plurality of cells, the received first input data and the first coefficient Generating a product data word representing a product, and adding a plurality of products of the same number as the predetermined number of taps sequentially generated in this way to generate a sum data word representing a sum of the results; And multiplication and addition means of.

According to the present invention, the first number can be 1 or more. Further, the coefficient generating means is
A) storage means for storing a plurality of the coefficient data words for giving different delays, and b) for selecting one of the plurality of coefficient data words stored in the storage means. And (c) counter means for sequentially reading the coefficient data words forming the selected one series of coefficient data words in a cyclic manner.
Can be composed of Furthermore, the plurality of multiplication and addition means a) a plurality of accumulators that output the sum data word and have the same number as the predetermined number of taps;
A multiplexer connected to receive a plurality of the sum data words, wherein the sum data word is the sum of a plurality of products of the same number as the predetermined number of taps that are sequentially generated. And a multiplexer for selecting and outputting a data word.

[0009]

Next, the present invention will be described in detail with reference to the drawings. First, FIG. 1 shows a basic configuration of a digital filter device A according to the present invention. This filter device A is
A typical configuration of a digital filter of the N-1 of a series of 1-clock delay device D ₁ to D _N-1 to N taps with receiving a digital input (TP ₁ to TP _N) (N is 2 or more integer), and the other, the N multipliers M ₁ ~M _N receiving the output of each tap TP ₁ to TP _N, and the adder a which adds the outputs of these multipliers together to generate filter output
And D. In addition, the N multipliers respectively have a series of N coefficients, that is, coefficient sequences CE _{1 to} CE _N.
Is applied.

In this filter device A of the present invention, a part of the N taps, that is, (NM) adjacent taps are used for the filter function (M is an integer of 1 or more), and the remaining taps are used. When using M taps for the delay function,
The series of coefficients CE _{1 to} CE _N are (NM) series of filter coefficients, that is, the filter coefficient sequence FC ₁ to
FC _NM and M delay coefficients DC _{1 to} DC _M. Delay factor DC ₁ to DC _M are each 0.

In the above filter device A, the tap portion to which the corresponding coefficient of the filter coefficient sequence FC _{1 to} FC _NM is applied operates according to the desired filter characteristic defined by the filter coefficient sequence, while , the multiplier output tap portion by applying a delay factor DC ₁ to DC _M is to become 0, the delay unit D followed appropriate tap
Only will work. For example, when M = 2, 1
Clock delay is obtained and applies the beginning and delay factor to the multiplier M _1, M _N of the last tap TP _1, TP _N, 2-clock delay is at the head of the two multipliers tap TP _1, TP ₂ Obtained by applying, and also the last two taps T
When applied to multiplier P _N-1, TP N, becomes 0 clock delay. Therefore, three types of delay time can be realized. Further, the conventional filter function is realized in the tap portion to which the filter coefficient is applied. By doing so, a digital filter having both a filter function and a variable delay function can be configured.

Next, FIG. 2 shows an embodiment of a digital filter device B of the type having a number of taps equal to the number of taps and accumulators for multiply-accumulate operations, which is a more specific form of the basic configuration of FIG. This filter device B is a 64-tap FIR low-pass digital filter, and here 62 taps are used for the filter function and the remaining 2 taps are used for the delay function. Therefore, one filter / delay cycle of this filter device B is 64 clocks long.
In this embodiment, two types of delay time, 0 clock delay and 2 clock delay, are provided.

As shown, the filter device B has a data input terminal for receiving an input data word of 9-bit width, a coefficient input terminal, a clock (CL) input terminal, address input terminals A0-5, and an erase input. Terminals E0-63,
And a digital filter 10 having an output terminal for producing a filtered output data word of 9-bit width. In this embodiment, as the digital filter 10,
Harris Semiconductor Digital Filter HSP4
Eight 3891 are used. In addition, the filter device B
Is a clock generator 20, a counter 30, and a coefficient RO.
It has an M40, a delay switch 50, and a decoder 60.

More specifically, the clock generator 20 in this embodiment generates a clock CL of 32.4 MHz. The counter 30 is a binary 6-bit counter,
In response to the clock, counts 0 to 63 are cyclically generated at the output terminals A0 to A5. This counter output is supplied to the coefficient ROM 40 and the digital filter 10. The coefficient ROM 40 receives the counter output at the 6-bit lower address terminals A5 to 0, and receives the 1-bit delay selection signal DS from the delay switch 50 at the most significant address bit A6. In this example, as shown in FIG.
By the time the selection signal DS is 0 (A6 = 0), using the first coefficient sequence CE ₁ '~CE _64' for the stored at the address 0 to 63 0 clock delay. On the other hand, when the selection signal DS is 1 (A6 = 1), the address 64 to
The second coefficient sequence CE ₁ "providing the 2-clock delay stored in 127 (the lower 6 bits A0 to 5 are 0 to 63)
.. CE ₆₄ ". At this time, the coefficient ROM ₄₀ sequentially supplies the coefficients constituting the corresponding coefficient sequence to the filter 10 in synchronization with the input of the input data word.

The counter output applied to the digital filter 10 is used as an address for selecting one of the multiplexers (described later) having the same number of taps as the digital filter 10, which has completed one filter / delay cycle. Yes (described later). The decoder 60 which receives the counter output has 64 output terminals of the same number as the number of taps, outputs 1 to only one of the series of 64 output terminals and sets 0 to the other, and outputs the counter output. For each increment, the output of its one output is sequentially and cyclically shifted as well (this is described below, one of 64 accumulators in digital filter 10 has completed one filter / delay cycle). It is for erasing the contents of the register in). These outputs are
It is given to the erase inputs E0 to 63 of the digital filter.

Next, FIG. 3 will be described. This Figure 3
Shows the details of the digital filter 10.
As shown, the filter 10 includes one 9-bit wide cell (a group of T flip-flops) that receives an input data word.
An input data shift register consisting of 100 and a series of 64 (same as the number of taps) 9 receiving coefficient data words.
Bit-width cells (T flip-flop group) 200, 21
0 ... 220 coefficient data shift register,
Then, 64 accumulators 300, 310 ...
320, and a multiplexer (MUX) 400,
Made of.

The input data shift register 100 outputs the received input data word in synchronization with the clock CL,
And it applies to each of 64 accumulators 0-63. Each cell of the coefficient data shift register also operates in synchronization with the clock CL to shift the input coefficient data word and apply its output to the corresponding one of the accumulators 0-63. . The accumulators 0 to 63 all have the same configuration, so only the accumulator 0 is shown in detail in the figure. That is,
.. 220 and the corresponding ones of the shift register cells 200, 210 ... 220, ie the outputs from the cell 200, and multiply them together to generate a product data word (18 bits wide). A multiplier 302 and an adder 304 that receives the product data word of this multiplier at one input and adds the inputs to this other to the resulting sum data word (26 bits wide), Register 306, which is a cell that stores this sum data word. The output of the shift register 306 is adapted to be applied to the other input of the adder 304. This shift register operates in synchronization with the clock CL, and also among the 64 erase signals E0 to E63. , The erase signal E0 is received. The shift register when the erase signal goes to 1, i.e., after adding 64 sequentially generated product data words and the sum data word is used as an output, i.e., one filter / delay cycle is completed. The contents of 306 are deleted.

Multiplexer 400 having input terminals F0-F63 for receiving the sum data words from each of accumulators 0-63 receives the output of counter 30 at address input terminals A0-5 and is equal to the value of that counter output. Selects the sum data word of the numbered input terminals to occur at the output. That is, when the counter output value is 0, the sum data word of the input F0 is output, and when the value is 63, the sum data word of the input F63 is output. The output of the multiplexer is 26 bits wide, but in order to make it the same bit width as the input data word, 9 bits of bits 25 and 16 to 9 out of bits 25 to 0 (MSB is bit 25) are used as outputs. To do. Immediately after this output, the erase signal of the accumulator that generated the output sum data word goes to "1" to erase the sum data word, thereby preparing the accumulator for the next filter / delay cycle. .

Next, the overall operation will be described. For example, when the delay selection signal DS is set to "1", the coefficient ROM
40 outputs the second coefficient sequence of FIG. Assuming now that the counter output is at 0 and that the leftmost coefficient of the second coefficient sequence of FIG. 4 is fed to the digital filter 10 and that the leftmost coefficient is in the register cell 200, the accumulator 0 is 0, 1, 2 ...
Execute one filter / delay cycle using 63 coefficients in that order. In addition, other accumulators 1-63
Also performs one filter / delay cycle using the coefficients of ROM addresses 0, 1, ... 63 in this order.

The accumulator 0 will be described.
The accumulator multiplies the sequentially input 64 data words from cell 100 and the sequentially input 64 coefficients from cell 200 in the corresponding order to produce a product, and 64 Their products are added together. Immediately after the addition of these 64 pieces is completed, the counter output becomes 0, and the multiplexer 400 outputs the sum data word of the accumulator 0. At that time, the erase signal E0 becomes "1", and the register 306
Erase the contents of. Accumulator 0 then advances to the next filter / delay cycle. Other accumulators also operate in the same manner as above.

Next, FIG. 5 shows a second embodiment of a digital filter device C of the type having one accumulator for sum of products calculation. This filter device C has a terminal for receiving an input data word of 9-bit width, a coefficient input terminal, a clock input terminal, an erase input terminal E0, and an output terminal for generating a filtered output data word of 9-bit width. , And an accumulator 1000 having In addition to this, a clock generator 2000, a counter 3000, a coefficient ROM 4000, and a delay switch 50
00, a decoder 6000, a multiplexer (MU
X) 7000 and the input data shift register 8100,
8200, ..., 8300, and latch 9000
It has and.

More specifically, the filter device C has 64
A tap FIR digital filter, the clock generator 2000 generates a clock signal CLK1 having a frequency 64 times the sampling frequency of the input data word. The counter 3000 is a 7-bit counter,
Receiving the clock signal CLK1, a count from 0 to 127 is cyclically generated at the output terminals A6 to A0 (A6: MSB). Of this counter output, A5-A0
Is supplied to the coefficient ROM 4000, the decoder 6000 and the multiplexer 7000, and A6 is the clock signal CL.
K1 is used as a clock signal CLK2 obtained by dividing 1/64, and input data shift registers 8100 to 8300 are used.
And latch 9000. An input data shift register consisting of a series of 63 (tap number-1) 9-bit wide cells (T ₁ ) 8100, 8200, ..., 8300 for receiving an input data word has its counter output A
6 as the clock signal CLK2, shifts in synchronization with the clock signal CLK2, and the multiplexer 70
The output of each cell is applied to F63 to F0 of 00. Also,
The multiplexer 7000 has address input terminals A5 to A
The counter outputs A5 to A0 are received at 0, and the input data word of the input terminal having the number equal to the value of the counter output is selected and generated at the output. That is, when the counter output value is 0, the input F0 is input, and when the counter output value is 63, the input F6 is input.
3 is output. Therefore, 64 input data words from the present to the past are generated at the output terminal of the multiplexer 7000, and the input data words are shifted in synchronization with the clock signal CLK2, and a new set of 64 input data words is generated. Occur sequentially.

The coefficient ROM 4000 is the same as the coefficient ROM 40, and receives the counter outputs A5 to A0 at 6-bit lower address terminals A5 to A0, and the highest address bit A6 to 1 from the delay switch 5000. It receives a bit delay selection signal DS. In this example, as shown in FIG. 4, when the selection signal DS is 0 (A6 = 0), the first coefficient sequence CE ₁ ′ to CE ₆₄ ′ for 0 clock delay stored in the addresses 0 to 63. To use.
On the other hand, when the selection signal DS is 1 (A6 = 1), the addresses 64 to 127 (the lower 6 bits A5 to A0 have values 0 to 0).
63) using the second coefficient sequence CE ₁ ″ -CE ₆₄ ″, which gives the two-clock delay. At this time, the coefficient R
The OM 4000 sequentially supplies the coefficients forming the corresponding coefficient sequence to the accumulator 1000 in synchronization with the input data word output from the multiplexer 7000. Further, the decoder 6000 has the same structure as the decoder 60, has 64 output terminals of the same number as the number of taps, and receives the counter outputs A5 to A0 to output one of the series of 64 output terminals. "1" for only one
Is output, and the others are set to "0", and at each increment of the counter output, the terminal outputting the "1" output is sequentially and cyclically shifted. Accumulator 100
A signal is applied to the erase input terminal E0 of 0 from the terminal which generates "1" when the counter outputs A5 to A0 are all zero among these 64 output terminals (this is 1
This is to erase the contents of the register in the accumulator when the filter / delay cycle is complete).

Accumulator 1000 includes input data word output from multiplexer 7000 and coefficient RO.
A coefficient data word output from the M4000 is subjected to a product-sum operation to output a 26-bit wide sum data word, and only the necessary 9 bits (similar to the above-described embodiment) are applied to the latch 9000. At this time, since the sum data word that has not completed one filter / delay cycle is also input, it is operated in synchronization with the clock signal CLK2, and only the sum data word that has completed one filter / delay cycle is latched and filtered. Get the output data word.

The accumulator is an output from the coefficient ROM 4000 and each cell 8100 of the input data shift register.
A multiplier 1002 that receives the output data of ~ 8300 and the input data words sequentially generated by the multiplexer 7000 and multiplies them by one another to generate a product data word (18-bit width), and a product data word of this multiplier , An adder 1004 that adds the input received at the other input to the other input to generate the resulting sum data word (26 bits wide) and one cell (T ₂ Register consisting of 100)
It consists of 6 and 6. The output of the shift register 1006 is adapted to be applied to the other input of the adder 1002. This shift register operates in synchronization with the clock CLK1 and receives the erase signal E0. When the erase signal goes to "1", that is, after adding 64 sequentially generated product data words and the sum data word is used as an output, that is, when one filter / delay cycle is completed, The contents of the shift register are erased, which prepares the accumulator for the next filter / delay cycle.

Next, the overall operation will be described. First, assume that the delay selection signal DS = 0. At this time, in the present digital filter device, the input data word is first stored in the input data shift register cells 8100 to 8300. The 64 coefficient data words CE ₁ ′ to CE ₆₄ ′ read from the coefficient ROM 4000 and the 64 data output from each cell are sequentially supplied to the accumulator 1000 in a corresponding order. In the accumulator, multiply these to produce the product,
The four products are added together. This summed sum data word is output from latch 9000 and, at the same time, the contents of register 1006 in the accumulator are erased and ready for the next filter / delay cycle. The next filter / delay cycle is then started and the input data shift register cells 8100-8300
To store the next new set of 64 input data words. After that, the above operation is repeated. Further, when the delay selection signal DS is switched to "1", it is switched in synchronization with the clock signal CLK2 at the time when one filter / delay cycle is completed (when the added sum data word is output from the latch 9000). Then, from the coefficient ROM 4000, the second coefficient sequence CE ₁ ″ to CE ₁ which gives the 2-clock delay stored in the addresses 64-127 (the lower 6 bits A5 to A0 are 0 to 63) is stored.
It can output ₆₄ ''.

The present invention can also be applied to a known parallel processing type interpolation filter for performing k-times oversampling as a third embodiment (not shown). In this parallel processing type filter, the coefficient sequence for the entire interpolation filter is divided into k mutually interpolating partial coefficient sequences for each of the k separate filter portions. In order to realize the variable delay function in such a k-times oversampling interpolation filter, the coefficient sequence for the entire filter may be divided into the filter coefficient sequence and the delay coefficient as described above. In that case, the delay of 1 clock resolution in the digital filter will reduce the input data word to 1 /
The delay can be given with a resolution of k clocks.

The following modifications can be made to the above-described respective embodiments of the digital filter of the present invention.
That is, first, in the above embodiment, the delay time is two clocks, but it can be changed to provide a longer or shorter delay time. This can be done by changing the number of taps used for the delay function and the number of delay coefficients. Secondly, in the above embodiment, there are two kinds of delay times (including 0 delay), but it is possible to change so as to provide more different delay times. In that case,
This is possible by assigning the number of taps required to give the maximum delay time to the delay function. Thirdly, in the above embodiment, the FIR low-pass digital filter has been described, but by changing the filter coefficient sequence, other filter characteristics (for example, high-pass filter,
A variable delay function can be added to a bandpass filter or the like).

[0029]

According to the present invention described above, the variable delay function can be realized without substantially changing the structure of the conventional non-recursive digital filter. Further, variable delay can be realized without changing the frequency characteristic / group delay characteristic as the filter function.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a digital filter with a variable delay function according to the present invention.

FIG. 2 is a FIR with variable delay function constructed according to the present invention.
It is a block diagram showing the 1st example of a digital filter device, and is a figure showing the type provided with the accumulator for product-sum operation of the same number as the number of taps.

FIG. 3 is a circuit diagram showing details of a digital filter portion in the apparatus of FIG.

FIG. 4 is a diagram showing a coefficient sequence stored in a ROM of the apparatus of FIG.

FIG. 5: FIR with variable delay function constructed according to the present invention
It is a block diagram which shows the 2nd Example of a digital filter apparatus, and is a figure which shows the thing of the type provided with only one accumulator for sum of products calculation.

[Explanation of symbols]

A, B: a digital filter device D ₁ ~D _N-1: delayer TP ₁ to TP _N: Tap M ₁ ~M _N: Multiplier AD: adder CE ₁ ~CE _N: coefficient sequence FC ₁ ~FC _NM: filter coefficient sequence DC ₁ to DC _M: chain of delay coefficients 10: digital filter 20: clock 30: counter 40: factor ROM 50: delay switcher 60: decoder 100: input data shift register 200, 210, 220: factor Data shift register 300, 310, 320: Accumulator 400: Multiplexer DS: Delay selection signal E0 to E63: Erase signal

Claims (15)

[Claims] 1. A receiving digital signal and outputs a digital signal filter, a predetermined number of taps of the _{(N) (TP 1 ~TP N} )
A) a non-recursive digital filter having: a) a second number (NM) of taps smaller than the predetermined number by a first number (M) is allocated for a filter function, b) the first number (M) assigning the taps for a delay function, and c) a set of filter coefficients (FC _{1 to} FC _NM ) to apply to each of the second number of adjacent taps, and the rest of the _first taps. Zero coefficient applied to taps of 1 (DC
₁ generates and to DC _M), a series of coefficients (CE ₁ ~CE _N) consisting each of two) the series coefficients, applied to corresponding said tap by the filter function and a delay function A non-recursive digital filter that achieves both. 2. The filter according to claim 1, wherein the series of coefficients comprises a plurality of series of coefficients (CE ₁ ′ to CE ₆₄ ′, CE ₁ ″ to CE ₆₄ ″) that give different delays to each other. A non-recursive digital filter characterized in that a filter that gives a desired delay can be selected. 3. The filter according to claim 2, wherein the first number (M) of the taps is the number required to provide the maximum of the delays provided by the plurality of series of coefficients. A non-recursive digital filter characterized by: 4. The filter according to claim 1, wherein the series of filter coefficients (FC _{1 to} FC _NM )
Are non-recursive digital filters, which can be selected to give desired filter characteristics. 5. The filter according to any one of claims 1 to 4, wherein the non-recursive digital filter is of a type provided with a plurality of sum-of-products calculating means equal in number to the predetermined number of the taps. A non-recursive digital filter characterized by: 6. The filter according to any one of claims 1 to 4, wherein the non-recursive digital filter is of a type including only one product-sum calculation means. Recursive digital filter. 7. The non-cyclic filter according to claim 1, wherein the non-cyclic digital filter is a parallel processing type interpolation filter for performing k-fold oversampling. Digital filter. 8. Upon receiving the digital signal and outputs a digital signal filter, a predetermined number of taps of the _{(N) (TP 1 ~TP N} )
A) a non-recursive digital filter having: a) a series of filter coefficients for a predetermined filter function for a second number (NM) of adjacent taps that is smaller than the predetermined number by a first number (M). (FC _{1 to} FC _NM )
Apply the corresponding one of b) b) For the remaining taps of the first number (M),
Applying the zero coefficients for the delay function (DC ₁ ~DC _M), by a method to achieve both a filter function and delay function. 9. The method according to claim 8, wherein the series of coefficients (CE _{1 to} CE _N ) consisting of the series of filter coefficients and the zero coefficient comprises a plurality of series of coefficients (CE _{1 to} CE _N ) providing different delays. CE ₁ '-CE ₆₄ ', CE ₁ "-CE ₆₄ "), selecting the one that gives the desired delay. 10. The method of claim 9, wherein the first number of taps (M) is the number required to provide the maximum of the delays provided by the plurality of series of coefficients. Is a method. 11. The method according to claim 8, wherein the series of filter coefficients (FC _{1 to} FC _NM ).
Can be selected to give the desired filter characteristics. 12. A digital filter with a predetermined number of taps, which receives an input data word of a predetermined number of bits (9) and produces a filtered output data word, a) connected to receive the input data word. did,
An input data shift register means (100) comprising one cell having a width of the predetermined number of bits, wherein the input data word held is output as a first input data word. B) a plurality of series of second numbers (62) each word having the same number of bits as the predetermined number of bits and smaller than the predetermined number of taps by a first number (2) used for the filter function. Filter coefficient data words (FC ₁ 'to FC ₆₂ ') of the above, and each word having the same number of bits as the predetermined number of bits used for the delay function, and at least one delay coefficient data word of the first number. (DC ₁ ', DC ₂ '), and ₁ from a series of coefficient data words (CE ₁ '-CE ₆₄ ', CE ₁ "-CE ₆₄ ") containing
Coefficient generating means for sequentially generating one coefficient data word (2
0, 30, 40, 50) and c) coefficient data shift register means (200, 210, 220) connected to receive the coefficient data words (D0-8) generated by the coefficient generating means, the input data shift Coefficient data shift register means (20) having a width of the predetermined number of bits and having a same number of cells as the predetermined number of taps, which shifts in synchronization with the register means (20).
0,210,220), wherein each of the plurality of cells holds and outputs the first number of first coefficient data words representing a coefficient to be applied to the first input data word.
The coefficient data shift register means, d) a plurality of multiplication and addition means (300, 310, 320, 400) of the same number as the predetermined number of taps, each of the plurality of multiplication and addition means having the first input data word, Corresponding one of the plurality of cells of the coefficient data shift register
Generating a product data word (302), the product data word (302) being connected to receive the first coefficient data word generated by one cell and representing the product of the received first input data and the first coefficient, and A plurality of multiplication and addition means (a plurality of multiplication and addition means for adding a plurality of products of the same number as the predetermined number of taps sequentially generated in this way to generate a sum data word (304, 306) representing the sum of the results 300,310,320,400) and a digital filter consisting of. 13. The filter according to claim 12, wherein
A digital filter, wherein the first number is 1 or more. 14. The filter according to claim 12 or 13, wherein said coefficient generating means includes: (a) a storage means (40) for storing a plurality of said series of coefficient data words for giving different delays; (B) Selection means (50) for selecting one of the series of coefficient data words stored in the storage means.
And (c) counter means (30) for sequentially reading the coefficient data words forming the selected one series of coefficient data words in a cyclical manner. 15. The filter according to claim 12, wherein the plurality of multiplication and addition means are: a) A plurality of accumulators (300, 310, 320) that output the sum data word and have the same number as the predetermined tap number. And (b) a multiplexer (400) connected to receive a plurality of the sum data words, the sum of the plurality of products being the same as the predetermined number of taps in which the sum data words are sequentially generated. The multiplexer (40) that selects and outputs the sum data word when it becomes
0) and including a digital filter.