JPH11220357A - Digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To incorporate an attenuating function in the digital filter. SOLUTION: Input data X(n) is inputted to a multiplier 35 through a selector 33 and multiplied by an attenuation coefficient g(m) inputted through a selector 34 and the result is stored as attenuation input data x(n) in a RAM 31. The attenuation input data x(n) read out of the RAM 31 is inputted to a multiplier 35 through the selector 34 and supplied to a cumulating adder 36. The multiplication data is cumulatively added by the cumulating adder 36 according to the number of taps and final cumulative addition data are stored as intermediate data A(n) and B(n) in registers 39 and 40 alternately. An adder subtracter 41 performs a subtracting process and an adding process for the intermediate data A(n) and B(n) and output data Ya(n) and Yb(n) are stored in an output register 42.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital filter for separating digital data used in digital audio equipment and the like.

[0002]

2. Description of the Related Art A FIR (Finite Impulse Response) digital filter is configured to obtain output data Y (n) by convolution of input data X (n) and an impulse response as shown in equation (1). Is done.

[0003]

(Equation 1)

[0004] Here, h (k) is a filter coefficient, and N is the number of taps. Then, when Expression (1) is Z-transformed,

[0005]

(Equation 2)

[0006] From this equation (2),

[0007]

(Equation 3)

Thus, the frequency response can be understood. And ω
= 2πk / N, equation (3) becomes

[0009]

(Equation 4)

## EQU1 ## This equation (4) can be regarded as an equation of a discrete Fourier transform (DFT). Therefore, the filter coefficient h (k) is obtained by inversely transforming the frequency characteristic given by the equation (4) (IDFT: Invers
e Discrete Fourier Transform). FIG. 5 is a circuit diagram showing a configuration of a standard FIR type digital filter.

The plurality of delay elements 1 are composed of, for example, shift registers, are connected in series with each other, and each delay input data X (n) by a predetermined period T. The plurality of multipliers 2 are provided on the input side of the input data X (n) and each delay element 1
And multiplies the input data X (n) and the output of each delay element 1 by a unique filter coefficient h (k). Thereby, the convolution process of the impulse response is performed on the input data X (n).

The sum adder 3 takes the output of each multiplier 2, that is, the sum of the input data X (n) multiplied by a predetermined filter coefficient h (k) and the output of each delay element 1, and outputs the output data. Output as Y (n). Therefore, the operation according to the above equation (1) has been performed on the input data X (n). In such a digital filter, since the delay element 1 and the multiplier 2 are arranged according to the number of taps N, there is a problem that the circuit scale increases as the number of taps N increases. Therefore, there has been proposed a digital filter of a stored program method in which time-series input data is temporarily stored in a memory, and input data read from the memory is sequentially multiplied by a filter coefficient, and the multiplication result is cumulatively added. I have.

FIG. 6 is a block diagram showing the configuration of a digital filter of the stored program system. RAM1
1 sequentially stores input data X (n) input in time series, and the ROM 12 stores a plurality of filter coefficients h (k) in advance. Further, the RAM 11 stores the stored input data X
(n) is read and output for each step,
Reads and outputs a specific filter coefficient h (k) corresponding to the value of k that increases in each step. Note that k is equal to k shown in Expression (1). Then, the multiplier 13 multiplies the input data X (nk) read from the RAM 11 by the filter coefficient h (k) read from the ROM 12.

The accumulator 14 comprises an adder 15 and a register 16, and accumulates the multiplication result of the multiplier 13. That is, the output of the multiplier 13 and the register 16
Is added to the output of the register 16 again.
, The multiplication results of the multiplier 13 are sequentially added. The output register 17 takes in the accumulation result output from the accumulator 14 and outputs it as output data Y (n).

In this FIR digital filter, RA
By sequentially reading the input data X (n) and the filter coefficient h (k) from the M11 and the ROM 12 and repeating the product-sum operation, the operation according to the equation (1) is executed to obtain the output data Y (n). . Therefore, even if the number of taps N increases, the circuit scale does not increase. By the way, for a digital filter having a first filter coefficient h1 (n),

[0016]

(Equation 5)

The second filter coefficient h2 given by
The digital filter having (n) is called a mirror filter because of its frequency response. The relationship of Z conversion in such a mirror filter is as follows.

[0018]

(Equation 6)

## EQU1 ## Here, considering the frequency response,

[0020]

(Equation 7)

Therefore, equation (6) is

[0022]

(Equation 8)

## EQU1 ## This indicates that the frequency response of the mirror filter is symmetric at π / 2. Here, since π / 2 is ４ of the sampling period, this mirror filter is a QMF (Quadrature Mirror).
Filter). Such a QMF is described in IEE Transactions on Acoustic Speech and Signal Processing, ISSP Vol. 32, No. 3, June 1984, (IEEE Tr
ans. Acoust., Speech, Signal Process., Vol.ASSP-32, N
o.3, June 1984) pages 522 to 531.

In the separation filter that separates the frequency components by the above-described QMF, the equations (9) and (1)
As shown in (0), two output data Ya (n), which are separated data of the input data X (n), are obtained by convolution processing of the input data X (n) and the impulse response and addition or subtraction processing thereof. It is configured to obtain Yb (n).

[0025]

(Equation 9)

[0026]

(Equation 10)

FIG. 7 is a block diagram showing a configuration of a separation filter for performing band separation processing according to equations (9) and (10). The plurality of delay elements 21 are connected in series, and each delay the input data X (n) by a certain period T. The plurality of first multipliers 22 are connected to the input side of the input data X (n) and the output side of the delay element 21 in the even-numbered stages, and
(n) and the output of each delay element 21 are respectively multiplied by a filter coefficient h (2k). Further, the plurality of second multipliers 24
It is connected to the output side of the odd-numbered delay elements 21 and multiplies the output of each delay element 21 by a filter coefficient h (2k + 1). Thereby, the convolution process of the impulse response with respect to the input data X (n) is performed.

The first sum adder 24 includes a first multiplier 2
2 are all added to output intermediate data An.
On the other hand, the second sum adder 25 adds all the outputs of the second multiplier 23 and outputs intermediate data Bn. The subtracter 26 subtracts the intermediate data Bn input from the second sum adder 25 from the intermediate data An input from the first sum adder 24, and outputs the result as first output data Ya (n). I do. Further, the adder 27 includes the intermediate data An input from the first sum adder 24 and the second sum adder 25.
Is added to the intermediate data Bn input from the second unit and output as second output data Yb (n). In this way, the arithmetic processing according to the equations (9) and (10) is achieved.

The construction of such a separation filter by the above-mentioned stored program method is disclosed in Japanese Patent Application Laid-Open No. Hei 7-131295 proposed by the present applicant.

[0030]

In general audio equipment, there is provided an attenuation function for attenuating an audio signal and lowering a reproduction volume. In the case of a digital audio device typified by an MD (Mini Disc) player, the attenuation function is realized by multiplying the digitized audio data by an attenuation coefficient having a gain of 1 or less.

In digital data arithmetic processing, as the number of multipliers having a large circuit scale increases, the arithmetic processing device becomes complicated, resulting in an increase in cost. In particular, in the case of audio data having a large number of bits, an increase in the number of multipliers tends to greatly affect an increase in cost. Accordingly, an object of the present invention is to provide a digital filter with a built-in attenuation function without increasing the circuit scale.

[0032]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized by time-series input data and data generated based on the time-series input data. Attenuation input data is input together with a predetermined attenuation coefficient and a filter coefficient corresponding to the attenuation input data, and any one of the set of the time-series input data and the predetermined attenuation coefficient or the combination of the attenuation input data and the filter coefficient A selector for selecting one of the sets, a multiplier for multiplying the set of data selected by the selector with each other, and a calculation result of the multiplier for the set of the time-series input data and a predetermined attenuation coefficient, and storing the attenuation input. RAM for supplying data to the selector as data
And a accumulator for sequentially accumulating the operation result of the multiplier corresponding to the set of the attenuation input data and the filter coefficient; and first and second registers for alternately receiving the operation result of the accumulator. , An adder / subtractor for adding or subtracting two operation results taken out from the first and second registers, wherein the operation result of the adder / subtracter is used as first and second separation data of the input time series data. Output as time-series data.

According to the present invention, the input time-series data is multiplied by a predetermined attenuation coefficient and stored in the RAM.
Then, the attenuated input time-series data is multiplied by a filter coefficient, and arithmetic processing for band separation is performed. By using a common multiplier for the multiplication of the attenuation coefficient and the multiplication of the filter coefficient, it is not necessary to increase the number of multipliers.

[0034]

FIG. 1 is a block diagram showing a digital filter according to a first embodiment of the present invention. RAM3
1 is connected to a multiplier 35 to be described later and stores the attenuation input data x (n) input from the multiplier 35 for a predetermined period,
The data is sequentially read and output for each step of the arithmetic processing. The ROM 32 stores a plurality of filter coefficients h (k) in advance, reads out a predetermined filter coefficient h (k) corresponding to the value of k that increases for each step, and repeatedly outputs the same.
This k coincides with k shown in the above equations (9) to (10). The first selector 33 is connected to the encode input and the RAM 31, and receives time-series input data X (n) or attenuation input data x (n) read from the RAM 31.
Is selected and output. Second selector 34
Is connected to the attenuation input and the ROM 32, and selects and outputs one of the attenuation coefficient g (m) and the filter coefficient h (k) read from the ROM 32.
The first and second selectors 33 and 34 are selectively controlled in response to a common selection control signal SC.

The multiplier 35 is connected to the first selector 33 and the second selector 34, and receives one of the input data X (n) or the attenuation input data x (n) selected by the first selector 33, The signal is multiplied by one of the attenuation coefficient g (m) or the filter coefficient h (k) selected by the second selector 34. Here, when the first selector 33 selects the input data X (n), the second selector 34 selects the attenuation coefficient g (m), and the first selector 33 selects the attenuation input data x (n). In this case, the second selector 34 operates so as to select the filter coefficient h (k). Thereby, the multiplier 35 multiplies the input data X (n) by the attenuation coefficient g (m) or multiplies the attenuation input data x (n) by the filter coefficient h (k). The multiplication data of the input data X (n) and the attenuation coefficient g (m) is stored in the RAM.
The multiplied data of the attenuation input data x (n) and the filter coefficient h (k) is supplied to the accumulator 36.

An accumulator 36 comprising an adder 37 and a register 38 is connected to the multiplier 35, and accumulates the multiplication data input from the multiplier 35 according to the number of taps. That is, the data read from the register 38 and the multiplication data input from the multiplier 35 are added by the adder 37, and the added data is stored in the register 38 again.
The multiplication data of the multiplier 35 is cumulatively added.

First register 39 and second register 4
The 0 is connected to the accumulator 36, alternately fetches and stores the accumulated data continuously input from the accumulator 36, and outputs each at a predetermined timing. For example, odd-numbered intermediate data A (n) output from the accumulator 36
Is stored in the first register 39, and the intermediate data B (n) outputted even-numbered is stored in the second register 40. The adder / subtractor 41 is connected to the first register 39 and the second register 40,
The intermediate data A (n) and B (n) read from 0 are subtracted or added.

The output register 42 is connected to the adder / subtractor 41, stores the addition / subtraction data input from the adder / subtractor 41 for each operation, and outputs the data as output data Ya (n) and Yb (n). For example, it corresponds to the adder / subtractor 41 that alternately repeats the subtraction operation and the addition operation, and outputs the subtraction data to the output data Ya.
(n), and outputs the added data as output data Yb (n). The output of this output register 42 is the encoded output.

In the above digital filter, the multiplier 35 performs the multiplication of the attenuation coefficient g (m) and the multiplication of the filter coefficient h (k) in a time-division manner, and attenuates and separates the input data X (n). Processed output data Ya (n),
Generate Yb (n). This makes it possible to perform an attenuation process in a digital filter without adding a new multiplier.

FIG. 2 shows that the digital filter shown in FIG.
FIG. 6 is a timing chart for explaining an operation when the number of taps N is “4”, and shows a case where n = 4. First, the first selector 33 selects the input data X (n),
Selector 34 selects the attenuation coefficient g (m). In this state, when the input data X (8) is input, the multiplier 35 multiplies the input data X (8) by the attenuation coefficient g (1), and obtains the multiplied data x (8).
(8) (= X (8) · g (1)) is RAM as attenuation input data.
31 is written. Here, the attenuation coefficient g (1)
Is used to determine the degree of attenuation with respect to the input data X (n), and is usually fixed at a constant value.
When the writing of the attenuation input data x (8) to the RAM 31 is completed, the first selector 33 is switched to the attenuation input data x (8) side (the RAM 31 side), and at the same time, the second selector 34 is switched to the second selector 34. Is the filter coefficient h (k) side (R
OM32 side).

The data separation processing by the digital filter is performed on the attenuation input data x (8) stored in the RAM 31. That is, the input data X (n) is replaced with the attenuation input data x (n), and the number of taps N = 4, and the equations (9) and (9) are used.
The arithmetic processing according to the following equations (11) and (12) obtained by calculating (10) is executed.

[0042]

[Equation 11]

[0043]

(Equation 12)

In FIG. 2, input data X (0) to X (7)
Although not shown in the drawing, the input data X (0) to X (7) are input before the input data X (8), and are respectively multiplied by the attenuation coefficient g (1). It is stored in the RAM 41 as attenuation input data x (0) to x (7). For the first and second selectors 33 and 34, input data X (0) to X (7) and attenuation input data x (0) to
Switching is performed in accordance with the multiplication process with x (7).

First, from the RAM 31 to the first selector 33
When the attenuation coefficient x (8) is read out from the ROM 32 and the filter coefficient h (0) is read out from the ROM 32 via the second selector 34, the attenuation input data x (8) is
, And the multiplied data is supplied to the accumulator 36. At this time, the data of the accumulator 36 has been cleared, and the multiplication value of the attenuation input data x (8) and the filter coefficient h (0) is A (1) = h (0) · x (8). The data is stored in the register 38 as it is.
Subsequently, attenuation input data x (6), x (4),
x (2) is sequentially read out, and the filter coefficients h (2), h (4), h (6) are sequentially read out from the ROM 32, multiplied by the multiplier 35, and each multiplied data is sequentially accumulated. 36. In the accumulator 35, the input multiplication data is accumulated, and A (2) = h (2) .x (6) + A1 A (3) = h (4) .x (4) + A2 A (4) = H (6) .x (2) + A3 are sequentially stored in the register 38. And
A (4) = h (0) .x (8) + h (2) .x (6) + h (4) .x (4) +
The data h (6) .x (2) is stored in the first register 39.

Subsequently, the RAM 31 stores the first selector 3
3, the attenuation input data x (7) is read out, and the filter coefficient h (1) is read out from the ROM 32 through the second selector 34 correspondingly.
5 and the multiplied data is supplied to the accumulator 36. At this time, the register 38 of the accumulator 36 has been cleared, and the multiplication value of the attenuation input data x (7) and the filter coefficient h (1) becomes B (1) = h (1) · x (7). Is stored in the register 38 as it is.
Subsequently, attenuation input data x (5), x (3),
x (1) is read out sequentially, and the filter coefficients h (3), h (5), h (7) are read out sequentially from the ROM 32, and the respective multiplied data are sequentially supplied to the accumulator 36. Therefore, B (2) = h (3) .x (5) + B1 B (3) = h (5) .x (3) + B2 B (4) = h (7) .x (1) + B3 The data is sequentially stored in the register 38. And
B (4) = h (1) .x (7) + h (3) .x (5) + h (5) .x (3) +
The data h (7) · x (1) is stored in the second register 40.

Then, the data A (4) and B (4) are input from the first register 39 and the second register 40 to the adder / subtractor 41, respectively, and the data A (4) and the data B (4) are added. Then, data B (4) is subtracted from data A (4). A (4) + B (4) = h (6) · X (2) + h (4) · X (4) + h (2) ·
X (6) + h (0) · X (8) + h (7) · X (1) + h (5) · X (3) +
h (3) .X (5) + h (1) .X (7) is stored in the output register 42 as output data Yb (4). Also, subtraction data, that is, A (4) −B (4) = h (6) · X (2) + h (4) · X (4) + h (2) ·
X (6) + h (0) .X (8) -h (7) .X (1) -h (5) .X (3)-
h (3) .X (5) -h (1) .X (7) is stored in the output register 42 as output data Ya (4). As a result, the arithmetic processing represented by Expressions (11) and (12) has been performed.

In this embodiment, the input data X (n) or the attenuated input data x
(n), and the second selector 34 selects either the attenuation coefficient g (m) or the filter coefficient h (k). However, the input data X (n) and the attenuation coefficient g ( m) may be replaced with the input.

FIG. 3 shows a second embodiment of the digital filter of the present invention.
FIG. 2 is a timing chart for explaining the operation. In these figures,
The parts other than the ROM 32 'are the same as those in FIG. 1, and the description is omitted. The ROM 32 'stores the attenuation coefficient g (m) together with the plurality of filter coefficients h (k). And the first
Control signal SC for controlling the selection operation of selector 33
, The attenuation coefficient g (m) or the filter coefficient h (k) is read and output. That is, as shown in FIG. 2, when the first selector 33 selects the input data X (n), the attenuation coefficient corresponding to the value of m which specifies the degree of attenuation with respect to the input data X (n). Read and output g (m). When the first selector 33 selects the attenuation input data x (n), a predetermined filter coefficient h corresponding to the value of k that increases for each step is set.
(k) is read and output repeatedly. This k coincides with k shown in the above equations (9) to (10), as in the case of FIG.

Therefore, the ROM 32 'has the second memory shown in FIG.
, The attenuation coefficient g (m) is supplied to the input data X (n), and the filter coefficient h (k) is supplied from the ROM 32 'to the attenuation input data x (n). . As a result, the same operation as in FIG. 1 can be achieved.

[0051]

According to the present invention, an attenuating function can be added without increasing the number of multipliers in a digital filter using a stored program type QMF which is advantageous for reducing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a digital filter according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a block diagram illustrating a digital filter according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment.

FIG. 5 is a circuit diagram showing a configuration of an FIR digital filter.

FIG. 6 is a block diagram showing a configuration of a stored program type QMF.

FIG. 7 is a configuration diagram of a separation filter using QMF.

[Explanation of symbols]

 1,21 delay element 2,22,23 multiplier 3,24,25 sum adder 11,31 RAM 12,32,32 'ROM 13,35 multiplier 14,36 accumulator 15,37 adder 16,38 Registers 17, 42 Output register 26 Subtractor 27 Adder 33, 34 Selector 39, 40 Register 41 Adder / subtractor

Claims (4)

[Claims] 1. Time-series input data and attenuation input data generated based on the time-series input data are input together with a predetermined attenuation coefficient and a filter coefficient corresponding to the attenuation input data. A selector for selecting one of the set of the predetermined attenuation coefficient or the set of the attenuation input data and the filter coefficient; a multiplier for multiplying the set of selection data of the selector by one another; and the time-series input data. And a RAM for storing a calculation result of the multiplier for a set of predetermined attenuation coefficients and supplying the result as the attenuation input data to the selector; and a calculation result of the multiplier corresponding to the set of the attenuation input data and the filter coefficient. And a first and second register for alternately taking in the operation result of the accumulator. And an adder / subtractor for adding or subtracting two operation results taken out from the first and second registers. The first and second units are used to separate the operation result of the adder / subtracter into separated data of the input time-series data. A digital filter for outputting as second output time-series data. 2. The apparatus according to claim 1, further comprising a ROM storing a plurality of filter coefficients, reading one filter coefficient at each operation timing of the multiplier, and supplying the read filter coefficient to the multiplier. Digital filter. 3. The digital filter according to claim 2, wherein the ROM stores a predetermined attenuation coefficient together with the plurality of filter coefficients. 4. The digital filter according to claim 1, further comprising an output register for holding the operation result of said adder / subtracter as first or second output time-series data.