JP2001345678A - Fir filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the clock frequency for energy saving in a data holding circuit. SOLUTION: An FIR filter includes data holding circuits 10 to 13, in which digital data X is sequentially entered as an input, fed sequentially, and stored in plurality; and operation circuits 20 to 40 for calculating a product-sum operation value Y(n) of the plurality of data X(n) to X(n-3) and given coefficient groups B0 to B3. In the data input and sequential feeding, the data holding circuits operate by dividing the data into a plurality of group lines 10+12 and 11+13. The operation circuit has a coefficient value selecting circuit 40 and thereby a coefficient value is selected from the coefficient groups corresponding to the dividing method during the product-sum operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a finite impulse response filter (FIR filter) among digital linear filters, and more particularly, to a technique for reducing the power consumption of the circuit. The FIR filter is preferably employed in various signal processing circuits such as audio signal processing, and is often incorporated in a part of a signal processing LSI. In particular, mobile phones and the like often include a plurality of FIR filters.

[0002]

2. Description of the Related Art An FIR filter whose circuit diagram is shown in FIG. 7 is a typical example of a conventional FIR filter, and a data holding circuit for sequentially inputting digital data and sequentially holding a plurality of digital data and holding a plurality of digital data. In a FIR filter comprising an arithmetic circuit for calculating a product-sum operation value with a group of coefficients, the data holding circuit performs data forwarding in a single sequence, and the arithmetic circuit compares data at each stage in the sequence with The product-sum operation is performed in a state where each coefficient value in the coefficient group is fixedly associated with each other, and the sum thereof is obtained.

More specifically, when digital data to be input is 1
There are m bits per word (four bits in FIG. 7 (b)), and data X (n-3), data X (n-2), and data X (n-
Under the situation where data is input in the order of 1), data X (n), data X (n + 1), a k-th order, for example, a third order, for calculating a product-sum operation value Y (n) based on these data strings The FIR filter will be described as a specific example. Then, in such a case, the data holding circuits 10 to 13 add the data X (n−1), data X (n−2), and data X up to k times before in addition to the data X (n) just input. (N-3) are held in a line, that is, in a series, and the plurality of data X (n) to X (n-
The value of 3) is sent to the arithmetic circuit at the same time.
Based on the (k + 1) data X and the (k + 1) coefficient values B0 to B3, the product-sum operation value Y (n) =
｛B0 × X (n) + B1 × X (n−1) + B2 × X (n
−2) + B3 × X (n−3)} is calculated.

In order to repeat such processing for each pulse of the basic clock CLK, the data holding circuits 10-1
No. 3 has (k + 1) or more m-bit registers 10, 11, 12, and 13 that perform a latch operation in synchronization with the clock CLK, and sequentially sends data X in the column order in word units, that is, m-bit parallel. It is supposed to.
Further, the arithmetic circuit has B0 ×
X (n), B1 × X (n−1), B2 × X (n−2),
In addition to the (k + 1) multiplication circuits 20, 21, 22, 23 for calculating B3 × X (n−3), a summation circuit 30 for calculating the sum of them is also provided. When the number of outputs (k + 1) of the multiplication circuit is three or more, the summation circuit 30 is often embodied by combining two-input addition circuits 31 to 33 in multiple stages. Further, the coefficient values B0 to B3 (counting group) are determined according to the filtering characteristics required by the application, and are often set to a fixed value of m bits. May be set to a different value.

[0005]

By the way, in such a conventional FIR filter, as described above, a plurality of bits of registers are used in a data holding circuit which holds and forwards a plurality of data. And a plurality of registers that are larger than the order of. Then, since they are switched at the same time each time they are forwarded in synchronization with the clock, the power consumption tends to increase.

Therefore, when applied to a device such as a portable telephone which is advantageous in low power consumption, the clock frequency of the data holding circuit is lowered in order to reduce the power consumption. It is a technical problem to obtain a product-sum operation value of. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has been developed to reduce the frequency of a clock of a data holding circuit.
It is intended to realize an R filter.

[0007]

Means for Solving the Problems First and second solving means invented to solve such problems are as follows.
The configuration and operation and effect will be described below.

[First Solution] FI of the first solution
The R filter is a data holding circuit for sequentially inputting and sequentially holding digital data and holding a plurality of digital data as described in claim 1 at the time of filing of the application, and a predetermined circuit provided with the plurality of data as a fixed value or a variable set value or the like. And an operation circuit for calculating a product-sum operation value with the coefficient group of the FIR filter, wherein the data holding circuit performs data input and forward transfer by distributing the data into a plurality of series, The arithmetic circuit has a coefficient value selecting circuit, and at the time of the product-sum operation, also selects a coefficient value from the coefficient group corresponding to the distribution.

In the FIR filter according to the first solution, the digital data sequentially sent to the data holding circuit at a predetermined cycle is assigned to one of a plurality of streams, and the sorted streams are sent. It is input to the part and is forwarded there. As a result, each series part of the data holding circuit only needs to operate when it is assigned to the distribution destination, and does not need to operate when data is distributed to the other series parts. It is possible to operate at a longer cycle than the cycle that is received.

[0010] For this reason, in the sequence portion other than the distribution destination, the sequential transmission of data is stopped. Instead, at the time of the product-sum operation, a coefficient value is selected from a coefficient group corresponding to the distribution. That is, an appropriate coefficient value is selected from the coefficient group in accordance with which series is the distribution destination. As a result, regarding the product-sum operation, the lack of sequential data advance is compensated by the selection switching of the coefficient value, so that a correct product-sum operation value can be obtained. Therefore, according to the present invention, it is possible to realize an FIR filter in which the clock frequency of the data holding circuit is lower than the frequency at which digital data is sequentially transmitted.

[Second solving means] FI of the second solving means
The R filter is an FIR filter according to the first solving means as set forth in claim 2 at the beginning of the application, wherein the arithmetic circuit selects data from the plurality of data corresponding to the distribution at the time of product-sum operation. Is provided, and an intermediate calculated value holding circuit for holding an intermediate calculated value in the middle of the product-sum operation is also provided.

[0012] In the FIR filter of the second solution, based on data distribution into a plurality of streams,
In addition to selection switching of coefficient values, selection switching of data is also performed. As a result, the multiplication circuit of the arithmetic circuit can be shared by each series of the data holding circuit, and even in such a case, the product of the appropriate data and the coefficient value can be calculated. Also, the intermediate calculated value calculated in this way is
Even if the multiplication circuit that has calculated it is directed to other series of data or the like, it is held by the intermediate calculation value holding circuit for as long as necessary.
Thereby, the sum is also properly calculated.

Therefore, even if the number of multiplication circuits is reduced in order to achieve a reduction in circuit scale in addition to a reduction in the clock frequency of the data holding circuit, a product-sum operation value equivalent to that of the related art can be obtained. Therefore, according to the present invention,
It is possible to realize an FIR filter in which the clock frequency of the data holding circuit is lower than the frequency at which digital data is sequentially transmitted, and the number of multiplication circuits is small.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments for implementing the FIR filter of the present invention achieved by such a solution will be described with reference to the following first and second embodiments. The first embodiment shown in FIG. 1 to FIG.
The second embodiment shown in FIGS. 4 to 6 also embodies the second solution described above. In each figure, “FF” indicates a flip-flop that holds 1-bit data, and “Reg” indicates 1
A register holding a word, that is, a plurality of bits of data is shown. In the drawings, the same components as those in the related art are denoted by the same reference numerals.

[0015]

First Embodiment A first embodiment of an FIR filter according to the present invention will be described with reference to the drawings. 1A is a schematic circuit diagram, FIG. 1B is an example of a circuit for generating a derived clock, and FIG. 2 is a detailed circuit diagram.

In this embodiment, a k-th order FIR filter, for example, a tertiary order FIR filter will be described as a specific example so as to be easily compared with the conventional example. That is, the input digital data is m bits per word (four bits in FIG. 2), and for example, data X (n-3) and data X (n-
2) Under the situation where data is input in the order of data X (n-1), data X (n), an FIR filter that calculates a product-sum operation value Y (n) based on these data strings State.

In this FIR filter, while the data X is transmitted by the pre-circuit 9 and the like in synchronization with the clock CLK, the data holding circuits 10 to 13 for sequentially inputting and sending the data X sequentially output the data X more than the clock CLK. Based on the low-frequency clocks CLKa and CLKb, for example, the latch operation is performed at the rising edge thereof. In addition, the data holding circuits 10 to 13 are reassembled into two series so that the product-sum operation is appropriately performed, and the coefficient value selecting circuit 40 is added to the arithmetic circuits 20 to 30.

In response to the number of streams to which the data X is distributed, that is, the number of streams, "2", the clock CL
Ka and CLKb include pulse oscillation signals having a frequency half that of the clock CLK and different phases from each other.
Adopted. For example, (see FIG. 1B), the clock CLK is divided into two by a T-type flip-flop, and its non-inverted output is used as the clock CLKa and its inverted output is used as the clock CLKb. Is made.
The positive-phase clock CLKa and the negative-phase CLKb generated in this way are both synchronized with the clock CLK, but are out of phase with each other.

The data holding circuits 10 to 13 are provided with (k + 1) registers 10, 11, 12, and 13 in the same manner as in the prior art. Each of the registers holds m bits of data X in order to hold m bits of data X. However, unlike the related art, the wiring for connecting the flip-flops and the clock for causing the flip-flop to perform the latch operation are changed so as to form two lines. Specifically, the output of the pre-circuit 9 is input to the register 10, wiring is performed so that the output of the register 10 is input to the register 12, and the registers 10, 12
Is supplied with the positive-phase clock CLKa, whereby the first series portion is established. The output of the pre-circuit 9 is also input to the register 11, and wiring is performed so that the output of the register 11 is input to the register 13.
By supplying the inverted-phase clock CLKb to these registers 11 and 13, the second series portion is established.

The output of register 10, ie, register 10
Is stored in the multiplication circuit 20 in the arithmetic circuit.
Is sent to the other input as one input, but unlike the conventional one, the other input of the multiplication circuit 20 is
Instead of directly inputting the coefficient value B0, the output of the multiplexer 41 of the coefficient value selection circuit 40 is guided. The outputs of the registers 11, 12, and 13 are also input to one of the multiplication circuits 21, 22, and 23 in the arithmetic circuit, respectively. The outputs of the multiplexers 42, 43, 44 of the circuit 40 are guided.

The multiplexers 41 and 42 of the coefficient value selection circuit 40 store the latest data X in the two-series register 1.
In response to being assigned to 0 and 11, the counting groups B0
Of the B3, a two-input one that inputs the coefficient value B0 and the coefficient value B1 is adopted. When the latest data X (n) is latched in the register 10, the data X held in the register 11 at that time becomes data X (n-1) one clock earlier than the clock CLK, and the latest data X (n). )
Is latched in the register 11, then the register 10
The clocks CLKa and CLKb are used as the control inputs of the multiplexers 41 and 42, respectively, in response to the fact that the data X held in the data becomes the data X (n-1) one clock before the clock CLK. And register 1
When 0 holds the latest data X (n), the coefficient value B0 is sent from the multiplexer 41 to the multiplier circuit 20, and the coefficient value B1 is sent from the multiplexer 42 to the multiplier circuit 21, and the register 11 stores the latest data X (n). n)
Is held, the coefficient value B1 is sent from the multiplexer 41 to the multiplier circuit 20, and the coefficient value B0 is sent from the multiplexer 42 to the multiplier circuit 21.

Each of the multiplexers 43 and 44 of the coefficient value selection circuit 40 employs a two-input one that inputs a coefficient value B3 and a coefficient value B4 of the count groups B0 to B3, respectively. This is because the data X distributed to the two series of registers 10 and 11 are sent forward in each series two clocks later by the clock CLK, and therefore the register 1
Data X (n-2) and data X (n-3)
Is to be held. The clock C is also applied to the control inputs of these multiplexers 43 and 44, respectively.
Using LKa and CLKb, the register 10 holds the latest data X (n) and the register 12 stores the data X (n−
When 2) is held, the coefficient value B2 is sent from the multiplexer 43 to the multiplier circuit 22, and the coefficient value B3 is sent from the multiplexer 44 to the multiplier circuit 23.
Register 11 holds the latest data X (n) and registers 1
When 3 holds data X (n-2), the coefficient value B3 is sent from the multiplexer 43 to the multiplication circuit 22 and the coefficient value B2 is sent from the multiplexer 44 to the multiplication circuit 23.

Of the arithmetic circuits, the sum circuit 30 is the same as the conventional one. That is, the summation circuit 30 includes the multiplication circuits 20 to
In order to take the sum of the calculated values of 23, for example, a two-input addition circuit 31 that inputs the output of the multiplication circuit 20 and the output of the multiplication circuit 21, the output of the multiplication circuit 22 and the multiplication circuit 2
And a two-input adder circuit 3 for inputting the outputs of the two adders 31 and 32.
3 and so on. The output of the multiplication circuits 20 to 23 is 2 × m
Corresponding to the bits, the outputs of the adders 31 and 32 are 2 × m + 1 bits, and the output of the adder 33, that is, the product-sum operation value Y (n) is 2 × m + 2 bits.

The usage and operation of the FIR filter of the first embodiment will be described with reference to the drawings. FIG. 3 is a timing chart showing an operation state of the filter circuit.

When the data X is sequentially sent from the pre-circuit 9 in synchronization with the clock CLK (see FIGS. 3A and 3B), that is, the data X (n-3) is sequentially output at the rise of the clock CLK. , Data X (n−2), data X (n−
1) When the data X (n) is input, the clocks CLKa and CLKb are inverted each time (see FIGS. 3 (c) and 3 (d)), and the data X (n) rises twice when the clock CLKb rises.
(N-3) is latched by the register 13 via the register 11 (see FIGS. 3F and 3H). Further, the data X (n-1) is latched in the register 11 at one rising of the clock CLKb (see FIG. 3F).

Further, although the clock CLK is shifted by one clock, the data X is shifted by two rises of the clock CLKa.
(N-2) is latched by the register 12 via the register 10 (see FIGS. 3E and 3G). Further, the data X (n) is latched in the register 10 at one rising of the clock CLKa (see FIG. 3E). In this manner, the data X is alternately distributed into two streams, sequentially input, and sequentially forwarded in each stream.

At the same time, each time the clock CLK rises, the multiplexer 41 alternately selects the coefficient value B0 or the coefficient value B1 (see FIG. 3 (i)), and the multiplexer 42 alternately selects the coefficient value B1. Alternatively, the coefficient value B0 is selected (see FIG. 3 (j)), the coefficient value B2 or the coefficient value B3 is alternately selected by the multiplexer 43 (see FIG. 3 (k)), and the coefficient value B3 or the coefficient value is alternately selected by the multiplexer 44. The numerical value B2 is selected (see FIG. 3 (l)).

Then, data X (n) to X (n-
3) is held in the registers 10 to 13 respectively, the multiplier circuit 20 calculates B0 × X (n) (see FIG. 3 (m)), and the multiplier circuit 21 calculates B1 × X
(N-1) is calculated (see FIG. 3 (n)), and the multiplication circuit 2
2 is used to calculate B2 × X (n−2) (FIG. 3 (o)).
B3 × X (n−3) is calculated by the multiplication circuit 23 (see FIG. 3 (p)). Further, the sum is obtained by the sum circuit 30.

In this way, the sum-sum circuit 30 calculates the product-sum operation value Y (n) = ｛B0 × X (n) + B1 × X (n-1) + B
2 × X (n−2) + B3 × X (n−3)} is output. This value is an appropriate product-sum operation value of the multiple data X and the count groups B0 to B3. In addition, although the detailed description is omitted, an appropriate multiply-accumulate operation is repeatedly performed in synchronization with the clock CLK. In addition, during the operation, each of the registers 10 to 13 of the data holding circuit
It operates in synchronization with LKa and CLKb.

Each of these registers uses m flip-flops, and each flip-flop generally includes several or more than ten transistors. And the switching operation of those transistors supports the latch operation of the corresponding register,
Generally, in a digital circuit, particularly in a CMOS circuit, power consumption by a transistor is concentrated at the time of switching. Therefore, the power consumption of the data holding circuits 10 to 13 is almost halved. As a result, even if the increase in power consumption due to the introduction of the coefficient value selection circuit 40 is considered, the power consumption of the entire FIR filter is reduced.

[0031]

Second Embodiment A second embodiment of the FIR filter according to the present invention will be described with reference to the drawings. 4A is a schematic circuit diagram, FIGS. 4B to 4D are examples of clock waveforms, and FIG. 5 is a detailed circuit diagram.

The FIR filter differs from that of the first embodiment in that the multiplexers 42 and 44 of the coefficient value selection circuit 40 are diverted to the data selection circuit, and the arithmetic circuit holds the intermediate calculated value. The point is that the circuit 50 is added. With these modifications, the multiplication circuits 21 and 23 are omitted from the arithmetic circuit. Multiplication circuits 20, 22
Remains.

The multiplexer 42 receives the data held in the register 10 in the first stream and the data held in the register 11 in the second stream, and receives, for example, the clock CLKa.
When the register 10 holds the latest data X (n) and the coefficient value B0 is sent from the multiplexer 41 to the multiplying circuit 20, the register 1
The held data of 0 is sent to the multiplying circuit 20, and when the coefficient value B1 is sent from the multiplexer 41 to the multiplying circuit 20, the held data of the register 11 is sent to the multiplying circuit 20. The multiplexer 44 receives the data held in the register 12 in the first stream and the data held in the register 13 in the second stream, and also performs selection switching according to the clock CLKa and the like. Is sent to the multiplication circuit 22, the data held in the register 12 is sent to the multiplication circuit 22, and the coefficient value B3
Is sent to the multiplier circuit 22. Such a multiplexer 42,
The data selection circuit 44 includes data holding circuits 10 to
In response to the distribution of data into a plurality of streams in step 13, some data are selected from the plurality of data toward a product-sum operation.

The intermediate calculated value holding circuit 50 holds the intermediate calculated value during the product-sum operation, and holds a register 51 for holding the calculated value of the multiplying circuit 20 and a calculated value of the multiplying circuit 22. And a register 52 are provided. Each of them is a 2 × m bit register. By latching the corresponding multiplication value at the rising edge of the clock CLK,
The disappearance of the value is delayed by one clock with the clock CLK. The intermediate calculation value held by the intermediate calculation value holding circuit 50 is sent to the summation circuit 30 in parallel with the latest intermediate calculation value by the multiplication circuits 20 and 22, and is used for the summation operation. .

The mode of use and operation of the FIR filter of the second embodiment will be described with reference to the drawings. FIG. 6 is a timing chart showing an operation state of the filter circuit.

Also in this case, each clock CLK, CLK
a, CLKb and the distribution and forward transmission of data X by the data holding circuits 10 to 13 are the same as those in the first embodiment (see FIGS. 6A to 6H). The same applies to the selection of coefficient values from the count groups B0 to B3 by the multiplexers 41 and 43 (see FIGS. 6 (i) and 6 (k)), but the multiple data X (n) to data X (n−) by the multiplexers 42 and 44. The data selection from 3) is different (FIG. 6).
(See (j) and (l)).

That is, the data X (n-
When 1) is latched, the clock CLK immediately after that is latched.
In one clock period, the coefficient value B1 is selected by the multiplexer 41 (see FIG. 6 (i)), and the data X (n-1) is selected by the multiplexer 42 (see FIG. 6 (j)). , Their multiplied values B1 × X (n
-1) is output from the multiplication circuit 20 (see FIG. 6 (m)). At the same time, the register 13
When the data X (n−3) is latched in
During the clock period, the multiplexer 43 selects the coefficient value B3 (see FIG. 6 (k)), and the multiplexer 44 selects the data X (n-3) (see FIG. 6 (l)). Multiplied value B3 × X (n−
3) is output from the multiplication circuit 22 (see FIG. 6 (n)).

When one clock period has passed and the next one clock period starts with the clock CLK, the intermediate calculated values B1 × X (n−1) and B3 × X (n−3) become
The registers are latched by the registers 51 and 52, respectively, and are maintained in a state where they can be referred to in the next one clock period (FIG. 6).
(See (o) and (p)). At the same time, when the data X (n) is latched in the register 10 and the data X (n−2) is latched in the register 12 at the same time, the multiplexer 4
A coefficient value B0 is selected by 1 (see FIG. 6 (i)), data X (n) is selected by the multiplexer 42 (see FIG. 6 (j)), and their multiplication value B0 × X (n) is multiplied by the multiplication circuit 20. (See FIG. 6 (m)), the coefficient value B2 is selected by the multiplexer 43 (see FIG. 6 (k)), and the data X (n-2) is selected by the multiplexer 44 (see FIG. 6 (l)). )) The multiplied value B2 × X (n−2) is output from the multiplying circuit 22 (see FIG. 6 (n)).

Then, the intermediate calculation value B0 × X (n) from the multiplication circuit 20 and the intermediate calculation value B
1 × X (n−1) and the intermediate calculation value B from the multiplication circuit 22
2 × X (n−2) and the intermediate calculated value B from the register 52
3 × X (n−3) are sent to the summation circuit 30 at the same time. Then, from the summation circuit 30, the product-sum operation value Y (n) =
｛B0 × X (n) + B1 × X (n−1) + B2 × X (n
−2) + B3 × X (n−3)} is output (FIG. 6).
(Q)). Thus, also in this example, an appropriate product-sum operation value of the plurality of data X and the count groups B0 to B3 is obtained.

Moreover, in this case, the data holding circuits 10 to 10
In addition to almost halving the power consumption at 13, the number of multiplication circuits included in the arithmetic circuit is halved. Then, looking at that part, the circuit scale is reduced to almost half and the power consumption is also reduced to almost half. Since the multiplication circuit generally has a large circuit scale, the effect of the reduction is more than compensated for by an increase in the circuit scale due to the addition of a multiplexer for selecting a coefficient value or data or the addition of a register for holding an intermediate calculated value. In addition, the combined effect of the power consumption reduction effects exceeds the increase in power consumption due to the introduction of the selection circuit 40 and the intermediate calculated value holding circuit 50. Therefore, in this FIR filter, not only power consumption but also circuit scale is reduced.

[0041]

[Others] In each of the above embodiments, the digital data X is distributed into two sequences. However, the distribution destination sequence is not limited to two sequences and may be three or more multi-lines. . In this case, the data holding circuits 10 to 13 increase the parallel number of the series in which the registers are cascade-connected, and divide the clock CLK by the number of the series, thereby distributing the same number of distribution clocks having different phases. It is good to derive and distribute to the registers of each series. In addition, as for the coefficient value selection circuit 40, the number of coefficient values to be selected may be increased in accordance with the number of series.
Each of the multiplexers 41, 42, etc., has three inputs and one output, and the coefficient values to be selected include:
“B0, B1, B” obtained by dividing the counting group into a subset of three elements
2 "," B4, B5, B6 "and the like. And
As the number of streams increases, the power consumption of the data holding circuit decreases.

Further, in each of the above embodiments, each register or flip-flop performs the latch operation at the rising edge of the clock. However, the present invention is not limited to this, and it operates at the rising edge of the clock or at the falling edge. May be determined for each register.

Further, in each of the above embodiments, the case where the number of bits m of the data X is "4" and the order k of the filter is "3" has been described. However, m and k are not limited thereto. Any of them is arbitrary as long as it is 2 or more. When the order k is large, for example, when the order k exceeds “1000”, the ratio of the FIR filter to all the circuits of the device is large, and the effect of reducing the power consumption of the data holding circuit is large.

Further, in each of the above embodiments, the number of bits increases in the later stages in the circuit so that the accuracy does not deteriorate at all with the operation, but the product-sum operation value Y (n)
In the case where is rounded to m bits or the like, or when some degree of precision deterioration is allowed during the calculation, the number of bits in the subsequent stage may be reduced.

In the second embodiment, each count value B
Under the condition that all 0 to B3 may be different, the number of multipliers can be reduced. In the FIR filter, B (i) = B (ki) between each count value. In many cases, such a specific relationship holds, and if the characteristics of such a counting group are used, the number of multiplier circuits can be further reduced.

[0046]

As is apparent from the above description, in the FIR filter according to the first solving means of the present invention, the data holding circuit is designed so that the sequential data transfer is performed only in the sequence part of the distribution destination. In addition, the lack of sequential data transfer is compensated by the selection switching of the coefficient value for the product-sum operation, so that the clock frequency of the data holding circuit is higher than the frequency at which the digital data is sequentially transmitted. There is an advantageous effect that a low FIR filter can be realized.

In the FIR filter according to the second solving means of the present invention, not only the switching of the coefficient value but also the switching of the data are performed based on the distribution of data into a plurality of streams. An advantageous effect is obtained that an FIR filter in which the clock frequency of the data holding circuit is lower than the frequency at which digital data is sequentially transmitted, and in which the number of multiplying circuits is small can be realized.

[Brief description of the drawings]

FIG. 1A is a schematic circuit diagram of a first embodiment of an FIR filter of the present invention, and FIG. 1B is an example of a circuit for generating a derived clock. Fig. 4 shows an embodiment of the FIR filter of the present invention.

FIG. 2 is a detailed circuit diagram thereof.

FIG. 3 is a timing chart showing the operation state.

FIG. 4A is a schematic circuit diagram of a second embodiment of the FIR filter of the present invention, and FIGS. 4B to 4D are examples of clock waveforms.

FIG. 5 is a detailed circuit diagram thereof.

FIG. 6 is a timing chart showing the operation state.

7A is a schematic circuit diagram and FIG. 7B is a detailed circuit diagram of a conventional FIR filter.

[Explanation of symbols]

10 to 13 Data holding circuit 10, 12 Register (latch, first series part in data holding circuit) 11, 13 Register (latch, second series part in data holding circuit) 20 to 23 Multiplication circuit (product part, Arithmetic circuit) 30 Summation circuit (sum section, arithmetic circuit) 31-33 Addition circuit 33 (addition circuit, summation circuit, summation circuit) 40 Coefficient value selection circuit (data selection circuit) 41, 43 Multiplexer (MUX, selector, Coefficient value selection) 42, 44 Multiplexer (MUX, coefficient value selection / data selection) 50 Intermediate calculated value holding circuit 51, 52 Register (latch) B0-B3 Count group (coefficient value) CLK Basic clock (data transmission clock) CLKa Normal-phase clock (divided clock, distribution-derived clock) CLKb Negative-phase clock (divided clock, distribution-derived clock) X data (input data, digital data) Y product-sum operation value (output data)

Claims (2)

[Claims] 1. A data holding circuit for sequentially inputting digital data while distributing the data into a plurality of streams, sequentially feeding and holding a plurality of data, and calculating a product-sum operation value of the plurality of data and a predetermined coefficient group. An FIR filter comprising: an arithmetic circuit for selecting a coefficient value from the coefficient group corresponding to the distribution. 2. The method according to claim 1, wherein said arithmetic circuit also selects data from said plurality of data corresponding to said distribution at the time of a product-sum operation and holds an intermediate calculated value during said product-sum operation. Item 1. An FIR filter according to Item 1.