JP2928072B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to a delta sigma A / D converter in the audio field.

[0002]

2. Description of the Related Art A conventional delta-sigma A / D converter has a delta-sigma modulator 21 having a signal input as an input and an oversampling output of the delta-sigma modulator 21 as an input, as shown in FIG. A first decimation circuit 22 that sets an intermediate sampling frequency without thinning directly from the oversampling frequency to the final sampling frequency, and a second decimation circuit that receives an output of the first decimation circuit 22 as an input and thins the final sampling frequency. And the output of the second decimation circuit 23 is used as a signal output (for example,
Oversampling A / D conversion technology, P104, FIG.
6,1990.12.25, Nikkei BP, Akira Yukawa).

Next, the operation of the conventional A / D converter will be described.

A delta-sigma modulator 21 samples an analog signal at an intermediate frequency (nfs) which is n times higher than a final sampling frequency (fs), and performs A / D conversion of 1 to 4 bits. Further, the first decimation circuit 22 receives a digital signal of 1 to 4 bits of nfs, performs digital filter processing (an example of frequency characteristics is shown in FIG. 6) and decimation processing, and performs m bits of 2 fs to 4 fs. (Usually m = 16 to 20) in the audio field.

Further, referring to FIG. 5 showing an example of the configuration of the second decimation circuit and FIG. 7 showing the frequency characteristics thereof, the second decimation circuit 23 has a frequency of 2 fs.
４4fs, an m-bit digital signal is input, and digital filter processing and decimation processing are performed.
An s m-bit digital signal is output. The frequency characteristic of the second decimation circuit 23 is determined by the data of the coefficient ROM 52 for performing the convolution.

Further, referring to FIG. 3, if it is desired to perform equalization processing of low-frequency emphasis or high-frequency emphasis on the output 24 of the A / D converter, the output 24 of the A / D converter 31 is converted to a digital signal processor. 32, and the control signal 34 controls the digital signal processor 32 to obtain a desired output 33.

As shown in FIG. 4, the digital null processor 32 has an external bus control unit 206 and a data bus 209, one of which is connected to the control input / output 201 and the other is connected to the data bus 209. A data ROM 208, an instruction ROM 209, and a data RAM 221 connected thereto, a decoder 211 to which the data bus 209 is input, an address pointer 212 to which an output of the decoder 211 is input, and a coefficient RAM 222 to which an output of the address pointer 212 is input. A multiplier 223 having the output of the coefficient RAM 222 as one input and the other input as a data bus 209, a second latch 226 having an output of the multiplier 223 as an input, and a first latch having a data bus 209 as an input. The latch 224 and the first latch 224 are used as one input and the other input is used. The ALU of the second latch 226
An accumulator 228 having an output of the accumulator 225 as an input, a third latch 227 having an output of the accumulator 228 as an input and an output connected to the data bus 209, and an output interface having the data bus 209 as an input and an output as a signal output 202. 205, and an input interface 204 having an input signal 203 as a signal output and an output connected to a data bus.

The equalizing process is realized by rewriting the coefficient RAM 222 from the control input / output 201 via the data bus 209 and rewriting the data in the instruction ROM 207.

[0009]

However, in this conventional A / D converter, it is necessary to connect a digital signal processor in order to perform an equalizing process, and since the circuit scale of the digital signal processor is large, a system circuit is not provided. There is a drawback that the scale is increased and the cost is significantly increased.

[0010]

An A / D converter according to the present invention comprises: a delta-sigma modulator which receives an analog signal;
The oversampling frequency output having the predetermined frequency and the oversampling frequency output having the predetermined frequency are decimated from the oversampling frequency output to have a final sampling frequency output having a desired frequency. 1st decimation circuit to set and intermediate frequency with value
A second decimation circuit for thinning out the output of the first decimation circuit to output the final sampling frequency output, and for inputting a control input signal and setting a low or high sampling frequency of the second decimation circuit. A filter function selection circuit for performing equalization processing ,
The first decimation is added to the second decimation circuit.
Receiving the output of the application circuit as a first input,
The output of the function selection circuit is input as the second input and the
This is a configuration for converting a log signal into a digital signal.

Further, the second decimation circuit of the A / D converter according to the present invention is characterized in that the second decimation circuit receives the data RA which receives the first input.
M, a multiplier receiving the output of the data RAM as a third input, the second input as a fourth input, and receiving each of the third and fourth inputs, and a second input receiving the output of the multiplier. 1, the second latch circuit, the output of the first latch circuit as a fifth input, the output of the second latch circuit as a sixth input, and the fifth and sixth inputs. An adder that receives the signals; and a third latch circuit that receives an output of the adder as an input. The output of the adder is input to the second latch circuit, and the output of the third latch circuit is output as a signal. An output configuration can also be used.

Still further, the filter function selection circuit of the A / D converter of the present invention includes a decoder for receiving the control input signal, an address pointer for receiving an output of the decoder, and a first for receiving an output of the address pointer. , Second
And a third coefficient ROM, wherein the output of the coefficient ROM is selected by the output of the address pointer, and this output is used as the second input.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an A / D converter according to one embodiment of the present invention.

An A / D converter according to one embodiment of the present invention includes a delta-sigma modulator 11 having a signal input 10 as an input, a first decimation circuit 12 having an output of the delta-sigma modulator 11 as an input, A filter function selection circuit 15 having a control input 16 as an input, and a second decimation circuit 13 having a first decimation circuit 12 as a first input 115 and an output of the filter function selection circuit 15 as a second input 116 In this configuration, the output of the second decimation circuit 13 is used as the signal output 14.

The above-mentioned filter function selection circuit 15
Is a decoder 111 having a control input 16 as an input, and an address pointer 112 having an output of the decoder 111 as an input.
Coefficient ROM 122 and second coefficient ROM 114 which receive the output of address and address pointer 112, respectively.
And a third coefficient ROM 113, and the output of the address pointer 112 is used as a second input 116.

The second decimation circuit 13 has a data RAM 121 having a first input 115 as an input, a fourth input 118 via a second input 116, and a data RA 121.
Multiplier 123 using output of M121 as third input 117
And the first latch 12 receiving the output of the multiplier 123 as an input.
4 and the output of the first latch 124 as the fifth input 119 and the output of the second latch 126 as the sixth input 120
, A second latch 126 receiving the output of the adder 125 as an input, and a third latch 127 receiving the output of the adder 125 as an input.
7 is used as the signal output 14.

Next, the operation of the A / D converter of this embodiment will be described.

In the delta-sigma modulator 11, the analog signal 10 is sampled at a frequency (nfs) which is n times higher than the final sampling frequency (fs).
In addition, A / D conversion of 1 to 4 bits is performed. The first decimation circuit 12 receives a digital signal of 1 to 4 bits of nfs and performs digital filter processing (an example of frequency characteristics is shown in FIG. 6) and decimation processing to perform m bits of 2 fs to 4 fs (audio field). Usually outputs a signal of m = 16 to 20). The frequency characteristic of the second decimation circuit 13 is determined by the data of the coefficient ROM (122, 113 or 114) for performing the convolution.

Further, the filter function selection circuit 15 of the A / D converter of the present invention decodes the control input 16 by the decoder 111, controls the address pointer 112 by the output, and controls the first coefficient ROM 122 and the second coefficient ROM 122. Coefficient ROM1
14 or the third coefficient ROM 113 is selected. First coefficient ROM 122, second coefficient ROM 114
In the third coefficient ROM 113, for example, coefficient data for realizing a filter function as shown in FIG. 7, FIG. 8, or FIG. 9 is stored, and the selected coefficient is stored in the multiplier 123 of the second decimation circuit 13. And a digital filter process is performed. Further, the third latch 127 performs decimation and outputs the result.
As described above, the equalizing process is realized by changing the frequency characteristics of the second decimation circuit 13 by the filter function selection circuit 15.

As described above, the first coefficient ROM 12
2, the second coefficient ROM 114 and the third coefficient ROM 1
An A / D converter having an equalizing function can be realized by adding a circuit having a small number of control inputs to a filter function selection circuit constituted by the address function control circuit 13 and the address pointer 112 and the decoder 111.

Comparing FIGS. 3 to 5 with FIG. 1, the reduction in circuit size is apparent.

[0023]

As described above, the present invention provides a delta-sigma modulator having a signal input as input, a first decimation circuit having an output of the delta-sigma modulator as input, and a decoder having a control input as input. A filter function selection circuit having an input of an output of the decoder, a decimation circuit having a first decimation circuit as a first input, and an output of the filter function selection circuit as a second input. As a result, the filter function of the second decimation filter can be selected, so that an A / D converter having an equalizing function can be realized by adding a small number of circuits.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an A / D converter according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a conventional A / D converter.

FIG. 3 is a block diagram in which a digital signal processor is connected to a conventional A / D converter.

FIG. 4 is a block diagram of one configuration example of an internal block diagram of a digital signal processor.

FIG. 5 is a block diagram of a second decimation filter in a conventional A / D converter.

FIG. 6 is a diagram illustrating an example of a frequency characteristic of a first decimation filter.

FIG. 7 is a diagram illustrating an example of a frequency characteristic of a second decimation filter.

FIG. 8 shows a frequency characteristic (within a signal band) of the second decimation filter of the A / D converter according to one embodiment of the present invention.
It is a figure showing an example of.

FIG. 9 shows a frequency characteristic (within a signal band) of the second decimation filter of the A / D converter according to one embodiment of the present invention.
It is a figure showing other examples of.

[Explanation of symbols]

10, 20, 65, 203 Signal input 11, 21 Delta-sigma modulator 12, 22, First decimation circuit 13, 23 Second decimation circuit 14, 24, 33, 64, 202 Signal output 15 Filter function selection circuit 16, 34,201 control input 32 digital signal processor 51,121,221 data RAM 52,113,114,122,222 coefficient ROM 53,123 multiplier 54,56,57,124,126,127 latch 55,125 adder 67 , 68, 69, 70, 115, 116, 117, 1
18, 119, 120 inputs 111, 211 decoder 112, 212 address pointer

Claims (1)

(57) [Claims] 1. A delta-sigma modulator for performing an A / D conversion by oversampling an analog signal at an oversampling frequency higher than a final sampling frequency, receiving an output of the delta-sigma modulator, and receiving the output from the delta-sigma modulator A first decimation circuit for thinning out to an intermediate frequency between the frequency and the final sampling frequency, and a second decimation circuit for receiving the output of the first decimation circuit and thinning out the output to the final sampling frequency And a filter function selection circuit for selectively changing a frequency characteristic of the second decimation circuit, wherein the filter function selection circuit comprises:
A plurality of coefficient ROMs, and means for selecting any one of the plurality of coefficient ROMs based on a control input signal, wherein the selection of the plurality of coefficient ROMs is switched based on the control input signal to form the second coefficient ROM. An A / D converter characterized by selectively changing a frequency characteristic of a decimation circuit so as to obtain an A / D conversion output in which a low band or a high band is equalized.